JPH08204527A - Delay reset circuit - Google Patents

Abstract

PURPOSE: To simplify the circuit while having sufficient accuracy. CONSTITUTION: A reference voltage generating circuit 2 generates a reference voltage V2 depending on a power supply voltage VIN. A charge current generating circuit 3 generates a charge current Id proportional to the reference voltage V2 . A comparator 11 compares the reference voltage V2 with the voltage of a delay time setting capacitor Cd charged by the charge current Id to provide a signal of the comparison result. When the power supply voltage VIN. is smaller than the threshold voltage, a voltage monitor circuit 12 discharges the capacitor Cd and when the power supply voltage VIN is higher than the threshold voltage, the voltage monitor circuit 12 stops discharging the capacitor Cd . An output circuit 13 generates an output voltage VRO commanding reset when the voltage of the capacitor Cd is smaller than the reference voltage V2 , and generates an output voltage VRO to command release of reset when the voltage of the capacitor Cd is more than the reference voltage V2 .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay reset circuit, and more particularly to a delay reset circuit which releases a signal instructing reset by delaying a set time from the time when a power supply voltage reaches a threshold voltage.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional delay reset circuit 20. The delay reset circuit 20 is configured as, for example, an integrated circuit formed on the same semiconductor chip. The delay reset circuit 20 includes constant current sources 21 and 2.
2, reference voltage source 23, delay time setting capacitor C _d ,
It is composed of a comparator 11 having a hysteresis characteristic, a voltage monitoring circuit 12, an output transistor Q _O, and an output circuit 13 including an output resistance R _L.

The GND terminal is grounded and the power supply terminal T
_The input power supply voltage V _IN is supplied to _VIN . From the negative logic reset output terminal (RESET *), the low level (0
At V), an output signal (output voltage V _RO ) instructing reset is output. The constant current source 21 supplies the constant current I _Z to the reference voltage source 23. The constant current source 22 supplies a constant current I _d that does not depend on the power supply voltage V _IN to the capacitor C _d .

The comparator 11 compares the reference voltage V _Z supplied to the plus input terminal with the voltage (charging voltage) V _Cd of the plus electrode of the capacitor C _d , and the voltage at the plus input terminal is lower than the voltage at the minus input terminal. When it is large, a positive output voltage is generated, and when the voltage at the positive input terminal is less than or equal to the voltage at the negative input terminal, an output voltage of about 0 V is generated.

The voltage monitoring circuit 12 compares the power supply voltage V _IN with the set threshold voltage V _TH, and discharges the capacitor C _d when the power supply voltage V _IN is smaller than the threshold voltage V _TH. , The voltage V _Cd (that is, the charging voltage) of the positive electrode of the capacitor C _d is maintained at V _Cd = 0. Voltage monitoring circuit 12
Stops the discharge of the capacitor C _d when the power supply voltage V _IN is equal to or higher than the threshold voltage V _TH . The charging of the capacitor C _d is started by the constant current I _d from the time when the discharging of the capacitor C _d is stopped. The threshold voltage V _TH is set to a value that is considered to have lowered the power supply voltage V _IN below the allowable value, corresponding to the power supply voltage V _IN in the steady state.

The output transistor Q _O is the comparator 1
It turns on when 1 produces a positive output voltage. At this time, the collector current of the transistor Q _O changes to the output resistance R _L.
Then, the output voltage V _RO becomes 0 V which is a level (reset level) instructing reset. Comparator 1
When the output voltage of 1 is 0 V and the transistor Q _O is off, the output voltage V _RO is the H level (= power supply voltage V _IN ) which is the level (reset release level) for instructing reset release.
Becomes

This output voltage V _RO is supplied to the reset input terminal of the circuit that requires resetting when the power supply voltage V _IN drops below the threshold voltage V _TH . Next, a detailed operation of the delay reset circuit 20 will be described. FIG. 4 is an explanatory diagram of the relationship between the power supply voltage V _IN and the output voltage V _RO when the power is turned on. FIG. 4 (A) shows a time variation of the supply voltage V _IN from the power-on time, the power supply voltage V _IN in a steady state is V _IN = V _INA and _{V IN = V INB (V INB} > V INA. ). In FIG. 4A, the case of V _INA is shown by a solid line, and the case of V _INB is shown by a broken line.

FIG. 4B corresponds to FIG. 4A and shows the time change of the output voltage V _RO from the time when the power is turned on. FIG.
In (B), the output voltage V _ROA when V _IN = V _INA is shown by a solid line, and the output voltage V _ROB when V _IN = V _INB is shown by a broken line. Now, the case where the power supply voltage V _IN = V _{INA in} the steady state is described. As shown in FIG. 4A, when the power is turned on at time t = 0, the power supply voltage V _IN rises linearly with time, and at t = t _{S, the} steady-state voltage V _IN = V _IN = V _IN
Has reached _INA .

[0009] between the time t until 0~t _LA, the power supply voltage V
_The delay reset circuit 20 does not operate because _IN does not reach the operation limit voltage V _LM (about 0.8 V). Therefore, the output voltage V _{RO A} rises similarly to the power supply voltage V _IN as shown in FIG. 4 (B). From the time the V _IN reaches V _IN = V _LM at time t = t _LA, delayed reset circuit 20 becomes operable.
The constant current sources 21 and 22 generate constant currents I _Z and I _d , and the reference voltage source 23 starts generating the reference voltage V _Z. The reference voltage V _Z is set to, for example, about 1 V, and the constant current I _Z is supplied to generate the steady-state reference voltage V _Z immediately after the time t _LA . The comparator 11 normally performs the operation of comparing the voltages of the positive input terminal and the negative input terminal.

The threshold voltage V _TH has a sufficiently large value with respect to V _LM . Therefore, when the delay reset circuit 20 starts operating at time t = t _LA , the power supply voltage V _IN <V
_TH . At this time, the voltage monitoring circuit 12, to discharge the capacitor C _d, keep the voltage V _Cd positive electrode of the capacitor C _d in V _Cd = 0. On the other hand, the reference voltage source 23 generates the reference voltage V _Z having a substantially normal value. Therefore, the comparator 11 generates a positive output voltage, the transistor Q _O is turned on, and the output voltage V _ROA = 0 V (reset level).

Power supply voltage V_INFurther increases, and time t = t
_TAAnd V_IN= V_THThe voltage monitoring circuit 12 reaches the
Densa C_dTo stop the discharge. Conden from this point
SA C _dConstant current I_dWill start charging. Power-supply voltage
V_INIs the threshold voltage V_THOutput voltage V_ROA
Indicates reset release from reset level (0V)
Time until reaching H level, that is, delay time t_dIs
It is calculated as below.

This delay time t_dIs the capacitor C_dCharge of
Electric voltage V_CdIs the reference voltage V_ZIn the charging time until it matches
is there. Therefore, the following equation (1) is established. Note that the conden
SA C _dCapacity of C_dShall be V_Cd= (I_d・ T_d) / C_d= V_Z (1) From equation (1), delay time t_dIs sought
Be done.

T_d= (C_d・ V_Z) / I_d (2) As shown in FIG. 4 (B), time t_TAAnd V_IN= V_THReached
Delay time t _dOutput voltage V
_ROAVoltage from 0V to H level (reset release level)
(= V_INA), And the reset instruction is released. What
Power supply voltage V_INIs a steady value V_INAReached stable enough
The reset instruction is released after the_d
The value of is set.

Power supply voltage V_IN= V_INBIn case of, V_IN= V
_INAPower supply voltage V_INHas risen sharply
Therefore, the power supply voltage V_INIs the operating limit voltage V_LMTime t_LB
And the power supply voltage V_INIs the threshold voltage V_THTime t_TBIs
V_IN= V_INAIt will be earlier than the case of. That is, t
_LB<T_LA, T_TB<T_TABecomes Delay time t_dThe origin of
Time t_TBIs. On the other hand, the delay time t_dIn the above equation (2)
As shown, the power supply voltage V _INConstant value regardless of the value of
Become. Therefore, as shown by the broken line in FIG.
Voltage V_ROBIs 0V to H level (reset release level)
Becomes V _IN= V_INAAnd the time is earlier than
It

Next, consider a case where the power supply voltage V _IN is below the threshold voltage V _TH for some reason while the power supply voltage V _IN is in a steady state. In this case, the voltage monitoring circuit 12 detects that the power supply voltage V _IN has dropped below the threshold voltage V _TH ,
Discharge the capacitor C _d . With this, in an extremely short time,
V _Cd = 0V. Therefore, the power supply voltage V _IN is equal to the threshold voltage V
Immediately after falling below _TH , the output voltage V _RO changes from H level to 0 V.
Then, the delay reset circuit 20 enters the reset instruction state. Thereafter, when the power supply voltage V _IN is recovered above the threshold voltage V _TH, the voltage monitoring circuit 12 stops the discharge of the capacitor C _d, the charging of the capacitor C _d is started. This allows
In the same manner as when the power is turned on, the output voltage V _RO changes from 0 V to the H level after the delay time t _d has elapsed from the point of time when the power supply voltage V _IN was restored, and the delay reset circuit 20 enters the reset instruction release state.

[0016]

In the conventional delay reset circuit 20, the reference voltage source 23 for generating the reference voltage V _Z which does not depend on the power source voltage V _IN is a complicated circuit which requires about 6 transistors. Further, the constant current sources 21 and 22 are also complicated circuits having about 6 transistors. For this reason,
The delay reset circuit 20 has a problem that the circuit becomes complicated and the entire circuit scale becomes large.

The present invention has been made in view of the above points, and an object of the present invention is to provide a delay reset circuit which has a sufficient accuracy and can be simplified.

[0018]

A delay reset circuit of the present invention comprises a reference voltage generating circuit for generating a reference voltage dependent on an input power supply voltage, and a charging current generating circuit for generating a charging current proportional to the reference voltage. Comparing the charging voltage of the delay time setting capacitor charged by the charging current and the reference voltage, comparing circuit for outputting a signal of a comparison result, and comparing the input power supply voltage and the threshold voltage, A voltage monitoring circuit that discharges the delay time setting capacitor when the input power supply voltage is lower than the threshold voltage, and stops discharging the delay time setting capacitor when the input power supply voltage is equal to or higher than the threshold voltage. When the comparison result signal is supplied from the comparison circuit and the charging voltage of the delay time setting capacitor is lower than the reference voltage, an instruction to reset is output. It generates a signal, if the charging voltage setting capacitor said delay time is equal to or greater than the reference voltage, a structure and an output circuit for generating an output signal indicative of the reset release.

[0019]

In the delay reset circuit of the present invention, the delay time from when the input power supply voltage reaches the threshold voltage or more to when the output signal changes from the signal instructing reset to the signal instructing reset release is the delay time. It depends on the charging time to charge the setting capacitor to the reference voltage.

According to the present invention, since the charging current changes in proportion to the reference voltage which changes according to the input power supply voltage, the delay time which does not depend on the value of the input power supply voltage can be obtained. As a result, the reference voltage does not need to be a constant voltage and the charging current does not need to be a constant current. Therefore, the reference voltage generation circuit that generates the reference voltage and the charging current generation circuit that generates the charging current are simplified circuits. Can be composed of

Therefore, the circuit can be greatly simplified as compared with the conventional delay reset circuit which requires the reference voltage source and the constant current source which do not depend on the input power source voltage.

[0022]

1 is a circuit diagram of a delay reset circuit 1 according to an embodiment of the present invention. In FIG. 1, the same components as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted as appropriate. The delay reset circuit 1 is configured as, for example, an integrated circuit formed on the same semiconductor chip.

The delay reset circuit 20 includes a reference voltage generation circuit 2, a charging current generation circuit 3, a delay time setting capacitor C _d , a comparator (comparison circuit) 11 having a hysteresis characteristic, a voltage monitoring circuit 12, an output transistor Q _O, and The output circuit 13 is composed of an output resistor R _L.

The GND terminal is grounded and the power supply terminal T
_VINPower supply voltage V_INIs supplied. Negative logic reset
Low level (0V) from the output terminal (RESET *)
Output signal (output voltage V_RO) Is output
Is done. The reference voltage generation circuit 2 is a diode-connected NP.
N-type transistor Q₁, Resistance R ₁, R₂, Current Mira
-NPN type transistor Q that constitutes a circuit₂, Q₃, D
Mitter to reference voltage V₂Output NPN type transistor
Q_FiveConsists of

The diode-connected transistor Q ₁ , the resistors R ₁ and R ₂ , and the diode-connected transistor Q ₂ are connected in series between the power supply terminal T _VIN and the GND terminal to which the power supply voltage V _IN is supplied. The common emitters of the transistors Q ₂ and Q ₃ forming the current mirror circuit are grounded. The emitter area ratio of the transistors Q ₂ and Q ₃ is set to 1: 1. The base of the transistor Q ₅ is connected to the connection point of the resistors R ₁ and R ₂ , and the collector is the power supply terminal T
_It is connected to _VIN , and the emitter is connected to the collector of the transistor Q ₃ and the positive input terminal of the comparator 11. The reference voltage V ₂ is generated from the emitter of the transistor Q ₅ and is supplied to the plus input terminal of the comparator 11.

The charging current generating circuit 3 includes an NPN type transistor Q ₁ , resistors R ₁ and R ₂ , NPN type transistors Q ₂ and Q ₄ forming a current mirror circuit, and a transistor Q.
_It is composed of PNP type transistors Q ₆ and Q ₇ which are supplied with current from the collector of ₄ and constitute a current mirror circuit.

The emitter of the transistor Q ₄ forming a current mirror circuit with the transistor Q ₂ is grounded. The emitter area ratio of the transistors Q ₂ and Q ₄ is 1: 1.
Is set to The common emitters of the transistors Q ₆ and Q ₇ forming the current mirror circuit are connected to the power supply terminal T _VIN . The collector of the transistor Q ₆ is connected to the collector of the transistor Q ₄ . The emitter area of the transistor Q ₇ is set to N times that of the transistor Q ₆ . The collector of the transistor Q ₇ is connected to the positive electrode of the capacitor C _d and the negative input terminal of the comparator 11. The collector current of the transistor Q ₇ is generated as the charging current I _d of the capacitor C _d .

The power supply voltage V _IN becomes higher than the threshold voltage V _TH ,
When the voltage monitoring circuit 12 stops discharging the capacitor C _d , the charging current I _d starts charging the capacitor C _d . When V ₂ > V _Cd , the comparator 11
Generates a positive output voltage to turn on the transistor Q _O , and the output voltage V _RO becomes 0 V which is a level (reset level) instructing reset. When V ₂ ≦ V _Cd ,
When the output voltage of the comparator 11 is 0V, the transistor Q _O
Is turned off, and the output voltage V _RO becomes H level (= power supply voltage V _IN ) which is a level (reset cancellation level) instructing reset cancellation.

Next, the detailed operation of the delay reset circuit 1 will be described. Here, a case where the power supply voltage V _IN is a steady value will be described. When the current of the resistor R ₂ is I ₁ , the voltage V _{1 at} the connection point between the resistor R ₁ and the resistor R ₂ can be expressed by the following equation (3). V ₁ = V _BE2 + I ₁ · R ₂ (3) Further, the current I ₁ can be expressed by the following equation (4).

I ₁ = (V _IN −V _BE1 −V _BE1 ) / (R ₁ + R ₂ ) (4) where V _BE1 and V _BE2 are the transistors Q ₁ and
It is the base-emitter voltage of Q ₂ . Further, the voltage of the emitter of the transistor Q ₅ , that is, the reference voltage V ₂ can be expressed by the following formula (5) using the formula (3). Where V
_BE5 is the base-emitter voltage of the transistor Q _5.

V ₂ = V ₁ -V _BE5 = V _BE2- V _BE5 + I ₁ · R ₂ (5) The transistors Q ₂ and Q ₃ of the current mirror circuit have the emitter areas of 1: 1 and the collector currents are equal. The collector current of transistor Q ₂ is approximately equal to I ₁ . The collector current I ₅ of the transistor Q ₅ is substantially equal to the collector current of the transistor Q _3. For this reason, the collector current I ₅ of the transistor Q _5, the transistor Q ₂
Is almost equal to the collector current of, and I ₅ ≈I ₁ .
The transistors Q ₂ and Q ₅ are transistors formed on the same semiconductor chip and having the same characteristics. Therefore, V _BE2 ≈V _BE5 . Therefore,
From the equation (5), V ₂ can be expressed by the following equation (6).

V ₂ = I ₁ · R ₂ (6) Further, the transistors Q ₂ and Q ₄ of the current mirror circuit have an emitter area of 1: 1 and have equal collector currents. The collector current of transistor Q ₆ is approximately equal to the collector current of transistor Q ₄ . Transistor Q ₆ ,
Since the emitter area ratio of Q ₇ is N, the transistor Q
The collector current of ₇ , that is, the charging current I _d is given by the following equation (7).

I _d = N · I ₆ = N · I ₁ (7) The delay time t _d can be expressed by the following formula (8) as in the formula (2). t _d = (C _d · V ₂ ) / _Id (8) By substituting the expressions (6) and (7) into the expression (8), the following expression (9) is obtained.

T _d = (C _d · I ₁ · R ₂ ) / N · I ₁ = (C _d · R ₂ ) / N (9) As shown by the equation (9), the delay time t _d is It is determined only by the capacitance C _d of the capacitor C _d , the resistance R ₂ , and the emitter area ratio N, and does not depend on the power supply voltage V _IN .

Now, the power supply voltage V_INIs in a steady state
For some reason, the power supply voltage V_INIs the threshold voltage V_THBelow
Think about the case. In this case, the voltage monitoring circuit 12
Source voltage V_INIs the threshold voltage V_THIs detected below
Capacitor C_dTo discharge. With this, in an extremely short time,
V_Cd= 0V. Therefore, the power supply voltage V_INIs the threshold voltage V
_THImmediately below the output voltage V_ROIs from H level to 0V
(Reset instruction level), and the delay reset circuit 1
The reset instruction state is entered.

[0036] Thereafter, when the power supply voltage V _IN is recovered above the threshold voltage V _TH, the voltage monitoring circuit 12 stops the discharge of the capacitor C _d, the charging of the capacitor C _d in the charging current I _d which is determined by the equation (7) Is started. As a result, after the delay time t _d determined by the equation (9) elapses from the recovery of the power supply voltage V _IN ,
The output voltage V _RO changes from 0 V to the H level, and the delay reset circuit 1 enters the reset instruction release state. As mentioned above,
It is possible to obtain the delay time t _d that does not depend on the value of the power supply voltage V _IN .

The operation of the delay reset circuit 1 when the power is turned on is the same as that of the circuit of FIG. 3, and the time change of the power supply voltage V _{IN and} the time change of the output voltage V _RO from the time of turning on the power are as follows. It is similar to FIG. 4 (A) and FIG. 4 (B), respectively. That is, the output voltage V _RO changes from 0 V to the H level at the time point when t _d elapses from the time point when the power source voltage V _IN reaches the threshold voltage V _TH , and the reset instruction is released.

However, before the power supply voltage V _IN reaches the steady value, the charging current I _d becomes slightly smaller than the steady value, but compared with the time until the power supply voltage V _IN reaches the steady value from the threshold voltage V _TH. And the delay time t _d is sufficiently large, the delay time t
_There is almost no effect on the value of _d .

[0039] As described above, the delayed reset circuit 1 of this embodiment has the structure in which a change in the charging current I _d in proportion to the reference voltage V ₂ which changes the power supply voltage V _IN, the power supply voltage V _IN It is possible to obtain a delay time t _d that does not depend on the value of. The reference voltage V ₂ is not necessary to the constant voltage, the charging current I is not necessary to the constant current _d, the reference voltage generating circuit 2 and the charging current for generating the reference voltage V ₂ I _d
The circuit including the charging current generation circuit 3 for generating the voltage can be configured with a simple circuit including seven transistors and two resistors.

Therefore, the reference voltage source 23 and the constant current source 2
The circuit can be significantly simplified as compared with the conventional delay reset circuit 20 which requires about 6 transistors for each of 1 and 22. The emitter area ratio of the transistors Q ₂ and Q ₄ may be set to N, and the emitter area ratio of the transistors Q ₆ and Q ₇ may be set to 1: 1. Also, the transistor Q
_A PNP transistor or a diode may be used for ₁ .

FIG. 2 shows a circuit diagram of a delay reset circuit 1 _M as a modification of the delay reset circuit 1 according to the embodiment of the present invention. 2, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted as appropriate. In the delay reset circuit 1 _M of FIG. 2, a reference voltage generation circuit 2 _M and a charging current generation circuit 3 _M are provided instead of the reference voltage generation circuit 2 and the charging current generation circuit 3.

The delay time setting capacitor C _d is arranged between the power supply terminal T _VIN and the positive input terminal of the comparator 11 _M , and the charging current I _d generated by the charging current generation circuit 3 _M is supplied from the negative electrode of the capacitor C _d. Pour out. Further, the reference voltage generation circuit 2 _M supplies the reference voltage V _2M to the power supply terminal T _VIN.
And the negative input terminal of the comparator 11 _M.

The transistors Q _{1M to} Q _7M correspond to the transistors Q _{1 to} Q ₇ in the circuit of FIG. 1 and have the opposite polarities (relationship between NPN type and PNP type). The resistors R _1M and R _2M correspond to the resistors R ₁ and R ₂ . The current I _1M of the resistor R _2M corresponds to the current I ₁ .

The reference voltage generation circuit 2 _M is similar to the reference voltage generation circuit 2 in that the power supply terminal T _VIN and the comparator 11
_A reference voltage V _2M is generated between the negative input terminals of _M. Similar to the equation (6), the reference voltage V _2M can be expressed by the following equation (10). V _2M = I _1M · R _2M (10) The charging current generation circuit 3 _M generates the charging current I _{d in the} direction of drawing from the negative electrode of the capacitor C _{d in} the same manner as the charging current generation circuit 3. Due to the charging current I _d , a charging voltage V _Cd is generated across the capacitor C _d .

Similar to the equation (7), the charging current I _d can be expressed by the following equation (11). I _d = N · I _1M (11) Voltage at the negative input terminal of comparator 11 _M (GND
(Based on the terminal) becomes V _IN -V _2M , and the voltage at the positive input terminal of the comparator 11 _M (based on the GND terminal) becomes V _IN -V _Cd .

When V _2M > V _Cd , the comparator 11 _M outputs a positive output voltage, and the output voltage V _RO becomes the reset level of 0V. When V _2M ≦ V _Cd , comparator 1
The output voltage of 1 _M becomes 0 V, and the output voltage V _RO becomes the H level of the reset release level (power supply voltage V _IN ).

The power supply voltage monitoring circuit 12 _M has a power supply voltage V _IN
Is less than the threshold voltage V _TH , the capacitor C _d is discharged to V _Cd = 0 V, and when the power supply voltage V _IN is equal to or higher than the threshold voltage V _TH , the discharge of the capacitor C _d is stopped. Delay time t
The value of _d is the same as the delay reset circuit 1 of FIG.
It can be expressed by equation (2) and does not depend on the power supply voltage V _IN .

T _d = (C _d · R _2M ) / N (12) The delay reset circuit 1 _M operates in the same manner as the delay reset circuit 1 of FIG. That is, when the power supply voltage V _IN does not reach the threshold voltage V _TH , the output voltage V _RO is 0 V, which is in the reset instruction state, and when the power supply voltage V _IN reaches the threshold voltage V _TH , a delay time t _{d is} delayed. The voltage V _RO changes from 0 V to the H level, and the reset instruction is released.

[0049]

As described above, according to the present invention, the delay time which does not depend on the value of the input power supply voltage can be obtained by the configuration in which the charging current changes in proportion to the reference voltage which changes according to the input power supply voltage. Since it is not necessary to stabilize the reference voltage and the charging current with respect to the input power supply voltage, the reference voltage generating circuit and the charging current generating circuit can be configured by simple circuits. Therefore, the circuit can be greatly simplified as compared with the conventional delay reset circuit that requires the reference voltage source and the constant current source that do not depend on the input power supply voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a delay reset circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a delay reset circuit as a modified example of the exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional delay reset circuit.

FIG. 4 is an explanatory diagram of a relationship between a power supply voltage and an output voltage when the power is turned on.

[Explanation of symbols]

1,1 _M delay reset circuit 2,2 _M reference voltage generation circuit 3,3 _M charging current generation circuit 11,11 _M comparator 12 voltage monitoring circuit 13 output circuit C _d delay time setting capacitor T _VIN power supply terminal RESET * reset output Terminal V _IN Power supply voltage V _RO Output voltage

Claims (1)

[Claims] 1. A reference voltage generation circuit for generating a reference voltage depending on an input power supply voltage, a charging current generation circuit for generating a charging current proportional to the reference voltage, and a delay time setting for charging by the charging current. If the input power supply voltage is smaller than the threshold voltage by comparing the input power supply voltage and the threshold voltage with a comparison circuit that compares the charging voltage of the capacitor with the reference voltage and outputs a signal of the comparison result. A voltage monitoring circuit that discharges the delay time setting capacitor and stops discharge of the delay time setting capacitor when the input power supply voltage is equal to or higher than the threshold voltage, and a comparison result signal is supplied from the comparison circuit. When the charging voltage of the delay time setting capacitor is lower than the reference voltage, an output signal instructing reset is generated and the delay time setting capacitor is generated. When the charging voltage of the difference is equal to or more than the reference voltage, a delay reset circuit and having an output circuit for generating an output signal indicative of the reset release.