JPH08203273A - Information processing device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide an information processing device which performs accurate operation without malfunction even when storage media having various specifications are mounted. A memory control circuit unit 103 for generating a memory address 104 in response to a memory access request from a local bus address 102 from a CPU 101, and a DRAM 10 accessed by the memory address 104.
In the information processing device including the DRAM 108, the DRAM 108 is provided in the input path of the memory address 104 to the DRAM 108.
A noise cancel circuit section 106 that operates by a strobe signal 105 that notifies the timing of fetching the memory address 104 with respect to the memory address is removed, noise such as glitches generated at the time of memory address transition is removed, and a noise-free memory address 107 is generated. Then DRAM 108
It is an information processing device configured to input to.

Description

Detailed Description of the Invention

[0001]

The present invention relates to information processing technology,
Particularly, when a dynamic random access memory (hereinafter referred to as DRAM) is used as a storage medium, an internal address transient detector circuit (hereinafter referred to as AT)
The present invention relates to a technique effective when applied to prevention of malfunction of a D circuit).

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device for preventing a malfunction of the ATD circuit, for example, Japanese Patent Laid-Open No. 5-3255.
As disclosed in Japanese Patent Laid-Open No. 48, in the DRAM, two latch circuits in the main and preamplifier control circuits which operate by receiving an ATD signal are supplied to the main amplifier for the main amplifier by the output of the preamplifier latch circuit. The latch circuit is operated so that the output control signals of the preamplifier and the main amplifier are
There is known a technique of operating with the same sensitivity for TD signals.

FIG. 8 is a block diagram of a control circuit inside a semiconductor memory device disclosed in Japanese Patent Laid-Open No. 5-325548.

In FIG. 8, reference numeral 701 is a main preamplifier control circuit (output control means). 70
2 is a preamplifier control latch circuit, 703 is a main amplifier control latch circuit, and 704 is A
TD signal, 705 is preamplifier control signal (/
PAE), 706 is an output control input signal after the latch circuit 702, 707 is a main amplifier control signal, 708 is an information signal in a memory cell, 709 is a data output amplifier (output amplification means), 710 is a preamplifier, 7
Reference numeral 11 is a main amplifier, and 712 is output data.

FIG. 9 is a timing chart showing the operation of the control circuit block diagram shown in FIG.
The schematic operation of the conventional memory access control circuit shown in FIGS. 8 and 9 will be described below. After the sensing operation is completed, the ATD signal 704 becomes operable at the "L" level, and then the AT which is halfway due to noise or the like.
When the D signal 704 is input, the preamplifier control latch circuit 702 senses the change, and if it is determined that the address is switched, the preamplifier control signal 705 (broken line portion) is used to output the subsequent data output amplifier 709.
The preamplifier 710 is controlled, and at the same time, the result is sent to the main amplifier / control latch circuit 703 as a signal 706 (broken line portion), and by the output control signal 707 (output node A) (broken line portion) generated thereby, The main amplifier 711 is controlled so that the data output amplifier 709 outputs the information signal 708 in the memory cell array as output data 712 to the output terminal.

When the preamplifier control latch circuit 702 does not detect a change in the waveform due to the halfway ATD signal 704, that is, when it is determined that the address is not switched, the waveform shown by the solid line in FIG. The preamplifier control signal 705 is generated, and the main amplifier / control latch circuit 703 is operated by the signal 706 (solid line portion) in which the change is not sensed, and its output control signal 707 is output.
By (output node A) (solid line portion), the main amplifier 7
11 output data 712 is controlled. That is, the preamplifier control signal 705 and the main amplifier control signal 707 are the halfway ATD signal 704.
However, the output of the data output amplifier 709 is not in a high impedance (Hi-z) defective state.

As described above, in the conventional technique, the main amplifier
Like the preamplifier control signal 705, the control signal 707 is generated by the ATD signal 704 by the signal 706 passing through the preamplifier control latch circuit 702. The state of the output control signal 705 is determined, and a high impedance (Hi-z) defect state does not occur. The data output amplifier 709 reads the data even if the halfway ATD signal 704 is generated due to noise or the like. It tries to maintain the state.

[0008]

However, in the above-mentioned prior art, although the ATD control circuit inside the DRAM is improved, no consideration is given to noise removal of the ATD signal itself. Therefore, in an information processing apparatus having a DRAM whose ATD control circuit has not been improved, there is a problem that a problem may occur in the control of the DRAM.

Further, in the above-mentioned prior art, high impedance (Hi-
z) It has been improved so that it does not become a defective state, but during the invalid period of the cycle (hereinafter referred to as the idle period),
There is a problem that meaningless data is output due to noise on the ATD signal and power consumption increases.

An object of the present invention is to provide an information processing technique capable of performing an accurate operation without malfunction even if a storage medium having various specifications is mounted.

Another object of the present invention is to provide an information processing technique capable of realizing both prevention of malfunction and power saving.

Still another object of the present invention is to provide an information processing technique capable of realizing various mounting modes.

[0013]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, in an information processing system including a memory control device for generating a memory address and a storage medium, noise for removing noise of the memory address is added to a memory address input path from the memory control device to the storage medium. The removing means is provided.

As the noise removing means, for example, a three-state buffer having a strobe signal as a control input for instructing the storage medium at the timing of fetching the memory address can be used. As a storage medium,
For example, it is possible to use a DRAM.

That is, specifically, for example, noise on an address such as a glitch generated at the time of switching the memory address output from the memory control device is masked by using the high impedance state of the three-state buffer, The malfunction of the ATD circuit inside the DRAM is prevented.

If necessary, a timing adjusting means composed of, for example, a buffer circuit and a capacitive element is arranged in the path of the control input to the three-state buffer constituting the noise removing means to operate the noise removing means. Aim for further optimization. In addition, switching the noise removal means between valid / invalid on the intervening path of the noise removal means,
A series resistor having a damping function can be arranged.

[0018]

According to the present invention described above, noise such as glitch generated when the memory address is output from the memory control device can be masked by noise removing means such as a three-state buffer. It is possible to prevent malfunction. In other words, the DR in which the malfunction prevention measure is not applied to the ATD circuit
It is possible to use storage media having various specifications such as AM without concern about malfunction. Also, by using the three-state buffer for the mask of noise,
It is also possible to strengthen the drive capability of the memory address.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a schematic configuration of an information processing apparatus which is an embodiment of the present invention.

In FIG. 1, 101 is a central processing unit (hereinafter referred to as CPU), 102 is a local bus address output from the CPU 101, 103 is a memory control circuit section, and 104 is an output from the memory control circuit section 103. Memory address, 105 is the memory address 1
A strobe signal (hereinafter referred to as a CAS-N signal) for fetching a 04 column address, 106 is a noise canceling circuit unit in the present embodiment, and controls noise removal such as glitches on the memory address 104. To do. 107 is a memory address of the memory address 104 after noise removal, and 108 is a memory address 107.
If there is noise in the data storage medium (DR), the internal ATD circuit malfunctions and correct data cannot be read.
AM).

The information processing apparatus according to the present embodiment has the above-mentioned configuration, and by removing the noise on the memory address 104 output from the memory control circuit unit 103,
The system configuration allows all types of DRAM to be installed.

The outline of the operation of the information processing apparatus of this embodiment will be described below with reference to FIG. As shown in FIG. 1, the CPU 101 first requests a memory access and outputs the local bus address 102. In response to this, the memory control circuit unit 103 causes the local bus
The address 102 is converted into a memory address 104 and output in a time division manner in the order of rows (rows) and columns (columns). This memory address 104 is switched to the address of the next memory cycle after the end of the memory cycle. Noise such as glitch may occur at the transition of the address switching. Using the DRAM 108 as a storage medium,
When the fast page mode, which is the most general control method, is used, the memory address output in each memory cycle is a column address, and at the time of address switching, the negation (rising waveform) of the CAS-N signal 105 is Must occur. Therefore, in the present embodiment, the CAS-N signal 105 is used as a start signal (control input) of the noise cancellation circuit unit 106 in order to remove the noise of the memory address 104 by the noise cancellation circuit unit 106. The memory address 107 from which noise has been removed in this way is output from the noise cancellation circuit unit 106 as a memory address of the DRAM 108. Also, the CAS-N signal 105 is the D
The column address strobe signal of the RAM 108 is also given to the DRAM 108 to fetch the memory address (column address) 107 after the noise removal.

FIG. 2 is a block diagram showing in detail an example of the configuration of the noise canceling circuit section 106 illustrated in FIG. Reference numeral 201 denotes a three-state buffer which constitutes the noise canceling circuit section 106. In order to simplify the explanation, in FIG.
Memory addresses 104 and 107 therein are shown as one memory address 104b and 107b, respectively.

FIG. 3 is a timing chart showing the operation of the information processing apparatus shown in FIG. 2, and FIG. 7 is an explanatory diagram (truth table) showing an example of the operation of the three-state buffer 201 of this embodiment. is there.

The details of the operation of this embodiment will be described below with reference to FIGS.

The memory address 104b output from the memory control circuit unit 103 in response to a memory access request from the CPU 101 is input to the three-state buffer 201. An output enable terminal (hereinafter referred to as an OE terminal) of the three-state buffer 201 is high active, and a CAS-N signal 105 output from the memory control circuit unit 103 is connected to this terminal. Therefore, the memory address 107b output from the three-state buffer 201 to the DRAM 108
Indicates that the CAS-N signal 105 is asserted to "L".
The high impedance state (Hi-z state) is maintained during the period of the (“0”) level (see FIG. 7). As a result, noise such as glitch generated at the transition due to the memory address switching is removed when the memory address 107b is in the Hi-z state, and the memory address 107b given to the DRAM 108 has a noise-free waveform.

That is, noise such as glitches at the memory address 104 output from the memory control circuit unit 103 is removed by the noise canceling circuit unit 106 before being input to the DRAM 108 used as a storage medium. It is possible to prevent the malfunction of the ATD circuit.

Therefore, it is possible to operate the DRAM 108 accurately regardless of whether or not there is a noise countermeasure for the memory address 107b inside the DRAM 108. In other words, the DRAM 108 having various configurations
It becomes possible to construct an information processing device that operates accurately by using, for example, inexpensive DR without error countermeasures.
When the AM 108 is used, cost reduction can be realized without impairing the operation performance.

Since the noise on the memory address 107b is removed before being input to the DRAM 108, DR
Inside the AM 108, meaningless data will not be output during the idle period, and the DRAM 10
8, it is possible to realize power saving of the entire information processing apparatus.

Further, the memory address 104b is transferred to the memory address 10b via the three-state buffer 201.
By outputting as 7b and removing noise, the driving force of the memory address 107b is strengthened and becomes stronger against attenuation during propagation.

(Embodiment 2) FIG. 4 is a block diagram showing an example of the configuration of an information processing apparatus which is another embodiment of the present invention, and FIG. 5 is a timing chart showing an example of its operation.

In the first embodiment illustrated in FIG. 2 described above, in the memory address 107b after noise removal, the transition period from the valid address to the Hi-z state is CAS-N.
It is defined as the time that the three-state buffer 201 puts its output in the Hi-z state after the signal 105 is asserted.

Therefore, when this transition period is short and the DRAM 108 having a long access time is mounted,
There is a possibility that the specified value of the column address hold time required by 108 cannot be satisfied.

On the other hand, the transition period from the Hi-z state to the valid address is defined by the time when the three-state buffer 201 sets the output to the valid state after the CAS-N signal 105 is negated. Therefore, if this transition period is short, the mask of noise generated during address switching may be incomplete. The configuration of the present embodiment shown in FIG. 4 deals with the problems that may occur.

In FIG. 4, 401 is a CAS-N signal buffer (hereinafter referred to as a buffer), and 402 is a CAS-N signal.
N signal delay capacitive element (hereinafter referred to as capacitive element), 40
3 shows the delayed CAS-N signals, respectively.

Details of the operation using FIGS. 4 and 5 will be described below.

CAS-N output from the memory control circuit unit 103 in response to a memory access request from the CPU 101.
Signal 105 is applied to DRAM 108 and buffer 401. The output signal 403 of the buffer 401 is connected to the OE terminal of the three-state buffer 201.
The output signal 403 of this buffer 401 and the ground (GN
A capacitive element 402 is provided between D). Thus, the OE terminal control timing of the three-state buffer 201 can be delayed with respect to the timing of strobing a column address in the DRAM 108 and the end of the memory cycle, which is a concern in the embodiment of FIG. Secured column address hold time, and
It is feasible for a perfect noise mask. still,
The buffer 401 is a CAS that is given to the DRAM 108.
It is inserted in order to prevent the influence of the waveform delay due to the capacitive element 402 from spreading to the -N signal 105.

The capacitance of the capacitive element 402 is, for example, 25 to 33 M when the clock of the CPU 101 is set.
z and the access time of the DRAM 108 is 70 ns, it is about 50 to 300 pF.

As described above, in the case of this embodiment, the signal for controlling the noise canceling circuit section 106 is supplied to the DRAM.
By delaying the CAS-N signal 105 supplied to the DRAM 108, the DRAM 1 having a wide access time can be obtained.
08, it is possible to accurately remove noise in response to variations in noise delay occurring at the end of a memory cycle.

(Third Embodiment) FIG. 6 is a block diagram showing an example of the configuration of an information processing apparatus which is still another embodiment of the present invention. The third embodiment differs from the second embodiment illustrated in FIG. 4 in that the noise cancellation circuit unit 106 of the information processing apparatus can be enabled / disabled.

In FIG. 6, reference numeral 601 denotes a series (damping) resistance (hereinafter referred to as damping resistance A) for enabling the noise canceling circuit section 106, and 602 is a series (damping) for disabling the noise canceling circuit section 106. Resistance (hereinafter referred to as damping resistance B), 107
Reference character c denotes a memory address signal that has passed through the damping resistor A (601) or the damping resistor B (602). The values of the damping resistor A (601) and the damping resistor B (602) are set to, for example, 20 to 100Ω when the clock of the CPU 101 is 25 to 33 Mz and the access time of the DRAM 108 is 70 ns.

In the configuration of FIG. 6, the damping resistance A
When (601) is mounted and the damping resistor B (602) is not mounted, the noise canceling circuit section 106 is
Is enabled. Conversely, when the damping resistor A (601) is not mounted and the damping resistor B (602) is mounted, the noise cancellation circuit unit 106 is invalidated and the memory address 104b output from the memory control circuit unit 103 is It is directly applied to the DRAM 108 via the damping resistor B (602). Furthermore, the damping resistor A (601) and the damping resistor B in this embodiment are used.
The function (602) has a function of switching enable / disable of the noise cancellation circuit unit 106 and a function of damping an address waveform in each state, and a function of reducing noise on the address waveform in a steady state. There is also.

As described above, in the case of the present embodiment, it is possible to switch between enabling and disabling of the noise cancel circuit section 106 according to the presence / absence of noise on the memory address. -Costs can be reduced because the components that make up the cancel circuit unit can be left unmounted.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the description of the above embodiments, the case where the DRAM is used as the storage medium is illustrated, but the storage medium is not limited to the DRAM, and any storage medium having an ATD circuit inside may be applied to other storage media. It is possible.

[0047]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

That is, according to the information processing apparatus of the present invention, it is possible to carry out an accurate operation without malfunction even if storage media having various specifications are mounted.

Further, there is an effect that both prevention of malfunction and power saving can be realized.

Further, there is an effect that various mounting forms can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an information processing apparatus that is an embodiment of the present invention.

FIG. 2 is a block diagram showing in detail an example of a configuration of a noise cancellation circuit unit of the information processing apparatus according to the exemplary embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the information processing apparatus which is an embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a configuration of an information processing apparatus which is another embodiment of the present invention.

FIG. 5 is a timing chart showing an example of the operation of the information processing apparatus which is another embodiment of the present invention.

FIG. 6 is a block diagram showing an example of a configuration of an information processing apparatus which is still another embodiment of the present invention.

FIG. 7 is an explanatory diagram showing an example of the operation of a three-state buffer which constitutes an information processing apparatus according to an embodiment of the present invention.

FIG. 8 is a block configuration diagram showing an example of a configuration of a conventional storage device.

FIG. 9 is a timing chart showing an example of the operation of a conventional storage device.

[Explanation of symbols]

101 ... Central processing unit (CPU), 102 ... Local bus address, 103 ... Memory control circuit section, 104, 1
04b ... memory address, 105 ... CAS-N signal (strobe signal), 106 ... noise cancel circuit section,
107, 107b ... Memory address, 108 ... DRAM
(Storage medium), 201 ... Three-state buffer, 4
01 ... Buffer, 402 ... Capacitance element, 403 ... Output signal, 601 ... Damping resistance A, 602 ... Damping resistance B, 702 ... Preamplifier control latch circuit, 703 ... Main amplifier control latch circuit, 704 ... ATD signal, 705 ... Preamplifier control signal, 706 ... Output control input signal, 70
7 ... Main amplifier control signal, 708 ... Information signal, 709 ... Data output amplifier, 710 ... Preamplifier,
711 ... Main amplifier, 712 ... Output data.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location G11C 11/34 354 B (72) Inventor Kenichi Nagashima 810 Shimoimaizumi, Ebina-shi, Kanagawa Hitachi, Ltd. (72) Inventor Tsuyoshi Onijima Go to 810 Shimoimaizumi, Ebina City, Kanagawa Stock Company, Hitachi Systems Office System Division

Claims (3)

[Claims] 1. An information processing apparatus comprising: a memory control device for generating a memory address in accordance with a memory access request from a central processing unit or an external master device; and a storage medium to which the memory address is input. The input path of the memory address to the storage medium is provided with noise removing means for removing noise of the memory address by using a strobe signal for notifying the storage medium of the timing of fetching the memory address from the memory control device as a control input. An information processing device characterized by the above. 2. The information processing apparatus according to claim 1, wherein the noise removing means comprises a three-state buffer having the strobe signal as a control input. 3. The information adjusting apparatus according to claim 2, further comprising a timing adjusting unit arranged in an input path of the strobe signal to the noise removing unit, for adjusting an input timing of the strobe signal to the noise removing unit. Processing equipment.