JPH08202626A - Memory controller - Google Patents

Abstract

PURPOSE: To provide a memory controller which writes the data into an EEPROM and can accurately store such data that should be frequently rewritten for a long period by comparing the data to be written with the data which are already written in the same address of the EEPROM and then inhibiting the updating of both data when they are coincident with each other. CONSTITUTION: The memory controller consists of a CPU 1, an EEPROM 2 serving as a memory element, an interface circuit 3 and a common bus 4. The CPU 1 calculates the data A that should be written. Then, the CPU 1 reads out the contents B of the address that is already stored in the EEPROM 2 and compares the data A with the contents B of the EEPROM 2. If the data A are equal to the contents B, the rewriting of data is not required and therefore, the processing ends. If the data A are not equal to the contents B, the address contents are erased so that the data A are written in the EEPROM 2, Then the data A are written in the address and the processing ends.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a memory control device,
In particular, the present invention relates to a memory control device used in an on-vehicle electronic device.

[0002]

2. Description of the Related Art In an on-vehicle electronic device or the like, control parameters and set values are obtained by learning in order to optimize the control, and these are stored in a memory or dealt with the contents of a failure in the system. The fault code is stored in the memory for reference during inspection and maintenance.

Such learning data and failure history codes are not only generated while the vehicle-mounted electronic equipment is operating, but also when the main power source is turned off.
It is necessary to store (retain) data even during device hibernation at the time.

Therefore, conventionally, in order to realize the retention of the learning data and the failure history code, the method using the memory backup power supply is first adopted.

In this system, the RAM is installed in the electronic device.
The RAM data is supplied from a power supply (backup power supply) of a system different from the main power supply of the electronic device, and the backup power supply is supplied even when the electronic device is not in operation (main power OFF). Holding

However, the method using the memory backup power source has the following drawbacks.

It is necessary to add wiring for a backup power supply to a system different from the main power supply. Normally, the power supply voltage is always applied to the wiring for the backup power supply, and therefore the wiring must be performed in consideration of the prevention of electrical accidents. Since the backup power supply is directly connected to the vehicle battery, the vehicle inspection / maintenance can be performed independently of the electronic equipment inspection / maintenance.
If the battery is removed during maintenance, the data in the memory will be erased. Even if the electronic device body is recovered due to a failure, etc., the data in the memory will be erased when it is removed from the vehicle, so it may take some time to reproduce and check the failure.Read the memory contents before removing the electronic device and make a memo. It is necessary to keep such things.

For this reason, in recent years, a method using an EEPROM is becoming mainstream instead of a method using a memory backup power supply.

That is, data that needs to be held using an EEPROM known as an electrically erasable / writable non-volatile memory element is stored in this EEPROM.
The method of holding the data in advance and holding the data has been widely used.

[0010]

However, the method using the EEPROM as described above has the following problems.

Due to the internal structure of the EEPROM, the characteristics of the memory device are gradually deteriorated by the data erasing / writing operations. Therefore, the number of data erasing / writing operations at the same address of the EEPROM is finite, and the data is frequently written. It is inappropriate if it needs to be rewritten.

This point has been a serious problem in electronic equipment for commercial vehicles, which requires a relatively long operating time of the electronic equipment and a long service life of the equipment.

Therefore, it is an object of the present invention to accurately store data that needs to be rewritten frequently over a long period of time in a memory control device for writing data to an EEPROM.

[0014]

[Means for Solving the Problems]

(1) In order to achieve the above object, the memory control device according to the present invention is characterized in that data is compared with data already written in the same address of the EEPROM and the update is prohibited when both are the same. It was done.

(2) In the present invention, the data is EEPR.
The number of times of writing to the same address of the OM is counted and the E
It is also possible to retain the data in the EPROM and change the address of the data to write when the count value reaches the rewriting limit number of times.

[0016]

[Action]

(1) In electronic devices and the like, data calculation is frequently performed internally, but in the case of data that does not change much and has a nearly constant value each time data calculation is performed, E is already calculated after data calculation.
Once the data written in the EPROM is read,
Only when the calculated data is different from the calculated data, the already written contents of the EEPROM are erased, and new data is written.

(2) When the data is frequently calculated as described above and the data changes a lot, EEPRO
When a plurality of M addresses are provided and the number of times of writing data to the same address is counted, the count value is stored in the EEPROM.

When the count value exceeds the erase / write count guaranteed by the EEPROM, the EEPROM
By setting a new address for the same address, the same address is prevented from being used more than a predetermined number of times. In this way, the life of the EEPROM is extended.

[0019]

1 shows an embodiment of a memory control device (1) according to the present invention, in which 1 is a CPU as a memory control device and 2 is an EEPRO as a memory element.
M is an interface circuit for taking in input data, and 4 is a common bus for giving the data from the interface circuit 3 to the CPU 1 and the EEPROM 2.

FIG. 2 shows a memory map of the EEPROM 2 for writing data according to the present invention. Here, it is assumed that the data to be written is 1 byte. Therefore, as shown in FIG. 2, only the address ADD for writing data is required as the memory of the EEPROM 2.

FIG. 3 shows a flow chart of a data writing process performed by the CPU 1 shown in FIG. 1, and this flow chart is started when writing data.

First, the CPU 1 calculates the data (A) to be written (step S1).

Next, the content (B) of the address ADD already stored in the EEPROM 2 is read (step S2).

Next, the data (A) calculated in step S1 is compared with the memory content (B) of the EEPROM 2 read in step S2 (step S3).

As a result, if A = B, it is not necessary to rewrite the data and the process is terminated. However, if A ≠ B, the data (A) calculated in step S1 is changed to EEPR.
In order to write to OM2, the contents of address ADD are first erased (step S4).

Then, the data (A) is written to the address ADD (step S5), and the process is terminated.

It is possible to always store the same value as the latest data (A) in the EEPROM 2 by the processing of the above steps S1 to S5, but in this case, only when the data is changed and rewriting is necessary. Since the erasing / writing is performed, the life of the EEPROM is not adversely affected.

FIG. 4 shows that the CPU 1 has an EEPROM 2
7 shows a flowchart for reading data from the memory device. Data reading is performed in the same manner as in the case of data reading on a normal RAM (similar to step S2), and the direct address AD is used.
The contents will be read from D (step S10).

FIG. 5 shows a memory control device (2) according to the present invention.
This embodiment shows the embodiment of the present invention (1) shown in FIG. 1 in addition to the two-byte register R1.
The difference is that the 1-byte register R2 is prepared in the CPU 1. The CPU 1 also includes a ROM 10 that stores a predetermined number of times.

FIG. 6 shows the EEPROM 2 shown in FIG.
The memory map and the offset value (pointer data) for indicating the memory address and the address of the erase / write number counter of the memory address are stored in the address ADD.

A memory for writing data and a memory for erasing / writing frequency counter are allocated on a continuous array X as shown in the figure.

Here, the data to be written is 1 byte, and the maximum value of the erase / write count is set to 65535, and the erase / write count counter is allocated to 2 bytes. Therefore, the write count value is the address X
(0), X (1) and X (3), X (4), ... Are written, and data are written at addresses X (2), X (5) ,.

First, assuming that "0" is set in each of the addresses ADD, X (0), X (1) as an initial value at the shipping stage of electronic equipment and the like, the data writing process shown in FIG. 7 is performed. Run.

In FIG. 7, first, the data (A) to be written is calculated (step S11).

Then, the erase / write count value is read out to the register R1 (step S12). In this case, as shown in FIG. 6, since the count value is stored in all 2 bytes of the memory address where the data is written, the count value is stored in the addresses X (0 + ADD) and X (1 + ADD). .

Next, the count value of the register R1 and the set value are compared (step S13).

This set value is stored in advance in the ROM 10 incorporated in the CPU 1, and as described above, the EEP
Set according to the erase / write count guaranteed by ROM2,
In this embodiment, since it is 2-byte data, it can be set up to 65535 times as described above. This number is 65
Needless to say, if the memory is guaranteed up to 535 times or more, the counter memory may be changed to a setting of 3 bytes or the like.

If the result of determination in step S13 is that the content of the register R1 is less than the set value, both the counter and the data are written to the memory at the same address where the erasing / writing has been performed up to now. Since it is possible, the erase / write count up to now is “1”.
Is added and the result is left in the register R1 (step S14).

Then, in order to write the next count value, the contents of the addresses X (0 + ADD) and X (1 + ADD) are erased (step S15).

Next, addresses X (0 + ADD), X
The contents of the register R1 are written to (1 + ADD) (step S16), the contents of the data storage memory address X (2 + ADD) are erased to write the data (A) (step S17), and the data (A) is transferred to the address X. (2+
ADD) is written (step S18), and the process ends.

On the other hand, when it is determined in step S13 that the content of the register R1 has reached the set value, the processes of steps S19 to S23 are executed to change the addresses of the data memory and the counter memory.

First, in step S19, the offset value of the address ADD which is the address pointer is transferred to the register R2.

Next, in order to rewrite the offset value in step S11, the offset value of the address ADD is erased, and the previous address A transferred to the register R2 is deleted.
"3" is added to DD, and the result is left in the register R2 (step S21).

Then, in step S22, the value of the register R2 is written to the address ADD as a new address offset value, and the data writing to the new address is the first time. Therefore, the value is erased / written to the register R1. "1" is written (step S23).

After this, the process jumps to step S15 and the same processing as above (steps S15 to S18) is performed and the processing is ended.

In this way, steps S19 to S23 are performed.
By executing the processing of, the pointer value (offset value of the address ADD) up to now is incremented by "3",
Since the count value address and the data address on the memory map of the EEPROM 2 shown in FIG. 6 are changed by "3" respectively, a new address is set.

Then, the address pointer value (address A
The contents of DD) and the erase / write count value (address X (0 + ADD), X (1 + ADD)) are also stored in the EEPROM 2 together with the data value (address X (2 + ADD)), so the main power supply of the electronic device is turned off. The number of times of erasing / writing can be accurately stored in the EEPROM 2 and the memory address of data is not lost.

FIG. 8 shows a flowchart for reading the data value written by the processing shown in FIG. 7, and the stored data value is read by reading the memory contents of the address X (2 + ADD). (Step S30).

In the memory map shown in FIG. 6 and the flowchart shown in FIG. 7, the address on the memory map of the address offset of the address ADD is fixed at one location, but since it is set on the EEPROM, the data is Although there is a limit on the number of times of erasing / writing like the above, the data can be changed in the same manner as changing the data address.

[0050]

As described above, according to the memory control device of the present invention, the data is compared with the data already written in the same address of the EEPROM, and the update is prohibited when both are the same, Or EE the data
Since the number of times of writing to the same address of the PROM is counted and stored in the EEPROM and the count value reaches the rewriting limit number of times, the address of the data is changed and written, so that the backup power supply is not required and Data that needs to be written frequently can be stored accurately over a long period of time, and learning data and failure history codes can be retained without a backup power supply, especially in electronic devices such as commercial vehicles. Become.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory control device (1) according to the present invention.

FIG. 2 E used in the memory control device (2) according to the present invention
It is a memory map diagram of EPROM.

FIG. 3 is a block diagram of C in the memory control device (1) according to the present invention.
It is a flowchart figure of the data writing process performed by PU.

FIG. 4 C in the memory control device (1) according to the present invention
It is a flowchart figure of the data read-out process performed by PU.

FIG. 5 is a block diagram showing an embodiment of a memory control device (2) according to the present invention.

FIG. 6 E used in the memory control device (2) according to the present invention
It is a memory map figure of EPROM.

FIG. 7 C in the memory control device (2) according to the present invention
It is a flowchart figure of the data writing process performed in PU.

FIG. 8 C in the memory control device (2) according to the present invention
It is a flowchart figure of the data read-out process performed by PU.

[Explanation of symbols]

 1 CPU 2 EEPROM 10 ROM R1, R2 registers In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A memory control device for writing data to an EEPROM, wherein the data is compared with data already written at the same address of the EEPROM, and when both are the same, update is prohibited. Memory controller. 2. A memory control device for writing data to an EEPROM, the number of times the data is written to the same address of the EEPROM is counted and held in the EEPROM, and the count value reaches a rewriting limit number. A memory control device characterized in that sometimes the address of the data is changed and written.