JPH08201481A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To enable a delay pulse test at a high frequency equivalent to an internal clock by generating a high-frequency clock signal based on an input clock and generating a delay pulse with the same delay width as the period thereof. CONSTITUTION: A PLL circuit 40 converts 33MHz low-frequency clock which is inputted 10 to 100MHz high-frequency clock signal, and supplies it to an additional clock circuit 50. The circuit 50 starts generating a clock (a delay pulse comprising two pulse waves) at the same interval as the high-frequency clock frequency generated internally by the circuit 40. An order circuit block 30 of scan path design successively outputs 12 data every time it receives clocks by inputting 11 data, and forms a shift register on testing. In a delay pulse test mode where a select signal 14 is L, the circuit 50 distributes generated clocks to each latch circuit 31, thus executing the delay pulse test of the block 30 in terms of AC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including a test circuit therein, and more particularly to a synchronous semiconductor integrated circuit including a sequential circuit having a scan path design for fault diagnosis. More specifically, the present invention relates to a synchronous semiconductor integrated circuit having a scan path design and capable of performing a delay pulse test at a high frequency equivalent to an internal clock. .

[0002]

2. Description of the Related Art With the recent technological innovation, ASIC (Application Specific) such as gate array (Gate Array)
Integrated Circuits: Semiconductor integrated circuits using special purpose ICs) have become widespread.

The semiconductor integrated circuit is usually manufactured through a number of processes (exposure / film formation process, assembling process such as cutting, mounting, bonding (connection), sealing (sealing), etc.). Is naturally expensive. The cost is wasted if a defective or defective wafer or chip is sent to the next process. Therefore, it is necessary to find and repair or remove defective wafers / defective chips early in the manufacturing process by testing whether the chips work properly for each process.
This test is generally performed by inputting a test pattern (test sequence) and checking whether or not a normal output pattern (that is, an expected value) is obtained for each input test pattern. The test pattern is supplied to the chip and read by pressing a probe of an external tester (LSI tester) against the I / O pad on the chip.

A semiconductor integrated circuit is composed of a combinational circuit (that is, a circuit such as an OR, AND, and NOT gate whose output is determined only by the input at that time) and a sequential circuit (that is, a flip-flop (also called a latch). (For example, a circuit whose output is determined not only by the input at that time but also by the past input (or internal state))
It can be understood that it is composed of and. The operation confirmation test of the combinational circuit portion of the semiconductor integrated circuit is relatively easy. This is because the combinational circuit has a simple causal relationship between the input data and the expected value and is easy to analyze, and the output can be obtained at the same time as the input, so that the inspection cycle can be shortened. On the other hand, testing a sequential circuit is not easy. This is because the output of the sequential circuit changes depending on the combination with the internal state already held even with the same input pattern, so that the test pattern becomes complicated and long. Also, the sequential circuit is
Normally, since the input is received in the clock cycle, the inspection cycle also takes a long time accordingly. Therefore, in the test mode, each internal latch circuit is switched to a serial connection and one shift register (“scan path (Sc
There is also a semiconductor integrated circuit designed to be able to form an path) circuit). With a shift register, the internal states of all flip-flops can be set freely by inputting clocks as many as the number of flip-flops connected in series, thus facilitating the creation of test patterns. Because. Currently, various semiconductor integrated circuits incorporating a scan path design have been developed and put into practical use. So-called LSS
D (Level Sensitive Scan Design) is an example of scan path design.

Although the scan path circuit is easy to create a test pattern as described above, it has a problem of clock skew. Here, "clock skew" refers to a phenomenon in which a sequential circuit does not operate normally due to a delay between wirings. For example, in the scan path circuit shown in FIG. 5A, the output Q of the preceding D flip-flop is delayed until the next clock due to wiring delay due to passage of a combinational circuit connected between the flip-flops. In the meantime, the subsequent D flip-flop is not reached and the data is not latched. Alternatively, since the succeeding D flip-flop is still open when the preceding D flip-flop latches the next input, the data to be taken in at the next timing (that is, the output of the preceding D flip-flop) ) Is taken in and the data penetrates. Therefore, for an LSI with a scan path design, the output of the internal flip-flop circuit is set to a predetermined state, and a delay pulse consisting of two pulse waves with an interval similar to the operation clock is set. It is also necessary to check that data is normally transmitted between consecutive flip-flops within the clock time by using the pulse (see FIG. 5B) as a clock. Such an inspection is also called a "delay pulse test". In particular, in the case of a synchronous integrated circuit, the problem of clock skew is more important because each sequential circuit operates synchronously according to a clock without waiting for data transmission. Then, in order to confirm that the clock skew does not occur during the normal operation, the same timing as the normal operation speed of the integrated circuit (that is, the pulse interval in the delay pulse is set to be substantially the same as the clock cycle). ), A scan pass test is preferred.

By the way, in the case of inputting a clock signal or a delay pulse when inspecting a semiconductor integrated circuit, conventionally, a probe is brought into contact with an I / O pad on the semiconductor integrated circuit to provide an external dedicated test apparatus (so-called LSI tester). ) Or an oscillator. The input through the probe has no problem at the operating frequency of the conventional integrated circuit (about 30 MHz). However, 50 MH
High-speed clock signals such as z and 100 MHz cannot be handled by the probe input. Because the high-speed signal is affected by the inductance of the LSI tester itself or the test stand (performance board),
This is because ringing easily occurs. Also, because it is affected by the stray capacitance on the LSI tester or test stand (performance board), the voltage waveform, which should have been a discrete rectangle, is blunted into a low frequency component, which is no longer useful as a clock signal. Is. To avoid the problem of external input of high frequency clock,
At the time of test, lower frequency than normal operation (for example, 5MHz)
It is also possible to use a clock of about (degree). But,
When a low-frequency clock is used, the operating speed of the device is completely ignored, and a high-level or low-level DC voltage is merely given as timing, and D
It is equivalent to a C-like inspection. Of course, this does not mean that the clock skew inspection between the sequential circuits is performed at the same AC-like timing as the normal operating speed of the integrated circuit.

It should be noted that improving the test apparatus (LSI tester) to input a high-speed frequency probe is not completely impossible in view of the current technical level. However, it is difficult to output a high-speed clock signal as a steep waveform to the outside, and an expensive oscillator is required. Therefore, the unit price per probe is about 1 million yen, and the LSI tester for testing a 256-pin semiconductor integrated circuit is equivalent to 200 million yen, resulting in a high cost.

DX2, DX currently marketed by Intel Corporation
4 and PowerPC603 (Po which was jointly developed by IBM Corp., Motorola Corp. and Apple Computer Corp.)
werPC is 50 MH like registered trademark of IBM Corp.
Processors operating above z are becoming mainstream. With this in mind, it will be appreciated that there is a desire for a device or technique that can provide accurate delay pulses to the scan path circuit.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to provide an excellent synchronous semiconductor integrated circuit having a scan path design for fault diagnosis.

A further object of the present invention is to provide a synchronous semiconductor integrated circuit having a scan path design for fault diagnosis, which is capable of performing a delay pulse test at a high frequency equivalent to an internal clock. To provide.

[0011]

The present invention has been made in consideration of the above problems, and a first aspect thereof is configured by a circuit block including a plurality of scan path designed sequential circuits. In a semiconductor integrated circuit that operates synchronously, a test pattern input section for receiving a test pattern for inspecting the operation of an internal circuit from the outside, and a first clock signal having a first cycle are provided. A clock input section for receiving from the outside, a clock generation section for generating a second clock signal having a second cycle shorter than the first cycle based on the first clock signal, and a second clock signal A delay pulse generating section for generating a delay pulse composed of two pulse waves spaced by a second period based on the delay pulse as a clock. A semiconductor integrated circuit, wherein the testable the can path circuit.

The second aspect of the present invention is to
A test pattern input unit for receiving a test pattern for inspecting the operation of an internal circuit from the outside in a semiconductor integrated circuit which is composed of a circuit block including a plurality of sequential circuits whose paths are designed and which operates synchronously. When,
A clock input section for receiving a first clock signal having a first cycle from the outside, and generating a second clock signal having a second cycle shorter than the first cycle based on the first clock signal. And a delay pulse generator that sequentially outputs pulse waves with a delay time of a second period based on a second clock signal, and scans using the pulse waves as a clock. -A semiconductor integrated circuit characterized by being able to test a pass circuit.

A third aspect of the present invention is a scan /
A plurality of path-designed sequential circuits, a test pattern input section for receiving a test pattern for inspecting the operation of the internal circuit from the outside, and a first clock signal having a first cycle from the outside And a clock input section for generating a second clock signal having a second cycle shorter than the first cycle based on the first clock signal, and operating synchronously. In the integrated circuit, an additional clock for further inputting the second clock signal and outputting either the second clock signal or the delay pulse composed of two pulse waves having a delay time of the second period. A semiconductor integrated circuit comprising a supply unit.

Further, a fourth aspect of the present invention is, in a semiconductor integrated circuit composed of a circuit block including a plurality of sequential circuits, a clock input for externally receiving a first clock signal having a first cycle. A clock generator for generating a second clock signal having a second cycle shorter than the first cycle based on the first clock signal, and a second clock signal input to the sequential circuit. And a clock signal conversion processing unit for generating a third clock signal for timing the semiconductor integrated circuit.

According to the present invention, however, a relatively low frequency clock signal is input from the outside, and the same relatively high frequency clock signal as that during normal operation of the semiconductor integrated circuit is supplied to the internal clock based on the input clock. Generator (eg PLL
Circuit) to generate a delay pulse having the same delay width as the cycle of the internal clock signal. Therefore, if a scan path test is performed using the delay pulse as a timing, the same AC test as the normal operation of the semiconductor integrated circuit can be performed, so that the problem of clock skew can be sufficiently verified.

Still other objects, features and advantages of the present invention are as follows.
It will become apparent from the following more detailed description based on the embodiments of the present invention and the accompanying drawings.

[0017]

【Example】

A. Configuration of Semiconductor Integrated Circuit Chip FIG. 1 shows a semiconductor integrated circuit chip 100 embodying the present invention.
FIG. 3 is an overview diagram showing only the components that are particularly relevant to the gist of the present invention. The semiconductor integrated circuit chip 1
00 is composed of input / output (I / O) pads 10, ..., Combination circuit block 20, sequential circuit block 30, PLL circuit 40, and additional clock circuit 50.

The I / O pad 10 is provided on the chip 100 for convenience such as bonding with an envelope terminal (not shown).
It is arranged in the upper peripheral portion. The I / O pad includes an input pad for inputting data from the outside, an output pad for outputting the arithmetic processing result to the outside, and a pad for receiving a clock signal for synchronization from the outside. , Scan in (SI) pad 11, scan
Out (SO) pad 12, TEST_ON pad 13, SEL
There is an ECT pad 14. The SI pad 11 is for sequentially inputting serial data for setting the internal state of the sequential circuit block 30 from an external LSI tester. The SO pad 12 is for reading the output of the shift register formed in the sequential circuit block 30. The TEST_ON pad 13 and the SELECT pad 14 are for inputting signals for controlling the operation of the additional clock circuit 50 (described later).

The combinational circuit block 20 and the sequential circuit block 30 are circuit portions of the semiconductor integrated circuit chip 100 that perform substantial logical operations. The wiring between the elements is a problem that depends on the application of the chip 100, and is not related to the gist of the present invention, so a detailed description thereof will be omitted.

The sequential circuit block 30 includes a plurality of latch circuits (hereinafter, also referred to as SRL (Shift Register Latch)).
31 ... The group of SRLs 31 ... Has a scan path design, and can switch to a serial connection to form a shift register at the time of test execution. The sequential circuit block 30 as a whole receives serial data via the SI pad 11 and sequentially outputs data from the SO pad 12 each time a clock is received.

A PLL (Phase Lock Loop) circuit 40 is
As is well known, this is a circuit that can match the input oscillation frequency with a predetermined reference frequency. In this embodiment, the clock signal of the frequency multiplied from the I / O pad 10 is added to the subsequent additional clock. The PLL circuit 40 is used for the purpose of supplying the circuit 50. That is, I / O
A clock of 33 MHz, which is a low frequency that does not cause dullness, is input from the pad 10, and the PLL circuit 4
It is locked to a frequency of 100 MHz, which is about three times as high as 0, and is supplied to the subsequent additional clock circuit 50 as CLK_in. The frequency of 100 MHz is a high frequency that is difficult to apply from the outside, but since it is internally generated in the chip 100, there is no problem of signal rounding. The internal structure of the PLL circuit 40 is illustrated in FIG. 2 (described later).

The additional clock circuit 50 is a circuit for supplying a clock signal (CLK-out) for synchronization to the sequential circuit block 30, and more specifically, it is internally generated from the PLL circuit 40. Received clock signal (CLK_in), and the same frequency as this clock frequency (100M
In the case of Hz, two pulse waves are generated at 2 × 10 ⁻⁸ seconds) and can be distributed to each SRL 31 ... As a clock signal CLK-out. As a result, the delay pulse test of the sequential circuit block 30 can be performed in an AC manner.

Further, the additional clock circuit 50 has a TEST_ON signal input from each of the I / O pads 13 and 14 and an S signal.
The operation mode can be controlled externally by the ELECT signal. Of these, the SELECT signal is
This is a signal for selecting the pulse test mode or the normal operation. That is, the SELECT signal is high (Hig
h) level, the chip 100 is in normal operation, and the additional clock circuit 50 is the PLL circuit 40.
The clock signal (CLK_in) (for example, 100 MHz) input from the above is directly distributed to each SRL 31 ... On the contrary, when the SELECT signal is at the low level, it is in the delay pulse test mode, and the additional clock circuit 5
A clock generated within 0 (that is, a delay pulse composed of two pulse waves) is distributed to each SRL 31.
On the other hand, the TEST_ON signal is a signal for informing the additional clock circuit 50 of the start of the delay pulse test, and the additional clock circuit 50 delays the delay test in response to the transition of the TEST_ON signal to the high level. It is designed to start pulse generation. The internal configuration of the additional clock circuit 50 is illustrated in FIG. 3 (described later).

B. PLL Circuit FIG. 2 illustrates the configuration of a PLL circuit 40 that can be used in this embodiment. In the figure, the PLL circuit 40 is
/ N frequency dividing circuit 41, phase comparison circuit 42, low-pass filter 43, amplifier 44, voltage controlled oscillation circuit (VCO)
45 and a 1 / m frequency dividing circuit 46.

The frequency dividing circuits 41 and 46 are circuits for multiplying the frequency by an integer, and the 1 / n frequency dividing circuit 41 has a frequency f _{i of} a clock input from the outside via the I / O pad 10.
To 1 / n, and the 1 / m frequency divider circuit 46 sets the VCO 45
There has been a frequency f _o which is output so that the 1 / m. The phase comparison circuit 42 inputs the output frequencies f _i / n and f _o / m of the frequency dividing circuits 41 and 46, compares them, and outputs an error proportional to the phase difference f _i / n−f _o / m. It is designed to output a signal. This error signal is a low-pass filter 43.
The low-frequency noise portion is removed by the input signal, is amplified by the amplifier 44, and is then input to the VCO 45 as the control voltage V _c . VCO45, together with the absence of the reference signal and outputs the inherent oscillation frequency f _o, and is adapted to change the frequency f _o in accordance with the control voltage V _c.
Therefore, the loop formed by the circuits 42, 43, 44, 45, and 46 changes the output frequency f _{o in the} direction in which the control voltage V _c decreases, and the phases of f _i / n and f _o / m match. It is designed to let you. And f _i / n, f _o / m
When the phases of the two coincide with each other, they act to lock this state, and operate by following changes in the input frequency f _i .

When the PLL circuit 40 is in the locked state, the following equation (1) f _i / n = f _o / m (1) is established between the input frequency f _i and the output frequency f _o . the output frequency f _o is, the following formula
It will be locked to the value of (2). _{f o = m · f i /} n ... (2)

In this embodiment, an external input clock f
_{Since i} is 33 MHz, by setting the parameters of the frequency dividing circuits 41 and 46 so that m / n = 3,
That is, the clock signal CLK_in having an internal clock of the chip 100 of 100 MHz can be generated.

The PLL circuit itself is already well known as described above, and is not limited to the configuration shown in FIG.

C. Additional Clock Circuit FIG. 3 shows an additional clock circuit 5 usable in this embodiment.
0 illustrates a detailed configuration of 0. In the figure, the additional clock circuit 50 includes six D flip-flops (D
FF) 51, 52, 53, 54, 55, 56 and NOT
Gate 61 and four AND gates 62, 63, 64,
65, an OR gate 66, and a selector circuit 67.

Each of the DFFs 51 ... Is a delay circuit which delays the input signal until the next clock pulse and outputs it (well known). The DFFs 51, 52 and 55 put the output (CLK_in) of the PLL circuit 40 into the CLK terminal as it is, and other DF
F53, 54, and 56 are CKL_in via the NOT gate 61.
Is inverted to the CLK terminal. The DFF 51 receives a TEST_ON signal from the outside and supplies its output Q to one input terminal of the AND gate 62 and the DFF 52. The DFF 52 outputs the inverted output NQ to the AND gate 6
2 is applied to the other input terminal. AND gate 62
Is the output Q (DFF51_Q) of DFF51 and DFF5
The logical product of the inverted output NQ (DFF52_NQ) of 2 is D
It is put in both the FF 55 and the AND gate 64. DF
The F55 gives its output Q to one of the input terminals of the AND gate 65. The DFF53 is a TE like the DFF51.
Input ST_ON signal and output Q to AND gate 63
It is given to one of the input terminals and the DFF 54. DFF
54 applies the inverted output NQ to the other input terminal of the AND gate 63. The AND gate 63 has a DFF5
The logical product of the output Q (DFF53_Q) of 3 and the inverted output NQ (DFF54_NQ) of the DFF54 is calculated as DFF56 and A
It is put in both of the ND gates 64. AND gate 64
Inputs the logical product of the output of the AND gate 62 and the output of the AND gate 63 into one input terminal of the OR gate 66. The DFF 56 gives its output Q to the other input terminal of the AND gate 65. AND gate 65 is DF
The logical product of the output Q (DFF55_Q) of the F55 and the output Q (DFF56_Q) of the DFF 56 is input to the other input terminal of the OR gate 66. The OR gate 66 takes the logical sum of the outputs of the AND gates 64 and 65 and puts it in the input terminal A of the selector circuit 67. The selector circuit 67 is
Furthermore, the output CLK_in of the PLL circuit 40 is input to the input terminal B, and the SELECT signal from the outside is input to the S input terminal, and only one of the inputs A and B is selectively selected according to the level of the input S. It is designed to output. More specifically, while the SELECT signal is at a high level (that is, during normal operation), the input B is directly output,
Conversely, the input A (that is, the output of the OR gate 67) is output while the SELECT signal is at the low level (that is, during the delay pulse test). The output of the selector circuit 67 is distributed as a synchronizing clock signal (CLK_out) in the chip 100 to each latch circuit 31 ... Of the sequential circuit block 30.

FIG. 4 shows a timing chart of the DFFs 51 ... In the additional clock circuit 50.
The pulse test (Fig. 4 (a)) and the normal operation (Fig. 4 (b)) are shown separately.

When performing the delay / pulse test, FIG.
As shown in (a), a low-level SELECT signal is input. When the TEST_ON signal goes high,
The DFF 51 turns its output Q to a high level in synchronization with the next rising edge (T ₁ ) of the clock. DFF52
Receives the DFF 51_Q and turns its inverted output NQ to a low level in synchronization with the next rising edge (T ₃ ) of the clock. Then, the AND gate 62 outputs the DF
The logical product of F51_Q and DFF52_NQ is calculated to obtain T ₁
Outputs high level only during ~ T ₃ . On the other hand, DFF
Since 53 is inverting the clock CLK_in, TEST
After the _ON signal transits to the high level, its output Q is switched to the high level in synchronization with the first falling edge (T ₂ ) of the clock. The DFF 54 receives the DFF 53_Q and turns its inverted output NQ to a low level in synchronization with the next falling edge (T ₄ ) of the clock. And AND
The gate 63 takes the logical product of DFF53_Q and DFF54_NQ, outputs only high for the T ₂ through T _4. Further, the AND gate 64 includes the AND gate 62,
The logical product of 63 is taken and the high level is output only during the time T _{2 to} T ₃ . The DFF 55 turns its output Q to a high level in synchronization with the rising edge (T ₃ ) of the first clock after the output of the AND gate 62 has turned to a high level, and further rises the next clock (T ₅ ). The output Q is returned to the low level in synchronization with. Also, DFF
The reference numeral 56 changes its output Q to a high level in synchronization with the falling edge (T ₄ ) of the first clock after the output of the AND gate 63 has changed to a high level, and the falling edge of the next clock (T ₄ ). ₆ ) its output Q goes low
Return to level. AND gate 65 takes the logical product of DFF55_Q and DFF56_Q, only during the time T ₄ through T ₅ outputs a high level. Then, the OR gate 66
Takes the logical sum of the AND gates 64 and 65 to obtain the time T
Outputs a high level between ₂ through T ₃ and T ₄ through T _5. In this case, since the SELECT signal is at the low level, the selector circuit 67 selectively outputs the output of the OR gate 66 as CLK_out. Therefore, the output CLK_out of the additional clock circuit 50 becomes two pulse waves with the same interval as the normal clock signal CLK-in.

On the other hand, during normal operation, FIG.
As shown in (b), the high level SELECT signal is input. Also in this case, D in the additional clock circuit 50
The FFs 51 ... Operate in the same manner as in FIG. 4A, but the selector circuit 67 uses the input B, that is, the normal clock signal CLK-.
Output in as it is as CLK-out.

The generation of the pulse wave having the same period as the input clock is a matter which can be easily designed and manufactured by those skilled in the art, and the additional clock circuit 50 is limited to the configuration shown in FIG. is not.

The semiconductor integrated circuit 100 according to this embodiment is
The PLL circuit 40 and the additional clock circuit 50 are included in one chip. That is, a valuable mounting area is occupied for a circuit portion other than the original logic circuit of the LSI, which leads to an increase in cost such as material cost. However, by providing the PLL circuit 40 and the additional clock circuit 50 in the inside, the A speed is the same as the actual operation.
A C-like delay pulse test can be performed, and a defective wafer / chip can be found and removed at an early stage of the circuit manufacturing process. Therefore, it is possible to omit an extra manufacturing cost for defective products, so that it can be said that the merit of the present invention is more than the demerit in mounting area.

The present invention has been described in detail above with reference to the specific embodiments. However, it is obvious that those skilled in the art can modify or substitute the embodiments without departing from the scope of the present invention. That is, the present invention has been disclosed in the form of exemplification, and should not be limitedly interpreted. In order to determine the gist of the present invention, the section of the claims described at the beginning should be taken into consideration.

[0038]

As described above in detail, according to the present invention,
It is possible to provide a synchronous semiconductor integrated circuit with a scan path design that can perform a delay pulse test at a high frequency equivalent to an internal clock.

Therefore, in the semiconductor integrated device according to the present invention, a relatively low frequency clock signal is input from the outside,
Based on the input clock, a relatively high frequency clock signal, which is the same as that during normal operation, is supplied to the internal clock generator (eg PLL
Circuit) to generate a delay pulse having the same delay width as the cycle of the internal clock signal. Therefore, if a scan path test is performed using the delay pulse as a timing, the same AC test as the normal operation of the semiconductor integrated circuit can be performed, so that the problem of clock skew can be sufficiently verified.

[Brief description of drawings]

FIG. 1 is a schematic view showing, of a semiconductor integrated circuit embodying the present invention, only constituent elements particularly relevant to the gist of the present invention.

FIG. 2 is a diagram illustrating a P that can be used in a semiconductor integrated circuit 100.
It is the figure which illustrated the structure of the LL circuit.

FIG. 3 is a diagram showing a configuration of an additional clock circuit 50.

FIG. 4 is a diagram showing a timing chart of each flip-flop in the additional clock circuit 50. More specifically, FIG. 4 (a) shows a timing chart in the delay pulse test. FIG. 4B is a diagram showing a chart, and FIG. 4B is a diagram showing a timing chart during normal operation.

FIG. 5 (a) is a diagram schematically illustrating a part of a circuit having a scan path design, and FIG. 5 (b) is a signal (delay) input to a clock when a delay pulse test is performed.・
It is the figure which showed the chart of (pulse).

[Explanation of symbols]

10 ... I / O pad, 11 ... SI pad, 12 ... SO pad, 13 ... TEST_ON pad, 14 ... SELECT pad, 2
0 ... Combination circuit block, 30 ... Sequential circuit block, 4
0 ... PLL circuit, 41 ... 1 / n frequency divider circuit, 42 ... Phase comparator circuit, 43 ... Low-pass filter, 44 ... Amplifier, 45 ... Voltage controlled oscillator circuit, 46 ... 1 / m frequency divider circuit, 50 ... Additional Clock circuit, 51, 52, 53, 54, 55, 56 ...
D flip-flop, 61 ... NOT gate, 62, 6
3, 64, 65 ... AND gate, 66 ... OR gate, 6
7 ... Selector circuit, 100 ... Semiconductor integrated circuit.

Claims (6)

[Claims] 1. A semiconductor integrated circuit which is composed of a circuit block including a plurality of sequential circuits having a scan path design and which operates synchronously receives a test pattern for inspecting the operation of an internal circuit from the outside. A test pattern input section for receiving a first clock signal having a first period from the outside, and a first pattern
A clock generator that generates a second clock signal having a second cycle shorter than the first cycle based on the second clock signal, and a second cycle spaced based on the second clock signal. A semiconductor integrated circuit, comprising: a delay pulse generator that generates a delay pulse composed of two pulse waves, and a test of a scan path circuit using the delay pulse as a clock. 2. A semiconductor integrated circuit which is composed of circuit blocks including a plurality of sequential circuits having a scan path design and which operates synchronously, receives a test pattern for inspecting the operation of an internal circuit from the outside. A test pattern input section for receiving a first clock signal having a first period from the outside, and a first pattern
A clock generator that generates a second clock signal having a second cycle shorter than the first cycle based on the second clock signal, and a delay time of a second cycle based on the second clock signal. A semiconductor integrated circuit comprising: a delay pulse generator that sequentially outputs pulse waves, and a test of a scan path circuit using the pulse waves as a clock. 3. A plurality of scan path designed sequential circuits, and a test pattern input section for receiving a test pattern for inspecting the operation of an internal circuit from the outside.
A clock input section for receiving a first clock signal having a first cycle from the outside, and generating a second clock signal having a second cycle shorter than the first cycle based on the first clock signal. And a pulse generator having a delay time of the second clock signal or the second period, the semiconductor integrated circuit including a clock generating section for operating in synchronization with the second clock signal. 2. A semiconductor integrated circuit comprising an additional clock supply unit for outputting either one of the delay pulses consisting of 4. The additional clock supply unit comprises a scan
4. The semiconductor integrated circuit according to claim 3, wherein the delay pulse is output only when performing the path test, and the second clock signal is output as it is during the other period. 5. A semiconductor integrated circuit comprising a circuit block including a plurality of sequential circuits, wherein the first integrated circuit has a first cycle.
A clock input section for receiving the second clock signal from the outside, a clock generating section for generating a second clock signal having a second cycle shorter than the first cycle based on the first clock signal, and a second And a clock signal conversion processing unit for generating a third clock signal for timing the sequential circuit by inputting the clock signal. 6. The clock signal conversion processing unit comprises a delay circuit composed of two pulse waves spaced by a second period.
The semiconductor integrated circuit according to claim 5, wherein a pulse is generated.