JPH08195775A - Signal transmission circuit - Google Patents
Signal transmission circuitInfo
- Publication number
- JPH08195775A JPH08195775A JP7020952A JP2095295A JPH08195775A JP H08195775 A JPH08195775 A JP H08195775A JP 7020952 A JP7020952 A JP 7020952A JP 2095295 A JP2095295 A JP 2095295A JP H08195775 A JPH08195775 A JP H08195775A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- resistor
- signal line
- signal
- push
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000008054 signal transmission Effects 0.000 title claims description 9
- 230000005540 biological transmission Effects 0.000 abstract description 16
- 238000010586 diagram Methods 0.000 description 5
- 238000004088 simulation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
Landscapes
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は信号伝送回路に関し、特
にドライバとレシーバにより信号の送受を行うディジタ
ル信号線の終端回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission circuit, and more particularly to a digital signal line terminating circuit for transmitting and receiving signals by a driver and a receiver.
【０００２】[0002]
【従来の技術】従来の半導体集積回路において、ドライ
バとレシーバにより信号の送受を行う場合、図４に示す
ように、レシーバ３側の入力端にインピーダンス整合の
ため、終端抵抗器４が接続されるが、この終端抵抗器４
は信号線２とアースとの間に接続されている。2. Description of the Related Art In a conventional semiconductor integrated circuit, when signals are transmitted and received by a driver and a receiver, a terminating resistor 4 is connected to an input end on the receiver 3 side for impedance matching, as shown in FIG. But this termination resistor 4
Is connected between the signal line 2 and the ground.
【０００３】[0003]
【発明が解決しようとする課題】前記従来の信号伝送回
路では、終端抵抗器４が信号線２とアースとの間に接続
されているため、ディジタル信号を伝送するとその信号
の直流成分が終端抵抗器に流れることになり、電力損失
を生じるという問題があった。In the conventional signal transmission circuit described above, since the terminating resistor 4 is connected between the signal line 2 and the ground, when a digital signal is transmitted, the DC component of the signal is terminated. There was a problem that it would flow into the container and cause power loss.
【０００４】また、この電力損失を補うためドライバ側
の駆動能力を大きくとらなければならないという問題が
あった。In addition, there is a problem that the driving capability on the driver side must be large in order to compensate for this power loss.
【０００５】本発明は上記問題点に鑑みてなされたもの
であって、インピーダンス整合用の終端抵抗器を備えた
信号伝送回路において、終端抵抗器に流れる信号の直流
成分による消費電力を削減する信号伝送回路を提供する
ことを目的とする。The present invention has been made in view of the above problems, and in a signal transmission circuit including a termination resistor for impedance matching, a signal for reducing power consumption due to a DC component of a signal flowing through the termination resistor. An object is to provide a transmission circuit.
【０００６】なお、例えば特開平２−１４６８４３号公
報には、図４に示した前記従来の信号伝送回路における
上記問題点を解決するために、信号線を終端抵抗器の一
端と平均値整流回路の入力とに接続し、平均値整流回路
の出力を等価的電圧制御電圧源の入力に接続し、等価的
電圧制御電圧源の出力を終端抵抗器の他端に接続した、
信号線の終端回路が提案されおり、終端抵抗器を信号線
と信号の直流成分に等しい低インピーダンスの電圧源の
出力との間に接続することにより、終端抵抗器における
直流成分の電力損失を解消する構成が開示されている。
しかしながら、以下の説明で明らかとされるように、本
発明は、前記特開平２−１４６８４３号公報に開示され
た回路構成とは全く相違した設計方式により、例えば１
００ＭＨｚを越える高速ディジタル信号の伝送を実現す
るものである。Incidentally, for example, in Japanese Patent Laid-Open No. 2-146843, in order to solve the above-mentioned problems in the conventional signal transmission circuit shown in FIG. 4, a signal line is connected to one end of a terminating resistor and an average value rectification circuit. , The output of the average value rectifier circuit is connected to the input of the equivalent voltage controlled voltage source, and the output of the equivalent voltage controlled voltage source is connected to the other end of the terminating resistor,
A termination circuit for the signal line has been proposed, which eliminates the power loss of the DC component in the termination resistor by connecting the termination resistor between the signal line and the output of a voltage source with a low impedance equal to the DC component of the signal. A configuration is disclosed.
However, as will be apparent from the following description, the present invention uses a design method that is completely different from the circuit configuration disclosed in Japanese Patent Laid-Open No. 2-146843, for example,
It realizes transmission of high-speed digital signals exceeding 00 MHz.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するた
め、本発明の信号伝送回路は、信号線を終端抵抗器の一
端とＣＭＯＳトランジスタからなるプッシュプル回路と
に接続したことを特徴とする。To achieve the above object, a signal transmission circuit of the present invention is characterized in that a signal line is connected to one end of a terminating resistor and a push-pull circuit composed of a CMOS transistor.
【０００８】また、本発明においては、前記終端抵抗器
を帰還抵抗とする正帰還回路を具備することを特徴とす
る。Further, the present invention is characterized by comprising a positive feedback circuit using the terminating resistor as a feedback resistor.
【０００９】そして、本発明においては、好ましくは、
信号線を終端抵抗器の一端と反転バッファを介してＣＭ
ＯＳトランジスタからなるプッシュプル回路の入力端に
接続すると共に、前記終端抵抗器の他端を前記ＣＭＯＳ
トランジスタからなるプッシュプル回路の出力端とレシ
ーバ回路の入力端とに接続したことを特徴とする。In the present invention, preferably,
CM the signal line through one end of the terminating resistor and the inverting buffer
It is connected to the input end of a push-pull circuit composed of an OS transistor and the other end of the terminating resistor is connected to the CMOS.
It is characterized in that it is connected to an output end of a push-pull circuit composed of transistors and an input end of a receiver circuit.
【００１０】[0010]
【作用】本発明によれば、伝送回路の入力端はインピー
ダンス整合のための終端抵抗器を介して正帰還回路を構
成し、ＣＭＯＳトランジスタからなるプッシュプル回路
の入力端に接続することにより、終端抵抗器に流れる伝
送信号の直流成分を遮断し、電力消費を削減している。According to the present invention, the input end of the transmission circuit constitutes a positive feedback circuit through a terminating resistor for impedance matching, and is connected to the input end of the push-pull circuit composed of CMOS transistors, thereby terminating. The direct current component of the transmission signal that flows through the resistor is cut off to reduce power consumption.
【００１１】[0011]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【００１２】[0012]
【実施例１】図１は本発明の第１の実施例の回路構成を
示している。[Embodiment 1] FIG. 1 shows a circuit configuration of a first embodiment of the present invention.
【００１３】図１を参照して、ドライバ回路１が送信し
た信号は、信号線２を通してレシーバ回路３で受信さ
れ、インピーダンス整合のため、レシーバ入力端に終端
抵抗器４が接続されている。すなわち、信号線２は終端
抵抗器４の一端に接続されると共に、インバータ５を介
してＣＭＯＳトランジスタからなるプッシュプル回路
（「ＣＭＯＳプッシュプル回路」という）６の入力端に
接続されている。そして、終端抵抗器４の他端はレシー
バ回路３の内部回路に接続されると共に、ＣＭＯＳプッ
シュプル回路６の出力端に接続されている。Referring to FIG. 1, the signal transmitted by the driver circuit 1 is received by the receiver circuit 3 through the signal line 2, and a terminating resistor 4 is connected to the receiver input end for impedance matching. That is, the signal line 2 is connected to one end of the terminating resistor 4 and is also connected to the input end of a push-pull circuit (referred to as “CMOS push-pull circuit”) 6 including a CMOS transistor via the inverter 5. The other end of the terminating resistor 4 is connected to the internal circuit of the receiver circuit 3 and the output end of the CMOS push-pull circuit 6.
【００１４】インバータ５とＣＭＯＳプッシュプル回路
６とは終端抵抗器４を帰還抵抗とする正帰還構成をとっ
ている。これにより、信号線２を流れる伝送信号の直流
成分を遮断することができ、全体の電力消費を削減でき
る。The inverter 5 and the CMOS push-pull circuit 6 have a positive feedback configuration in which the termination resistor 4 is used as a feedback resistor. As a result, the DC component of the transmission signal flowing through the signal line 2 can be cut off, and the overall power consumption can be reduced.
【００１５】次に、図２を参照して、本実施例の伝送回
路のＡＣ特性を説明する。Next, the AC characteristics of the transmission circuit of this embodiment will be described with reference to FIG.
【００１６】図２は、０．５５μｍルールのＣＭＯＳト
ランジスタで電源電圧を３．３Ｖとした場合（周囲温度
２５℃）の本実施例の伝送回路の回路シミュレーション
によるＡＣ解析結果を示す図であり、横軸は周波数、縦
軸は電圧及びデシベルを表わし、各周波数の入力信号
（入力電圧）に対する伝送回路の出力特性（出力電圧）
を示している。また出力電圧は虚数部とゲイン（デシベ
ル表示）としても表わされている。FIG. 2 is a diagram showing an AC analysis result by a circuit simulation of the transmission circuit of this embodiment when the power supply voltage is 3.3 V in the 0.55 μm rule CMOS transistor (ambient temperature 25 ° C.), The horizontal axis represents frequency and the vertical axis represents voltage and decibel, and the output characteristics (output voltage) of the transmission circuit with respect to the input signal (input voltage) of each frequency
Is shown. The output voltage is also represented as an imaginary part and a gain (decibel display).
【００１７】図２を参照して、本実施例に係る伝送回路
においては、レシーバ回路３への入力信号の周波数を１
ＭＨｚ〜１ＧＨｚとしたときでも、正帰還回路特有の発
振現象は見られないことが確認される。Referring to FIG. 2, in the transmission circuit according to this embodiment, the frequency of the input signal to the receiver circuit 3 is set to 1
It is confirmed that the oscillation phenomenon peculiar to the positive feedback circuit is not observed even when the frequency is set to MHz to 1 GHz.
【００１８】[0018]
【実施例２】次に、本発明の第２の実施例について、図
３を参照して説明する。Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIG.
【００１９】本実施例においては、前記第１の実施例に
おけるＣＭＯＳトランジスタからなるプッシュプル回路
６の電源電圧を入力信号の電圧振幅よりも大きくとって
いる。例えば、入力信号の振幅電圧の最大値を３．３Ｖ
とした場合、ＣＭＯＳプッシュプル回路６の電源電圧を
５．０Ｖとする。これにより、出力電圧のノイズマージ
ンを大きくとることができる。In the present embodiment, the power supply voltage of the push-pull circuit 6 composed of the CMOS transistor in the first embodiment is set to be larger than the voltage amplitude of the input signal. For example, the maximum value of the amplitude voltage of the input signal is 3.3V
In that case, the power supply voltage of the CMOS push-pull circuit 6 is set to 5.0V. As a result, a large noise margin of the output voltage can be secured.
【００２０】[0020]
【発明の効果】以上説明したように本発明は、伝送回路
の入力端においてインピーダンス整合のための終端抵抗
器を介して正帰還回路を構成し、ＣＭＯＳトランジスタ
からなるプッシュプル回路に接続することにより、信号
線を流れる伝送信号の直流成分を遮断し、電力消費を大
幅に削減するという効果を有する。また、本発明は簡易
な回路構成により、高速ディジタル信号の伝送に対処で
きるという利点を有する。As described above, according to the present invention, the positive feedback circuit is configured at the input end of the transmission circuit through the terminating resistor for impedance matching, and is connected to the push-pull circuit composed of CMOS transistors. The DC component of the transmission signal flowing through the signal line is blocked, and the power consumption is significantly reduced. Further, the present invention has an advantage that it can cope with the transmission of high-speed digital signals with a simple circuit configuration.
【図１】本発明の第１の実施例の構成を示す回路図であ
る。FIG. 1 is a circuit diagram showing a configuration of a first exemplary embodiment of the present invention.
【図２】本発明の第１の実施例のＡＣ特性を説明するた
めのシミュレーション結果を示す図である。FIG. 2 is a diagram showing simulation results for explaining the AC characteristics of the first example of the present invention.
【図３】本発明の第２の実施例の構成を示す回路図であ
る。FIG. 3 is a circuit diagram showing a configuration of a second exemplary embodiment of the present invention.
【図４】従来の伝送回路におけるレシーバ側の入力端部
を示す回路図である。FIG. 4 is a circuit diagram showing an input end portion on a receiver side in a conventional transmission circuit.
１ ドライバ回路 ２ 信号線 ３ レシーバ（内部）回路 ４ 終端抵抗器 ５ インバータ ６ ＣＭＯＳプッシュプル回路 1 Driver Circuit 2 Signal Line 3 Receiver (Internal) Circuit 4 Termination Resistor 5 Inverter 6 CMOS Push-Pull Circuit
Claims (3)
ンジスタからなるプッシュプル回路の入力端とに接続し
たことを特徴とする信号伝送回路。1. A signal transmission circuit comprising a signal line connected to one end of a terminating resistor and an input end of a push-pull circuit composed of a CMOS transistor.
路を具備する請求項１記載の信号伝送回路。2. The signal transmission circuit according to claim 1, further comprising a positive feedback circuit using the termination resistor as a feedback resistor.
を介してＣＭＯＳトランジスタからなるプッシュプル回
路の入力端に接続すると共に、前記終端抵抗器の他端を
前記ＣＭＯＳトランジスタからなるプッシュプル回路の
出力端とレシーバ回路の入力端とに接続してなることを
特徴とする信号伝送回路。3. A signal line is connected to one end of a termination resistor and an input end of a push-pull circuit composed of a CMOS transistor via an inverting buffer, and the other end of the termination resistor is composed of a push-pull circuit composed of the CMOS transistor. A signal transmission circuit, characterized in that it is connected to the output end of the receiver and the input end of the receiver circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7020952A JP2897672B2 (en) | 1995-01-13 | 1995-01-13 | Signal transmission circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7020952A JP2897672B2 (en) | 1995-01-13 | 1995-01-13 | Signal transmission circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08195775A true JPH08195775A (en) | 1996-07-30 |
| JP2897672B2 JP2897672B2 (en) | 1999-05-31 |
Family
ID=12041534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7020952A Expired - Lifetime JP2897672B2 (en) | 1995-01-13 | 1995-01-13 | Signal transmission circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2897672B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002330182A (en) * | 2001-02-05 | 2002-11-15 | Samsung Electronics Co Ltd | Apparatus and method for updating impedance of termination circuit |
| KR100627944B1 (en) * | 2001-08-29 | 2006-09-22 | 자링크 세미컨덕터, 인크 | Subband Echo Location and Double-Talk Detection in Communication system |
| JP2008072693A (en) * | 2006-06-28 | 2008-03-27 | Intel Corp | Dynamic transmission line termination |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03116214A (en) * | 1989-09-29 | 1991-05-17 | Hitachi Ltd | Terminating circuit |
| JPH0661836A (en) * | 1992-08-05 | 1994-03-04 | Fujitsu Ltd | Termination circuit and waveform shaping circuit |
-
1995
- 1995-01-13 JP JP7020952A patent/JP2897672B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03116214A (en) * | 1989-09-29 | 1991-05-17 | Hitachi Ltd | Terminating circuit |
| JPH0661836A (en) * | 1992-08-05 | 1994-03-04 | Fujitsu Ltd | Termination circuit and waveform shaping circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002330182A (en) * | 2001-02-05 | 2002-11-15 | Samsung Electronics Co Ltd | Apparatus and method for updating impedance of termination circuit |
| KR100627944B1 (en) * | 2001-08-29 | 2006-09-22 | 자링크 세미컨덕터, 인크 | Subband Echo Location and Double-Talk Detection in Communication system |
| JP2008072693A (en) * | 2006-06-28 | 2008-03-27 | Intel Corp | Dynamic transmission line termination |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2897672B2 (en) | 1999-05-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19990209 |