JPH08190789A - Dynamic semiconductor storage - Google Patents

Abstract

PURPOSE: To reduce the power consumption of or to attain the high speed of a dynamic semiconductor storage. CONSTITUTION: Different sub-decode signals are supplied to respective blocks BL1 to BLm consisting of a memory array. These sub-decode signals are generated from addresses for block selections BS1 to BSm and addresses for sub-decode signals SDA1 to SDA2 respectively given to respective blocks in sub-decode signal generating circuits SDB11 to SDB1m provided corresponding to respective blocks BL1 to BLm . Thus, the number of sub-decode circuits and lengths of signal lines borne by one sub-decode signal generating circuit are reduced by supplying sub-decode signals only to sub-decode circuits of one block specified with a block selection address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention employs a division decoder system having a main word line and a sub word line, and performing decoding for selectively activating a word line to select a memory cell in two stages. More particularly, the present invention relates to a dynamic semiconductor memory device in which a memory cell array is divided into a plurality of blocks and a sense amplifier array is provided for each block.

[0002]

2. Description of the Related Art Conventionally, as an example of a method for reducing the rise time constant of a word line, there is a metal stake method in which the word line is lined with a first aluminum wiring layer. But,
As the miniaturization progresses, the pitch of the first aluminum wiring becomes narrower, and the possibility of yield decrease due to this narrowing increases, so that the relaxation of the pitch of the word line is an important technology.

As one method for realizing this, for example, NEC Technical Report Vol. 47 No. 3/19
94, pp69-73, there is a division decoder system, and by dividing the word line driver, the rise time constant of the word line can be reduced.

This system uses a main row decoder (hereinafter referred to as MRD).
Say. ) Selects a sub-word line by the main word line selectively activated by (4) and the decoded sub-decode signal. For example, the main word line is wired using the first metal wiring, the signal line for transmitting the sub-decode signal is wired using the second metal wiring, for example, and the sub word line is the transistor gate wiring. Be wired. Then, the sub word line is connected to a drive circuit for driving the sub word line according to the states of the main word line and the sub decode signal. By dividing the decoder for driving the main word line and the driving circuit for driving the sub word line, the load of the word line can be distributed and the word line can be started up at high speed. Further, as compared with the metal stakeout method, the pitch of the first metal wiring can be increased as the number of ways of the sub-decode signal increases.
Here, the number of ways corresponds to the number of rows of the memory cell array carried by all the sub word lines provided for one main word line.

In a dynamic random access memory (hereinafter referred to as DRAM), the power consumption increases as the number of memory cells constituting the memory cell increases. Therefore, the memory cell array is divided into a plurality of blocks, and each divided block is divided into blocks. In some cases, a sense amplifier is provided so that the read operation can be performed only on a necessary block.

FIGS. 16 and 17 show an example of a structure expected when the conventional division decoder system is applied to a conventional DRAM which divides a memory cell array into a plurality of blocks. FIG. 16 is a block diagram showing a main part of the structure of a DRAM in which the memory cell array is divided into a plurality of blocks.
In the figure, BL _{1 to} BL _m are blocks that form a memory cell array including a plurality of memory cells arranged in rows and columns, M
RD _{1 to} MRD _m are each block BL ₁ of the memory cell array
To main row decoders provided corresponding to BL _m ,
SA _{1 to} SA _m are sense amplifier rows provided corresponding to the blocks BL _{1 to} BL _m , respectively, and Bu ₁₀₁ is to prevent undesired electrical interaction between the circuit for generating the subdecode signal SDA ₁ and the subdecode circuit. A buffer to do
Bu ₁₀₂ denotes a buffer for preventing undesirable electrical interaction between the circuit and the sub-decoding circuit for generating a sub decode signal bar SDA ₁ which is a complementary signal of the sub decode signal SDA _1, Bu ₁₀₃ sub decode signal SDA ₂ buffer for preventing undesirable electrical interaction between the circuit and the sub-decoding circuit for generating, Bu ₁₀₄ circuit generating a sub decode signal bar SDA ₂ is a complementary signal of the sub decode signal SDA ₂ is a sub-decoding circuit Buffer to prevent undesired electrical interaction with
Reference numerals 201 to 204 are signal lines connected to the outputs of the buffers Bu _{101 to} Bu ₁₀₄ and arranged on the memory cell array for transmitting sub-decode signals, and 101 is a block BL.
Sub-decode band composed of a plurality of sub-decode circuits arranged in an odd column of ₁ , 102 is a sub-decode band composed of a plurality of sub-decode circuits arranged in an even column of block BL ₁ , 111 is an odd column of block BL ₂ . A sub-decode band composed of a plurality of sub-decode circuits arranged in
Is a sub-decode band composed of a plurality of sub-decode circuits arranged in an even column of the block BL ₂ .

A plurality of columns of subdecode bands are provided in the plurality of blocks BL _{1 to} BL _m , and each block BL ₁
In the sub-decode bands of the odd columns of ˜BL _m, the sub-decode signal SDA is passed through a plurality of sets of buffers Bu ₁₀₁ , Bu _102.
1 , bar SDA ₁ is supplied, and the sub-decode band SDA ₂ and bar SDA ₂ are supplied to the even-numbered sub-decode band through a plurality of sets of buffers Bu ₁₀₃ , Bu ₁₀₄ . Therefore, the sub-decode band in the same column of each block BL ₁ to BL _m, regardless of the same sub decode signal and that the block is one selected state or non-selected state are simultaneously supplied.

FIG. 17 is a block diagram showing an arrangement of sub-decoding circuits in each of the plurality of blocks shown in FIG. In FIG. 17, MWL _{1 to} MWL _m are first to mth main word lines, and SWL _{1a to} SWL _1b are connected to some of the plurality of memory cells in the first row of the block BL ₁ . Word line, SWL _{2a to} SWL _2b
Is a sub-word line connected to some of the plurality of memory cells in the second row of the block BL ₁ , D101 is connected to the main word line MWL ₁ and the sub-word line SWL _1a , and the _first word of the block BL ₁ is A sub-decode circuit belonging to the sub-decode band in the first column, D102, is connected to the main word line MWL ₁ and the sub word line SWL _2a, and is connected to the block B.
A sub-decode circuit belonging to the sub-decode band of the second column of L ₁ , D103 is a main word line MWL ₁ and a sub word line SW
A sub-decoding circuit connected to L _1b and belonging to the sub-decoding band in the third column of the block BL ₁ , D104
Be a sub-decoding circuits belonging to the main word line MWL ₂ and the first row of sub-decode band blocks BL ₁ is connected to the sub word line corresponding to some of the third row of the memory cell blocks BL ₁ The same reference numerals as those in FIG. 16 are the same portions as those shown in FIG.

When the number of columns of the sub-decoding band is increased,
It is possible to shorten the length of the sub-word line per sub-decoding circuit and reduce the number of memory cells, but conversely, the number of sub-decoding circuits increases and power consumption increases, and the sub-decoding This has the adverse effect of increasing the area for arranging the circuit.

The main word lines MWL _{1 to} MWL _m are arranged in parallel with the sub word lines, that is, the transfer gates in the memory cells, and the sub word lines are n−1 in the main word line direction with respect to the main word line length. Is divided into Sub-decode bands 101 to 104 and the like are arranged at the divided boundary portion. Main word lines MWL _{1 to} MW on this sub-decode band
Sub-decode signal SDA ₁ , bar S so that it is orthogonal to L _m
Signal line 201 for transmitting DA ₁ , SDA ₂ , and bar SDA ₂
~ 204 etc. are arranged. A sub-decode circuit (hereinafter referred to as SRD) is provided at the intersection of the main word line and the sub-decode signal.
To place. The detailed structure of the SRD is shown in FIG. In FIG. 18, Q1 is a P-channel MOS transistor having one current electrode to which the sub-decode signal SDA is applied, the other current electrode connected to the sub word line SWL, and a control electrode connected to the main word line, and Q2 is the sub word line. An N-channel MOS transistor having one current electrode connected to SWL, a control electrode connected to main word line MWL, and the other current electrode grounded, Q3 is a sub word line SW
One current electrode connected to L, subdecode signal SDA
Is an N-channel MOS transistor having a control electrode to which is applied and the other current electrode which is grounded. Table 1 shows the operation of the sub-decode circuit. In Table 1, V
_PP is a voltage higher than the voltage V _CC , and gnd is a ground voltage.

[0011]

[Table 1]

A voltage gn is applied to the main word line MWL when activated.
d is applied, and when inactive, the voltage V _PP is applied. Further, when activated, the voltage V is set as the sub-decode signal SDS.
_{When PP} is applied and the voltage gnd is applied as the sub-decode signal bar SDS, when it is inactive, the sub-decode signal S
The voltage gnd is applied as DS, and the voltage V _CC is applied as the sub-decode signal bar SDS. Therefore, in the standby mode, the voltage V _PP is applied to the main word line MWL, and the voltage gn is applied to the signal line as the sub-decode signal SDS.
d is applied, and the voltage V _CC is applied to the signal line as the sub-decode signal bar SDS.

When the main word line MWL is activated, the ground voltage gnd is applied to the main word line, and the sub-decode signal SDA is applied to one current electrode of the transistor Q1 in order to activate the sub-word line. The voltage V _PP is applied. Therefore, the transistor Q1 is turned on, and the voltage V _PP is applied to the sub word line SWL. Since the high voltage V _PP is applied as the sub-decode signal SDA when activated, the power consumption of the buffer Bu ₁₀₁ or Bu ₁₀₃ which outputs the sub-decode signal SDA is equal to that of the buffer Bu ₁₀₁ or Bu ₁₀₃ which outputs the voltage V _CC as the sub-decode signal SDA when inactive. It is larger than Bu ₁₀₂ or Bu ₁₀₄ .

The voltage V _PP must be applied to the main word line MWL during standby. However, since many main word lines MWL are wired in the memory cell array, the voltage V _PP is increased due to the leakage current from the main word line MWL. The work of lowering the level becomes greater. Generally, the voltage V _PP is the voltage V _CC
Often obtained by boosting. In such a case, the voltage V _PP circuit operates to occur to hold the level of the voltage V _PP, increasing the standby current. Further, after the standby state is held for a long time and before the circuit for generating the voltage V _PP operates to supply the voltage V _PP again, that is, the level of the voltage V _PP is lowered, the sub-decode signal SDS, When the bar SDS is activated, malfunction may occur.

Incidentally, in FIG.
An interleaved sub-decode configuration of ways is shown. In this case, for example, two sub word lines SWL _1a and SWL _2a are provided for one main word line MWL ₁ . The pitch of one main word line formed by the first metal wiring on the two sub word lines formed by the gate polysilicon can be relaxed to 1/2 as compared with the metal staking method. Further, since the sub-decode signals are arranged alternately, it is possible to arrange only sub-decode circuits receiving the same sub-decode signal for one row of sub-decode bands.

[0016]

In the above-mentioned DRAM constructed by combining the conventional techniques, the address is input in a time-division system, so that the sub-word lines divided at the time when the main word line rises are divided. Must be activated for one column in the main word line direction. Therefore, all subdecode signals and subdecode circuits operate. Therefore, there is a problem that as the number of divisions of the sub-word line increases, the charge / discharge current of the sub-decode signal and the sub-decode circuit increases, and the power consumption increases.

In addition, there is a problem that the leakage current from the main word line is increased during standby and power consumption is increased.

The present invention has been made in order to solve the above-mentioned problems, and the subdecode signal is input not in the direction orthogonal to the main word line but in parallel with the main word line, and By using a signal that has been decoded in advance as a signal for selecting a block, it is possible to charge and discharge only the sub-decode signal and sub-decode circuit related to the block in which the main word line is selected, and charge and discharge in other sub-decode circuits. It is an object of the present invention to obtain a dynamic semiconductor memory device of a division decoder type capable of preventing, activating a word line at a high speed with low consumption and relaxing the pitch of a first metal wiring. Another object is to obtain a dynamic semiconductor memory device that consumes less power during standby.

[0019]

A dynamic semiconductor memory device according to a first invention is divided into a plurality of blocks including at least first and second blocks, and arranged in a plurality of rows and a plurality of columns. A plurality of memory elements for dynamically storing information by accumulating charges and a plurality of main word lines provided in each of the plurality of blocks and arranged in parallel with each other for selecting the memory elements. And a plurality of sub-word lines, and each of the plurality of blocks is formed to have first and second sides parallel to the row and third and fourth sides parallel to the column. Memory cell array, and a plurality of sense amplifier columns provided corresponding to each of the plurality of blocks and arranged to face the first side or the second side of the corresponding block. , For selectively activating the plurality of main word lines in the corresponding block, which is provided corresponding to each of the plurality of blocks and is arranged on the side of the third side of the corresponding block. A plurality of main row decoding means, a plurality of sub row decoding means connected to the plurality of main word lines and a plurality of sub word lines and provided on the memory cell array, and a plurality of sub row decoding means. A plurality of selection signal lines for transmitting selection signals for activating the connected sub-row decoding means, and a plurality of selection signal lines connected to the plurality of selection signal lines for generating the selection signals. Selection signal generating means, and the plurality of main word lines include at least a plurality of first main word lines arranged in the first block and a plurality of first main word lines arranged in the second block. Two A plurality of first sub-word lines and a plurality of second sub-word lines provided corresponding to at least the plurality of first main word lines. , And a plurality of third sub-word lines and a plurality of fourth sub-word lines provided corresponding to the second main word line, the plurality of selection signal lines being at least the first sub-word line. A plurality of first selection signal lines and a plurality of second selection signal lines arranged in the block, and a plurality of third selection signal lines and a plurality of fourth selection signals arranged in the second block A plurality of sub-row decoding means including at least a signal line and arranged on at least the first block, the plurality of first main word lines, the plurality of first sub-word lines, and the plurality of first sub-word lines. A plurality of first sub-row decoding means connected to one selection signal line, the first block A plurality of second sub-row decoding means arranged above and connected to the plurality of first main word lines, the plurality of second sub-word lines and the plurality of second selection signal lines; A plurality of third sub-row decodes arranged on two blocks and connected to the plurality of second main word lines, the plurality of third sub-row word lines and the plurality of third selection signal lines. Means and a plurality of fourth main word lines, a plurality of fourth main word lines, a plurality of fourth sub word lines, and a plurality of fourth selection signal lines connected to the plurality of fourth main word lines. The plurality of selection signal generating means including sub-row decoding means are provided corresponding to at least the first block, are connected to the first selection signal line, and generate and output a first selection signal. First selection signal generating means, the first selection signal generating means being provided corresponding to the first block; Second selection signal generating means connected to the selection signal line for generating a second selection signal and outputting the second selection signal, and a third selection signal generating means provided corresponding to the second block and connected to the third selection signal line. Third for generating and outputting a selection signal
A plurality of selection signal generating means provided corresponding to the second block, connected to the fourth selection signal line, and generating and outputting a fourth selection signal. When one of the first main word lines of the first main word line is activated, the first and second sub-row decoding means corresponding to the activation of the first main word line is performed. Although the word lines can be activated at the same time,
In the first block, which of the first and second sub-word lines is to be activated is determined by the first block.
And a second main signal line selected from the plurality of second main word lines is activated, the third and fourth sub-lines corresponding to the second main word line are activated. The row decoding means brings the third and fourth sub-word lines into a state in which they can be activated at the same time. The second block determines which of the third and fourth sub-word lines is activated. Is characterized in that selection is made by the third and fourth selection signals.

A dynamic semiconductor memory device according to a second invention is the dynamic semiconductor memory device according to the first invention, wherein a plurality of the selection signal lines are arranged on a plurality of the sense amplifier columns. Characterize.

A dynamic semiconductor memory device according to a third invention is the dynamic semiconductor memory device according to the first invention, wherein the plurality of selection signal generating means are provided on the side of the third side of the plurality of blocks. It is characterized by being arranged.

A dynamic semiconductor memory device according to a fourth invention is the dynamic semiconductor memory device according to the first invention, wherein the first and second blocks are arranged adjacent to each other and the second selection signal is generated. And the third selection signal are the same, and the second and third selection signal lines and the second and third selection signal generation means are shared.

A dynamic semiconductor memory device according to a fifth aspect of the present invention is the dynamic semiconductor memory device according to the first aspect, wherein the plurality of selection signal generating means are provided on the fourth side of the plurality of blocks. It is characterized by being arranged.

A dynamic semiconductor memory device according to a sixth invention is the dynamic semiconductor memory device according to the first invention, characterized in that a plurality of the selection signal lines are arranged on a plurality of the blocks. To do.

A dynamic semiconductor memory device according to a seventh invention is the dynamic semiconductor memory device according to the first invention, wherein a plurality of the sub word lines are provided corresponding to a plurality of the first main word lines. A plurality of fifth sub-word lines and a plurality of sixth sub-word lines, and a plurality of seventh sub-word lines and a plurality of eighth sub-word lines provided corresponding to the second main word line. A plurality of the selection signal lines further includes a word line, and the plurality of selection signal lines are arranged in the plurality of fifth selection signal lines and the plurality of sixth selection signal lines and the second block. A plurality of seventh selection signal lines and a plurality of eighth selection signal lines that are provided, wherein the plurality of sub-row decoding means are arranged on the first block and the plurality of first main signal lines are provided. A word line and a plurality of the fifth sub word lines and a plurality of the fifth selections A plurality of fifth sub-row decoding means connected to a signal line, a plurality of the first main word lines, a plurality of the sixth sub word lines, and a plurality of the sixth sub-word lines arranged on the first block. A plurality of sixth signals connected to the selection signal line of
Sub-row decoding means, which is arranged on the second block and is connected to the plurality of second main word lines, the plurality of seventh sub-row word lines, and the plurality of seventh selection signal lines. A plurality of seventh sub-row decoding means and a plurality of the second main word lines, a plurality of the eighth sub-word lines, and a plurality of the eighth selection signal lines which are arranged on the second block. A plurality of eighth sub-row decoding units connected to each other are further included, and the plurality of selection signal generation units are provided corresponding to the first block and connected to the fifth selection signal line, and the first selection signal lines are connected to the fifth selection signal line. Fifth selection signal generation means for generating and outputting a fifth selection signal equivalent to the selection signal, the second selection signal generating means provided corresponding to the first block and connected to the sixth selection signal line.
Selection signal generating means for generating and outputting a sixth selection signal equivalent to the selection signal of No. 3, and the third selection signal generating means provided corresponding to the second block and connected to the seventh selection signal line. Seventh selection signal generation means for generating and outputting a seventh selection signal equivalent to the selection signal and the fourth selection signal provided corresponding to the second block and connected to the eighth selection signal line. An eighth selection signal generation means for generating and outputting an eighth selection signal equivalent to a signal, wherein any one of the plurality of first main word lines has the first main word line. When activated, the first and second sub-row decoding means and the fifth and sixth sub-row decoding means corresponding thereto activate the first and second sub-word lines and the fifth and sixth sub-word lines. The sub-word lines can be activated at the same time. In the first block, which of the fifth and fifth sub-word lines and the second and sixth sub-word lines is activated is activated in the first block. When the second main word line of any one of the plurality of second main word lines is selected by the fifth and sixth selection signals, the corresponding third and fourth main word lines are activated. The sub-row decoding means and the third and fourth sub-decoding means
Of the third and seventh sub-word lines and the fourth and eighth sub-word lines, the sub-word line and the seventh and eighth sub-word lines can be simultaneously activated. In the second block, the third and fourth selection signals and the seventh and eighth groups are activated.
The selection signal is selected.

A dynamic semiconductor memory device according to an eighth invention is the dynamic semiconductor memory device according to the seventh invention, wherein the first to fourth selection signal generating means are:
The fifth to eighth selection signal generating means, which are arranged on the side of the third side of each of the first and second blocks, include the fourth to fourth selection signal generating means of each of the first and second blocks. It is characterized in that it is arranged on the side of the side.

A dynamic semiconductor memory device according to a ninth invention is the dynamic semiconductor memory device according to the seventh invention, wherein the plurality of selection signal generating means are provided on the third side of each of the plurality of blocks. It is characterized in that it is arranged on the side.

A dynamic semiconductor memory device according to a tenth invention is the dynamic semiconductor memory device according to the first invention, wherein a plurality of the sub word lines are a plurality of the first word lines.
A plurality of fifth sub-word lines and a plurality of sixth sub-word lines provided corresponding to the main word lines of the above, and a plurality of seventh sub-words provided corresponding to the second main word lines. A plurality of fifth selection signal lines and a plurality of sixth selection signal lines, which further include a word line and a plurality of eighth sub-word lines, and wherein the plurality of selection signal lines are arranged in the first block , And a plurality of seventh selection signal lines and a plurality of eighth selection signal lines arranged in the second block, wherein the plurality of sub-row decoding means are arranged on the first block. A plurality of fifth sub-row decoding means connected to the plurality of first main word lines, the plurality of fifth sub-word lines and the plurality of fifth selection signal lines, and the first block A plurality of the first main word lines, a plurality of the sixth sub-word lines, and a plurality of the first main word lines arranged above. A plurality of sixth sub-row decoding means connected to the selection signal line, a plurality of the second main word lines and a plurality of the seventh sub-row word lines arranged on the second block, A plurality of seventh sub-row decoding means connected to the seventh selection signal line and a plurality of the second main word lines and a plurality of the eighth sub-words arranged on the second block. A line and a plurality of eighth sub-row decoding means connected to the plurality of eighth selection signal lines,
A plurality of selection signal generating means are provided corresponding to the first block and connected to the fifth selection signal line,
Selecting signal generating means for generating and outputting the selecting signal, and a fifth selecting signal generating means provided corresponding to the first block and connected to the sixth selecting signal line for generating and outputting a sixth selecting signal. 6 selection signal generating means, 7th selection signal generating means which is provided corresponding to the 2nd block, is connected to the 7th selection signal line, and generates and outputs a 7th selection signal, and the 2nd selection signal generating means. Of the plurality of first main word lines, which further includes an eighth selection signal generation unit which is provided corresponding to the block of FIG. 1 and is connected to the eighth selection signal line to generate and output an eighth selection signal. When any one of the first main word lines is activated, the first and second sub-row decoding means and the fifth and sixth sub-row decoding means corresponding thereto activate the first and second sub-row decoding means. The second sub-word line and the fifth and sixth sub-lines In the first block, which of the first, second, fifth and sixth sub-word lines is to be activated is the first line. And a second selection signal and the fifth and sixth selection signals, and when one of the plurality of second main word lines is activated, the second main word line is activated. The corresponding third and fourth sub-row decoding means and the corresponding seventh and eighth sub-decoding means simultaneously activate the third and fourth sub-word lines and the seventh and eighth sub-word lines. In the second block, which of the third, fourth, seventh and eighth sub-word lines is to be activated is set in the possible state. Selecting with the seventh and eighth selection signals And butterflies.

The dynamic semiconductor memory device according to an eleventh aspect of the present invention is the dynamic semiconductor memory device according to the tenth aspect of the present invention, wherein the first to fourth selection signal generating means are provided in the first and second blocks. Each said third
And the fifth to eighth selection signal generating means are arranged on the side of the fourth side of each of the first and second blocks.

According to a twelfth aspect of the present invention, a dynamic semiconductor memory device is provided with a plurality of memory elements arranged in a plurality of rows and a plurality of columns for dynamically storing information by accumulating charges, and a plurality of the memory elements. A main word line provided with either a first voltage for not making a selection of a set of rows or a second voltage higher than the first voltage for making a selection; and the first voltage. A first signal line for transmitting a binary first sub-decode signal having a third voltage lower than the second voltage, and a first signal line having a complementary logical value with respect to the first sub-decode signal. A second signal line for transmitting two sub-decode signals, and for selecting a predetermined row in the set of rows according to the activation state of the main word line and the first and second sub-decode signals. Sub word line of
A P-channel first MOS transistor having one current electrode connected to the main word line, a control electrode connected to the second signal line, and another current electrode connected to the sub word line; An N-channel second MOS transistor having one current electrode connected to a word line, a control electrode connected to the first signal line, and another current electrode connected to the sub word line, and the sub word line An N-channel third MOS transistor having one current electrode connected to the second current line, a control electrode connected to the second signal line, and the other current electrode connected to the first voltage. .

A dynamic semiconductor memory device according to a thirteenth invention is the dynamic semiconductor memory device according to the twelfth invention, wherein the high-level voltage applied to the second signal line is the second voltage or the second voltage. One of the third potentials is selectively determined.

[0032]

The first to fourth selection signal lines in the first aspect of the invention provide the first and second selection signals and the third and fourth selection signals to the first and second blocks, respectively. Therefore, for example, only the sub-row decoding means in one of the first and second blocks can be activated, and the sub-row decoding means of the unnecessary blocks can be driven. Since the selection signal generation means does not have to operate, it is possible to reduce the power consumed by the sub row decoding means in which the first to fourth selection signal generation means are not driven.

Since the selection signal line in the second invention is arranged on the sense amplifier column, it can be wired in parallel with the row of the memory cell array and the wiring distance can be shortened.

Since the first to fourth selection signal generating means in the third invention are arranged on the side of the fourth side where the main decoding means is not arranged, the degree of freedom of layout is large and the manufacturing is easy. It is easy to take various arrangements.

By making the second and third selection signals identical to each other in the fourth invention, the second selection signal line and the third selection signal line among the first to fourth selection signal lines are changed. The second and third selection signal generating means can be made common, and the number of selection signals, the number of selection signal lines, and the number of selection signal generation means can be reduced.

The selection signal generating means in the fifth invention is
Since it is arranged on the side of the third side of the block in which the main row decoding means is arranged, it can be arranged together with the main row decoding means, and the layout area of the semiconductor memory device can be reduced.

Since the first to fourth selection signal lines in the sixth aspect of the invention are arranged on the first and second blocks, the layout is made as compared with the case where these selection signal lines are arranged on other parts. The area can be reduced.

The first to fourth selection signal generating means and the fifth to eighth selection signal generating means in the seventh invention are the first to fourth selection signals for driving the first to fourth selection signals. In addition to the signal generating means, a fifth driving signal for driving fifth to eighth selection signals equivalent to the first to fourth selection signals.
To 8th selection signal generation means are provided, the number of sub-decoding means connected to one selection signal line can be reduced, the load per one selection signal line can be reduced, and the selection signal line can be reduced. It is possible to shorten the rise and fall times of the selection signal for transmitting the.

Since the first to fourth selection signal generating means and the fifth to eighth selection signal generating means in the eighth aspect of the invention are arranged on both sides of the first and second blocks, the first to fourth aspects are provided. The selection signal line and the fifth to eighth selection signal lines can be shortened, and the rising and falling times of the selection signal transmitted through the selection signal line can be shortened.

The selection signal generating means in the ninth invention is
Since they are all arranged on the side of the third side of the block, they can be arranged together with the main row decoding means, and the occupied area can be reduced.

According to the tenth aspect of the invention, the first and eighth selection signals can divide the first and second blocks in the column direction, respectively, and the first to fourth selection signal generating means and the fifth to fifth selection signals can be divided. Since only one of the selection signal generating means 8 operates, the power consumption can be further suppressed.

Since the first to fourth selection signal generating means and the fifth to eighth selection signal generating means in the eleventh invention are arranged on both sides of the first and second blocks, respectively.
The fourth to fifth selection signal lines and the fifth to eighth selection signal lines can be shortened, and the rising and falling times of the selection signal transmitted through the selection signal line can be shortened.

In the third MOS transistor according to the twelfth invention, when the first word line is applied with the first voltage and the first selection signal line is at the third voltage, the third MOS transistor becomes non-conductive and the second voltage is applied. At this time, the MOS transistor becomes conductive and the first voltage is applied to the sub word line. When the second voltage is applied to the main word line and the first selection signal line is at the second voltage, the first MOS transistor becomes conductive and the third MOS transistor becomes non-conductive. Therefore, the same voltage as the main word line is applied to the sub word line,
The sub word line is activated. And the second to the main word line
When the first selection signal line is at the first voltage, the first and second transistors become non-conductive,
Since the third transistor becomes conductive, the sub word line is supplied with the first voltage. The state where the main word line is at the low level can be used as the standby state.

Since the second selection signal line in the thirteenth invention can be selectively applied with either the second voltage or the third voltage lower than the second voltage as the high potential side voltage. By using the third voltage instead of the second voltage when a high voltage is unnecessary, the leak current can be suppressed and the drop in voltage can be mitigated.

[0045]

【Example】

First Embodiment A dynamic semiconductor memory device according to the first embodiment of the present invention will be described below with reference to FIGS. 1 is a block diagram showing an outline of the configuration of a dynamic semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, 1 is a dynamic semiconductor memory device having a memory cell array divided into a plurality of blocks, 2 is a dynamic semiconductor memory device 1 in accordance with a control signal and a clock applied from the outside of the dynamic semiconductor memory device 1. Internal clock used Row-cl
A control clock generation circuit 3 for generating k and Col-clk is provided for each part in the dynamic semiconductor memory device 1 according to the clock Row-clk for the addresses A _{1 to} A _n input from the outside of the dynamic semiconductor memory device 1. An address buffer 4 for distributing the column address among the addresses given from the address buffer 3 in response to the clock Col-clk, and a column decoder 5 for decoding the address given from the multiplexer 4, BL
_{1 to} BL _m are respective blocks constituting the memory cell array, MRD _{1 to} MRD _m are row decoders provided corresponding to the blocks BL _{1 to} BL _m and decoding row addresses received from the address buffer 3, SA ₁ to SA _m is block BL
Each block BL ₁ provided corresponding to _{1 to} BL _m
A sense amplifier row in which a plurality of sense amplifiers for reading information stored in the memory cells of BL _m to BLc according to the block selection address and the clock Row-clk are arranged, and 6 is a block provided from the address buffer 3. A sub-decode signal generation circuit group that outputs individual sub-decode signals SDS _{1 to} SDS _k to the blocks BL _{1 to} BL _m in accordance with the selection address BS and the sub-decode address, and 7 is sense amplifiers SA _{1 to} SA. _This is an I / O control circuit for outputting the signal output from _m to the outside of the dynamic semiconductor memory device 1 according to the clock Col-clk.

Further, in FIG. 1, 8 is a block BL ₁
One of a plurality of memory cells provided inside, MWL
Is a main word line corresponding to a predetermined row set to which the memory cell 9 belongs, SWL is a sub word line corresponding to the row to which the memory cell 9 belongs in the row set, and 9 is a sub-decode signal and a main word line. A decode circuit for deciding whether the sub-word line is active or inactive depending on the state, 10 is a sub-decode band which is a set of decode circuits in the same column as the decode circuit 9 of the decode circuits, and 11 is a decode circuit of the sub-decode band 10. A signal line for transmitting a sub-decode signal, and 12 is a bit line connected to the memory cell 8.

The sub-decode signals SDS _{1 to} SDS _k generated by the sub-decode signal generating circuit group 6 differ depending on how many rows each one main word line serves. For example,
In the case of a 2-way divided decoder system in which one main word line is responsible for two rows of memory cells, two types of subdecode signals are required for each of the blocks BL _{1 to} BL _m , and subdecode for each block is performed. Since the signals are made different, 2 × m kinds of sub-decode signals are required in the entire memory cell array.

The dynamic semiconductor memory device having a structure in which the memory cell array is divided into a plurality of blocks as described above, in order to suppress power consumption, only the selected block among the blocks BL _{1 to} BL _m is activated and the other blocks are activated. since the non-selected block in an inactive state, the block select address BS for selecting an active or inactive block is supplied to the row decoder MRD ₁ ~MRD _m corresponding to each block.

Here, the sub-decode signals SDS ₁ -SDS 2 _m are obtained by, for example, taking the logical product of the block selection address BS and the address that selects an odd row or an even row of the block. To generate.

Next, will be described with reference to FIG. 2 the relationship between the memory cell array and a sub decode signal generating circuits 6 and Shugyo decoder MRD ₁ ~MRD _m and the sense amplifier array. FIG. 2 is a block diagram showing the configuration of the memory cell array and its periphery when a 2-way split decoder system is used in the dynamic semiconductor memory device according to the first embodiment of the present invention. In FIG. 2, SDB1 _{1 to} SDB1 _m are provided corresponding to the blocks BL _{1 to} BL _m , and the subdecode signal generation circuit that configures the subdecode signal generation circuit group 6 shown in FIG. Reference numeral 20 is an AND gate for obtaining the logical product of the address SDA ₁ for the sub-decode signal and the address BS ₁ for the block selection, and 21 is a NOT gate for receiving the output of the AND gate 20 and outputting a signal having the opposite logical value. , 22 are buffers for transmitting the output of the AND gate 20, and 23 is NO
A buffer for transmitting the output of the T gate 21, 24 is an AND gate for taking the logical product of the address SDA ₂ for the sub-decode signal and the address BS ₁ for block selection, and 25 is the output of the AND gate 24 A NOT gate that outputs a signal having an opposite logical value, 26 is a buffer for transmitting the output of the AND gate 24, and 27 is NO
A buffer for transmitting the output of the T gate 25, 31 is arranged in parallel to the row of the block BL ₁ on the sense amplifier column SA ₁ and is output from the sub-decode signal SD of the buffer 22.
A signal line for transmitting S ₁ , 32 is a sense amplifier row S
A signal line for transmitting the sub-decode signal bar SDS ₁ output from the buffer 23, which is arranged parallel to the row of the block BL ₁ on A ₁ , 33 is on the row of the block BL ₁ on the sense amplifier column SA _1. A signal line arranged in parallel for transmitting the sub-decode signal SDS ₂ output from the buffer 26, and a sub-decode signal 34 output from the buffer 27 and arranged in parallel to the row of the block BL ₁ above the sense amplifier column SA _1. Signal line for transmitting the bar SDS ₂ , SD _1-1 ~
SD _1-n is a sub-decode band provided in n columns on the block BL ₁ , and SD _{2-1 to} SD _2-n are sub-decode bands provided in n columns on the block BL ₂ .

Subdecode signal generating circuits SDB1 _{2 to} SDB
The circuit configuration of DB1 _m is the sub-decode signal generation circuit SD
Same as B1 ₁ . These are different in that block selection addresses BS ₁ to BL _{1 of} corresponding blocks BL _{1 to} BL _m are
This is the point at which BS _m is given. The subdecode signals for operating the subdecode circuits of only the blocks selected by the block selecting addresses BS _{1 to} BS _m are the respective subdecode signal generation circuits SDB1 _{1 to} SDB.
Generated in 1 _m .

The conventional dynamic semiconductor memory device is
Since sub-decode signals were simultaneously applied to the sub-decode circuits of all blocks belonging to the sub-decode band of odd-numbered columns or even-numbered columns, many signal lines and decode circuits were driven at once, which resulted in an increase in charge / discharge current. It was On the other hand, in the dynamic semiconductor memory device of the first embodiment, the power consumption can be reduced because the sub-decode signal is charged / discharged for only one block. Further, since the load per drive circuit for giving the sub-decode signal is also dispersed, it is possible to speed up the rise and fall of the sub-decode signal.

Sub-decoding is performed via signal lines 31 and 32 to the odd-numbered sub-decoding bands SD _1-1 , SD _1-3 , SD _2-1 and SD _{2-3 of} each block BL _{1 to} BL _m. Signal SDS
₁ , bar SDS ₁ is given. In addition, for even-numbered sub-decode bands SD _1-2 , SD _1-4 , SD _2-2 , SD _2-4, etc.,
Sub-decode signal SDS ₂ via signal lines 33 and 34,
Bar SDS ₂ is provided.

Further, the arrangement of the sub-decoding circuits arranged in the block will be described. FIG. 3 is a block diagram showing an arrangement of sub-decode circuits in the block BL ₁ in FIG. 3, sub-decoding circuit D1~D6, MWL ₁ ~MWL _i primarily word line, SWL _1a to S
W _3b is a sub word line. Subdecode circuit for controlling the sub-word line SWL _1a is connected to the first row of memory cells in the block, the active or inactive, such as SWL _1b D1, D
3, sub decode signal SDS _1, the bar SDS ₁ receives is connected to the main word line MWL _1. On the other hand, the sub-decode circuit D2 etc. for controlling the activation or inactivation of the sub-words SWL _2a , SWL _2b etc. in the second row in the block are
It is connected to the main word line MWL ₁ and receives the sub-decode signals SDS ₂ and SDS ₂ .

₁ when the main word line MWL ₁ is activated
It is determined whether the sub-word lines SWL _1a , SWL _1b, etc. of the row are activated or the sub-word lines SWL _2a , SWL _2b, etc. of the second row are activated by the odd-numbered sub-decode band SD _1-1. , SD
Sub-decode signals SDS ₁ , SDS ₁ and SDS given to _1-2 etc. and even-numbered sub-decode bands SD _1-2 etc.
₂ , determined by bar SDS ₂ .

As described above, the dynamic semiconductor memory device shown in FIGS. 2 and 3 is similar to the dynamic semiconductor memory device shown in FIG. 16 for the sake of easy description.
Although the main and sub word lines are provided by the alternate way sub-decoding method, the same effect can be obtained even if the number of ways is four or more.

Example 2. Next, a dynamic semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a block diagram for explaining the relationship between each block of the memory cell array of the dynamic semiconductor memory device according to the second embodiment of the present invention and the sub-decode signal. FIG. 5 is a block diagram for explaining the arrangement of sub-decode circuits in the block BL ₁ shown in FIG. The difference between the dynamic semiconductor memory device according to the second embodiment and that of the first embodiment is that each block BL _{1 to} BL _m of the sub-decode signal according to the second embodiment.
To the sub-decode signal according to the first embodiment.

In FIG. 4, SDB10 _{1 to} SDB10 _m
Is a sub-decode signal generation circuit. For example, the sub-decode signal generation circuit SDB10 ₁ includes the main row decoder MRD ₁
Address BS ₁ for block selection, which is located on the upper side of
And an address SDA ₁ for the sub-decode signal, AND gate 40, a buffer 42 for transmitting the output of the AND gate 40 to the block BL ₁ as a sub-decode signal, and an output of the AND gate 40 It is composed of a NOT gate 41 for outputting a logical value and a buffer 43 for transmitting the output of the NOT gate 41 as a sub-decode signal to the block BL ₁ .

Subdecode signal generation circuit SDB10
Reference numeral ₂ denotes an OR gate 44 that takes the logical sum of the block selection addresses BS ₁ and BS _2, an AND gate 45 that takes the logical product of the output of the OR gate 44 and the address SDA ₂ for the subdecode signal, and an AND gate. A buffer 47 for transmitting the output of 45 as a sub-decode signal to the blocks BL ₁ and BL ₂ , a NOT gate 46 for outputting a logical value opposite to the output of the AND gate 45, and an output of the NOT gate 46 Block BL as decode signal
It is composed of a buffer 48 for transmitting to ₁ and BL ₂ .

Subdecode signal generation circuit SDB10
₃ is an OR gate 49 that takes the logical sum of the addresses BS ₂ and BS ₃ for block selection, an AND gate 50 that takes the logical product of the output of the OR gate 49 and the address SDA ₁ for the subdecode signal, and an AND gate A buffer 52 for transmitting the output of 50 as a sub-decode signal to the blocks BL ₂ and BL ₃ , a NOT gate 51 for outputting a logical value opposite to the output of the AND gate 50, and an output of the NOT gate 51 Block BL as decode signal
It is composed of a buffer 53 for transmitting to ₂ and BL ₃ .

In FIG. 5, SDS ₁ and bar SDS ₁ are subdecode signals output by the subdecode signal generation circuit SDB10 ₁ , and SDS ₂ and bar SDS ₂ are subdecode signals output by the subdecode signal generation circuit SDB10 ₂ . The other parts having the same reference numerals as those in FIG. 3 are the parts corresponding to those shown in FIG.

[0062] For example, sub decode signal SDS ₁ from the top side signal lines disposed on the sense amplifier column SA ₁ of the block BL _1, supplies a bar SDS _1, a sense amplifier array of the lower side of the block BL ₁ SA ₂ The sub-decode signal SDS ₂ and bar SDA ₂ are supplied from the signal line arranged above.
By supplying the sub-decode signal in this manner, the sub-decode signal SDS ₂ and the bar SDS ₂ can also be supplied to the block BL ₂ , and the sub-decode signal running in the bit line direction can be supplied to the adjacent blocks BL ₁ and BL _2. It is possible to have a shared configuration.

Therefore, the same sub-decode signal SDS ₂ ,
Sub decode bands SD _12-1 , S to which the bar SDS ₂ is supplied
D _{12-2 and the} like will span the block BL ₁ and the block BL ₂ .

For example, when a memory cell in the block BL ₂ is selected, the sub-decode signal generating circuits SDB 10 ₂ and SDB 10 ₂ and 103 generate the sub-decode signal SDS ₂ , bars SDS ₂ and SDS ₃ , bar by the block selection address BS ₂ . Enable SDS ₃ output.

As a result, the number of signal lines for transmitting the sub-decode signal running on the sense amplifier row can be halved. Other effects are the same as those of the dynamic semiconductor memory device shown in the first embodiment. In the second embodiment, the two-way configuration has been described, but even if the number of ways is four or more, sharing between adjacent blocks is possible.

Example 3. A dynamic semiconductor memory device according to the third embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram for explaining the positional relationship between the memory cell array and its peripheral circuits of the dynamic semiconductor memory device according to the third embodiment of the invention. In FIG. 6, the same reference numerals as those in FIG. 2 are portions corresponding to the same reference numerals in FIG. As shown in FIG. 2, a dynamic type semiconductor memory device according to the first embodiment, the area or between the main row decoders and sense a sub decode signal generating circuit SDB1 ₁ ~SDB1 _m main row decoder MRD ₁ ~MRD _m are arranged Area adjacent to the amplifier row,
That is, they are arranged on the left side of the blocks BL _{1 to} BL _m .

In the dynamic semiconductor memory device according to the third embodiment, the main row decoder M is sandwiched across the memory cell array.
RD ₁ ~MRD _m In the side opposite to the area where is formed a peripheral circuit band side of the peripheral circuit is formed, that is located on the right side side of the block BL ₁ to BL _m of the memory cell array.
When the SA control circuit or the like is originally arranged on the left side of the memory cell array in which the main row decoder is arranged, and it is difficult to secure a place for arranging the sub-decode signal generation circuits SDB1 _{1 to} SDB1 _m There is. Only the arrangement of the subdecode signal generation circuits SDB1 _{1 to} SDB1 _m is changed, and the effect of using the dynamic semiconductor memory device according to the third embodiment is similar to that of the first embodiment.

Example 4. A dynamic semiconductor memory device according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a block diagram for explaining the positional relationship between the memory cell array of the dynamic semiconductor memory device according to the fourth embodiment of the present invention and its peripheral circuits. In FIG. 7, reference numeral 60 denotes a bus for transmitting a sub-decode signal, and those having the same reference numerals as those in FIG. 2 are portions corresponding to those having the same reference numerals in FIG. The bus 60 is composed of a plurality of signal lines.

In the dynamic semiconductor memory device according to the first embodiment, the signal line for transmitting the sub-decode signal is arranged on the sense amplifier rows SA _{1 to} SA _m . By using the main and sub word lines rather than the divided decoder system,
Since the pitch of the first metal wiring used as the wiring of the main word line is relaxed, the bus 6 for transmitting the sub-decode signal is formed.
The signal line forming 0 can be arranged on each block BL _{1 to} BL _m of the memory cell array, that is, between the main word lines. For example, one signal line may be arranged between one main word line. Further, the position between the main word lines for arranging this signal line does not have to be at the end of the block, and may be in the middle. From this, the sense amplifier rows SA _{1 to} SA _m
It is not necessary to additionally run a signal line above, and an increase in the width of the sense amplifier rows SA _{1 to} SA _m can be suppressed. Only the arrangement of the signal lines for transmitting the sub-decode signal is changed, and other effects of using the dynamic semiconductor memory device according to the fourth embodiment are similar to those of the first embodiment.

As shown in FIG. 8, the sub-decode signal generation circuit SDB1 ₁ is similar to the relationship between the dynamic semiconductor memory device according to the first embodiment and that of the third embodiment.
~ SDB1 _m to the peripheral circuit band side, that is, blocks BL _{1 to} B
It may be arranged on the right side of L _m . The restriction on the arrangement of the signal line for transmitting the sub-decode signal and the sub-decode signal generation circuit is eliminated, and the degree of freedom in layout is increased, and the control circuit for other control circuits such as the sense amplifier control circuit is increased as in the third embodiment. Optimization can be achieved for placement.

Example 5. A dynamic semiconductor memory device according to the fifth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a block diagram for explaining the relationship between the memory cell array of the dynamic semiconductor memory device of the present invention and the circuits around it. In FIG. 9, S
DB2 _{1 to} SDB2 _m are provided corresponding to the blocks BL _{1 to} BL _m , and the subdecode signal generation circuits SDB1 _{1 to} SDB are provided.
A sub-decode signal generation circuit having a configuration similar to 1 _m ,
70 and 71 are sub-decode signal generation circuits SDB
1 ₁ and SDB2 ₁ are buses for transmitting the sub-decode signals output, and other parts having the same reference numerals as those in FIG.
The part corresponding to the part of the same reference numeral is shown.

When the number of memory cells per row of the memory cell array increases and the main word line becomes longer, the signal line for transmitting the sub-decode signal also has substantially the same length as the main word line. In some cases, the load on the signal line becomes too heavy and the rise and fall of the sub-decode signal becomes slow.

In that case, the main word line is the block BL.
_The widths of _{1 to} BL _m are made equal to each other, and the buses 70 and 71 for transmitting sub-decode signals are divided at the center, and sub-decode signal generation circuits SDB1 _{1 to} SDB1 _m and SDB2 ₁ having the same configuration are formed.
˜SDB2 _m are arranged on both left and right sides of the blocks BL _{1 to} BL _m to drive the buses 70, 71.

As a result, the wiring and gate load driven by one subdecode signal generation circuit can be halved, and the rise and fall of the subdecode signal can be accelerated. Further, the present invention can be applied to a case where the sub-decode signal generation circuit is shared by adjacent blocks such as the dynamic semiconductor memory device according to the second embodiment, and the same effect as the above embodiment can be obtained.

Although the signal line for transmitting the sub-decode signal is divided in the fifth embodiment as shown in FIG. 10, the sub-decode signal may be supplied from one side to distribute only the gate load. . In FIG. 10, SDB31
-SDB3m are sub-decode signal generation circuits SDB1 ₁ shown in FIG. 9 corresponding to the blocks BL ₁ -BL _m , respectively.
～SDB1 _m and sub decode signal generating circuit SDB2 ₁ to S
A sub-decode signal generation circuit combining DB2 _m , 72,
Reference numeral 73 is a bus for transmitting sub-decode signals corresponding to the buses 70 and 71 shown in FIG. 9, respectively. In this case, the number of signal lines for subdecode signals wired in each of the sense amplifier columns SA _{1 to} SA _m increases, but the number of subdecode circuits is reduced and the load of the buffer for transmitting the subdecode signals is reduced. The speed can be increased by the amount of distribution. Here, the sub-decode signal generation circuit is arranged in the region where the main row decoder on the left side of the blocks BL _{1 to} BL _m is provided, but it may be arranged on the right side of the blocks BL _{1 to} BL _m .

Example 6. Next, a dynamic semiconductor memory device according to a sixth embodiment of the present invention will be described with reference to FIG. FIG. 11 is a block diagram showing the relationship between the memory cell array of the dynamic semiconductor memory device according to the sixth embodiment of the present invention and its peripheral circuits. In FIG. 11, SDA _{3 to} SDA ₆ are addresses for sub-decode signals, and those having the same reference numerals as those in FIG. 9 are portions corresponding to the portions having the same reference numerals in FIG. 9.

For example, the sub-decode signal generation circuit SDB
1 to _1, although the sub-decoding addresses SDA _3, SDA ₄ and the block selecting address BS ₁ is given, subdecode address SDA ₅ to the sub decode signal generating circuit SDB2 _1, SDA ₆ and the block select address BS ₁
Is given.

Subdecode signal generation circuit SD having the same configuration
By inserting different signals into B1 ₁ and SDB2 ₁ , only the necessary sub-decode signal generation circuits are operated. Other sub-decode signal generation circuits SDB12 to SDB1m, SDB2
The same applies to 2 to SDB2m. With this configuration, even sub-decoding circuits belonging to the same row can complementarily control activation and deactivation depending on which side of the blocks, the left or right side. Therefore, the sub-decode signal generation circuits SDB arranged on both sides
By selectively using 11 and SDB21, the charge / discharge load of the sub-decode signal can be dispersed, and the power consumption and speed can be reduced. It is also possible to arrange the sub-decode signal generation circuit on one side as shown in FIG.
Further, the present invention can be applied to the case where the sub-decode signal generating circuit is shared by adjacent blocks such as the dynamic semiconductor memory device according to the second embodiment, and the same effect can be obtained.

Next, the sub-decoding addresses SDA3 ...
The SDA6 will be described. For example, it is assumed that the upper bit of the row address is a bit that selects a memory cell on either side from the center of the blocks BL1 to BLm, that is, a memory cell in a region shared by the signal lines 72 and 73. The sub-decoding address SD is obtained by taking the logical product of the upper bits of the row address and the sub-decoding addresses SDA1 and SDA2 used in the fifth embodiment.
A3 and SDA4 can be generated. Similarly, the logical value opposite to the upper bit of the row address is logically ANDed with, for example, the sub-decoding addresses SDA1 and SDA2 used in the fifth embodiment to obtain the sub-decoding address SD.
A5 and SDA6 can be generated.

Example 7. Next, a dynamic semiconductor memory device according to a seventh embodiment of the present invention will be described with reference to FIGS. FIG. 12 is a block diagram showing the structure of a subdecode circuit of a dynamic semiconductor memory device according to the seventh embodiment of the present invention. In FIG.
Q5 is a PMO having a control electrode to which the sub-decode signal bar SDS is applied, one current electrode connected to the main word line MWL, and the other current electrode connected to the sub word line SWL.
An S transistor, Q6 is an NMOS transistor having a control electrode to which a sub-decode signal SDS is applied and one current electrode connected to the main word line MWL and the other current electrode connected to the sub word line SWL, and Q7 is a sub word line SWL.
One-side current electrode and sub-decode signal bar SD connected to
It is an NMOS transistor having a control electrode to which S is applied and another current electrode connected to a power source to supply the ground potential gnd.

At the time of standby (when the row address strobe signal bar RAS is at a high level), the sub-decode circuit belongs to the block selected during the operation, and the sub-decode circuit belongs to the block not selected during the operation. Table 2 shows the states of the main word line and the sub-decode signals SDS and SDS at the same time.

[0082]

[Table 2]

Next, the operation of this circuit will be described with reference to FIG. For example, here block B shown in FIG.
It is assumed that L2 is selected. The block selection address BS2 corresponding to the block BL2 changes from the low level to the high level in the operating state. At this time,
The voltage level of the selected main word line MWL changes from gnd to V _P P. The other voltage levels of the main word line MWL remain gnd. Also, block BL2
The sub-decode signal supplied to SDS1,
Assume that there are bars SDS1, SDS2, and bar SDS2. Then, in the operating state, given a voltage V _C C as a sub decode signal SDS1 to activate predetermined sub-decoding circuit, a voltage gnd given as a sub decode signal bar SDS1, other sub-decoding circuit inactive Therefore, the voltage V _P P is applied as the sub-decode signal SDS2, and the voltage V _C C is applied as the sub-decode signal SDS2.

In the standby state, the sub-decode circuits belonging to the non-selected block and the sub-decode circuits which are inactivated by the sub-decode signal in spite of the main word line of the selected block being inactive, the same signal is supplied. Given, that is, the main word line MWL of the sub-decode circuit
Voltage gnd in the voltage gnd as a sub decode signal SDS is, the voltage V _P P as a sub decode signal bars SDS
Is given. At this time, in the sub-decoding circuit shown in FIG. 12, the transistors Q5 and Q6 are turned off,
The transistor Q7 becomes conductive. At this time, the voltage gnd is applied to the sub word line SWL through the transistor Q7.

The operation when main word line MWL to which the sub-decode circuit is connected is activated and voltage V _P P is applied will be described. The sub-decoding circuit sub-word line connected is activated, the voltage V _C C as a sub decode signal SDS, sub decode signal bars SD
The voltage gnd is applied as S. At this time, the transistors Q5 and Q6 are rendered conductive, and the transistor Q7 is rendered non-conductive. Therefore, the voltage V is applied from the main word line MWL to the sub word line SWL through the transistors Q5 and Q6.
_P P is supplied. On the other hand, the sub-decoding circuit sub-word line connected is not activated, the voltage gnd as a sub decode signal SDS is, the voltage V _P P given as a sub decode signal. At this time, the transistors Q5 and Q6
Is turned off and the transistor Q7 is turned on, so that the voltage gnd is supplied to the sub word line SWL through the transistor Q7.

When the sub-decode signal is a signal for activating the sub-word line even though the main word line MWL connected to the sub-decode circuit is inactive, that is, the main word line MWL is not When the voltage gnd is applied, the voltage V _CC is applied as the sub-decode signal SDS, and the voltage gnd is applied as the sub-decode signal SDS, the transistor Q6 is turned on and the transistor Q7 is turned off. The voltage gnd is applied from the word line MWL to the sub word line SWL through the transistor Q6.
Is given.

By using the sub-decode circuit having the structure as shown in FIG. 12, the main word line MWL, which is wired more than the signal lines wired for transmitting the sub-decode signal in the memory cell array, is on standby. Since the voltage gnd is applied as the voltage at the time, the power consumption due to the leak current can be reduced as compared with the conventional dynamic semiconductor memory device in which the voltage V _P P is applied to the main word line, and the malfunction due to the decrease in the voltage level can be prevented. Can be prevented.

Example 8. Next, a dynamic semiconductor memory device according to an eighth embodiment of the present invention will be described with reference to FIGS. 14 and 15. FIG. 14 is a circuit diagram showing a structure of a circuit for converting a sub-decode signal of the dynamic semiconductor memory device according to the eighth embodiment of the present invention. 14
, 80 is a NOT gate that outputs a signal having a logic value opposite to that of the block selection address BS, and 81 is NO.
Output of T gate 80 and subdecode signal S shown in Table 2
OR gate ORing the sub decode signal SDE corresponding to DS, Q8 has a source applied voltage V _P P O
P having a gate and a drain for receiving the output of the R gate 81
A MOS transistor 82 is an AND gate that takes the logical product of the sub-decode signal SDE and the block selection address BS. Q9 is connected to the source to which the voltage VCC is applied, the gate to which the block selection address BS is applied, and the drain of the transistor Q8. PMOS with open drain
The transistor Q10 is an NMOS transistor having a drain connected to the drain of the transistor Q8, a gate connected to the output of the AND gate 82, and a source to which the ground voltage gnd is applied. The sub-decode signal bar SDS is output from the drain of the transistor Q8.
Here, the block selection address BS and the sub-decode circuit activation signal SDE become high level when selected. All the logic gates shown in FIG. 14 are driven by the voltage V _P P.

FIG. 15 is a timing chart showing the state of the sub-decode signal. In the standby mode (when the row address strobe signal RAS is at a high level), when the sub-decode circuit belongs to the block selected in the operation, and when the sub-decode circuit belongs to the block not selected in the operation. Table 3 shows the states of the main word line, sub-decode signal SDS, and bar SDS.

[0090]

[Table 3]

In FIG. 15, the sub-decode signal SDS is used.
It is assumed that 1 and SDS1 are signals which belong to the selected block and are supplied to the sub-decoding circuit connected to the sub-word line to be activated. In the operating state, the subdecode circuit activation signal SDE is at high level,
The block selection address BS becomes high level, as shown in FIG.
In the sub-decode signal conversion circuit shown in FIG. 4, only the transistor Q10 is rendered conductive, so that the voltage gnd is output as the sub-decode signal bar SDS1.

It is assumed that the subdecode signals SDS2 and SDS2 are signals provided to the subdecode circuits connected to the subword line which belongs to the selected block but should be inactive. In the operating state, the sub-decode circuit activation signal SDE is at the low level, the block selecting address BS is at the high level, only the transistor Q8 is in the conductive state, and the voltage V _P P is the sub-decode signal bar SDS.
Output as 2. At this time, the sub-decode signal bar S
If the voltage V _CC is output as DS2, the transistor Q5 becomes conductive and malfunctions.

It is assumed that the subdecode signals SDS3 and SDS3 are signals applied to the subdecode circuits belonging to the non-selected block. It is the same as the signal given to the sub-decode circuit in the standby mode. In the operating state, the block selection address BS becomes low level,
Only the transistor Q9 becomes conductive, and the voltage V _C C is output as the sub-decode signal bar SDS.

By configuring as described above, the seventh
Compared with the dynamic semiconductor memory device according to the embodiment, the eighth embodiment requires only that the voltage of the signal line at the time of standby is kept at a low voltage V _C C, so that the level of the voltage V _P P is prevented from being lowered at the time of standby. In addition, the effect of suppressing the power consumption is increased. Here, since the sub-decode signal is converted according to the block selection address BS, the voltage V _CC is applied as the sub-decode signal bar SDS except for a specific block to suppress the power consumption, but the power consumption is somewhat reduced. There is an increase in
It may be controlled by using the row address strobe signal bar RAS that controls whether the standby state or not.

[0095]

As described above, according to the dynamic semiconductor memory device of the first aspect of the invention, any one of the plurality of first main word lines is activated. Then, the first and second sub-row decoding circuits corresponding to the first and second sub-word lines can be simultaneously activated, but either the first or second sub-word line can be activated. Whether to activate is selected by the first and second selection signals in the first block, and when any one of the plurality of second main word lines is activated. Although the third and fourth sub-row decoding means corresponding thereto can simultaneously activate the third and fourth sub-word lines, whichever of the third or fourth sub-word lines is activated. In the second block, the third and fourth Since the selection is performed by the selection signal, only the first to fourth selection signal lines and the first to fourth sub-decoding means related to the block in which the main word line is selected are charged and discharged. Therefore, there is an effect that the word line can be started up at high speed with low consumption.

According to the dynamic semiconductor memory device of the second aspect of the invention, since the plurality of selection signal lines are arranged on the plurality of sense amplifier columns, the wiring distance can be shortened and the consumption can be reduced. There is an effect that the word line can be raised at high speed.

According to the dynamic semiconductor memory device of the third aspect of the present invention, since the plurality of selection signal generating means are arranged on the side of the third side of the plurality of blocks, the selection signal means. This has the effect of increasing the degree of freedom in layout and facilitating manufacturing.

According to the dynamic semiconductor memory device of the present invention, since the second selection signal and the fourth selection signal are the same, the number of selection signals and the number of selection signal lines are set. There is an effect that the device can be simplified by reducing the above.

According to another aspect of the dynamic semiconductor memory device of the present invention, since the plurality of selection signal generating means are arranged on the fourth side of the plurality of blocks, the semiconductor memory is formed. The layout area of the device can be reduced, and the dynamic semiconductor memory device can be easily downsized.

According to the dynamic semiconductor memory device of the sixth aspect of the invention, since the plurality of selection signal lines are arranged on the plurality of blocks, the layout area can be reduced and the device can be easily miniaturized. There is an effect that.

According to another aspect of the dynamic semiconductor memory device of the present invention, when any one of the plurality of first main word lines is activated, the first main word line is activated. 1st and 2nd sub-row decoding means and 5th
The first and second sub-word lines and the fifth and sixth sub-word lines can be activated simultaneously by the sixth and sixth sub-row decoding means. In the first block, which of the second and sixth sub-word lines is to be activated is selected by the first and second selection signals and the fifth and sixth selection signals, and a plurality of groups are selected. When any one of the second main word lines is activated, the corresponding third and fourth main word lines are activated.
The third and fourth sub-word lines and the seventh and eighth sub-word lines can be simultaneously activated by the sub-row decoding means and the seventh and eighth sub-decoding means. In the second block, the third and fourth selection signals and the seventh and eighth selection signals are used to determine which of the seventh sub-word line and the fourth and eighth sub-word lines is activated. Since it is configured to select by signal,
The number of sub-decoding units driven by the selection signal generation unit can be reduced, the rise and fall times of the selection signal transmitted through the selection signal line can be shortened, and the operation of the device can be speeded up.

According to another aspect of the dynamic semiconductor memory device of the present invention, the first to fourth selection signal generating means and the fifth to eighth selection signal generating means are of the first and second blocks. Since the third and fourth sides are arranged separately, the lengths of the first to eighth selection signal lines can be shortened, and the selection signal rising on the selection signal line rises. Further, there is an effect that the fall time can be shortened and the operation of the device can be speeded up.

According to another aspect of the dynamic semiconductor memory device of the present invention, since the plurality of selection signal generating means are arranged on the side of the third side of each of the plurality of blocks, the occupied area is reduced. Therefore, there is an effect that the device can be easily downsized.

According to the dynamic semiconductor memory device of the tenth aspect of the present invention, when any one of the plurality of first main word lines is activated, the corresponding first main word line is activated. By the first and second sub-row decoding means and the fifth and sixth sub-row decoding means, the first and second sub-word lines and the fifth and sixth sub-word lines can be simultaneously activated. Which of the first, second, fifth, and sixth sub-word lines is activated in the first block is determined by the first and second selection signals and the fifth and sixth selection signals. When the second main word line of any one of the plurality of second main word lines is selected and activated, the third and fourth sub-row decoding means and the seventh and eighth sub row decoding means corresponding thereto are selected. Third and fourth sub-word lines by the sub-decoding means Although sub-word lines of the seventh and eighth is activatable at the same time each time, third, fourth, or to activate any of the seventh and eighth sub-word line and the second
In this block, the selection is made by the third and fourth selection signals and the seventh and eighth selection signals, so that the main word line is selected and the first to fourth selection signals are selected. Generating means or fifth to eighth
It is possible to reduce power consumption by operating only one of the selection signal generating means.

According to another aspect of the dynamic semiconductor memory device of the present invention, the first to fourth selection signal generating means are the third and third blocks of the first and second blocks, respectively.
, And the fifth to eighth selection signal generating means are arranged on the fourth side of each of the first and second blocks, so that the first to eighth selection signals are generated. There is an effect that the length of the signal line can be shortened, the rise and fall times of the selection signal transmitted through the selection signal line can be shortened, and the operation of the device can be speeded up.

According to another aspect of the dynamic semiconductor memory device of the present invention, one current electrode connected to the main word line, the control electrode connected to the second selection signal line and the sub word line are connected. The P-channel first MOS transistor having the other current electrode, the one current electrode connected to the main word line, the control electrode connected to the first selection signal line, and the other current electrode connected to the sub word line. An N channel having an N channel second MOS transistor, a current electrode connected to the sub word line, a control electrode connected to the second selection signal line, and the other current electrode connected to the first voltage And a third MOS transistor of No. 3, the main word line is at a low level can be used as a standby state, and power consumption during standby is reduced. There is an effect that it is Rukoto.

According to the dynamic semiconductor memory device of the thirteenth aspect, the high-level side voltage applied to the second selection signal line is selectively either the second voltage or the third potential. Therefore, there is an effect that the voltage on the high potential side can be suppressed to a low level as necessary, and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a configuration of a dynamic semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an arrangement of circuits around a memory cell array of the dynamic semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing an arrangement of sub-decode circuits in the memory cell array according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing an arrangement of circuits around a memory cell array of a dynamic semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing an arrangement of sub-decode circuits in a memory cell array according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing an arrangement of circuits around a memory cell array of a dynamic semiconductor memory device according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing an example of an arrangement of circuits around a memory cell array of a dynamic semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram showing another example of arrangement of circuits around a memory cell array of a dynamic semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram showing an example of an arrangement of circuits around a memory cell array of a dynamic semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 10 is a block diagram showing another example of the arrangement of circuits around the memory cell array of the dynamic semiconductor memory device according to the fifth embodiment of the present invention.

FIG. 11 is a block diagram showing an arrangement of circuits around a memory cell array of a dynamic semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a structure of a sub-decoding circuit of a dynamic semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 13 is a timing chart showing an operation of the dynamic semiconductor memory device according to the seventh embodiment of the present invention.

FIG. 14 is a circuit diagram showing a configuration of a subdecode signal conversion circuit of a dynamic semiconductor memory device according to an eighth embodiment of the present invention.

FIG. 15 is a timing chart showing an operation of the dynamic semiconductor memory device according to the eighth embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration expected when a division decoder system is applied to a dynamic semiconductor memory device in which a conventional memory cell array is divided into a plurality of blocks.

17 is a block diagram showing an arrangement of sub-decode circuits in the memory cell array of the dynamic semiconductor memory device shown in FIG.

FIG. 18 is a circuit diagram showing a configuration of a conventional sub-decoding circuit.

[Explanation of symbols]

1 dynamic semiconductor memory device, 2 control clock generation circuit, 3 address buffer, 4 multiplexer, 5 column decoder, 6 sub-decode signal generation circuit group, BL1 to BLm block, SA1 to SAm sense amplifier column, MRD1 to MRDm main row decoder , SDB11
-SDB1m sub-decode signal generation circuit.

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[Procedure amendment]

[Submission date] November 1, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 7

[Correction method] Change

[Correction content]

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 10

[Correction method] Change

[Correction content]

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 13

[Correction method] Change

[Correction content]

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

[0008] Figure 17 is a block diagram showing an arrangement of a sub-decoder circuit block of a plurality of blocks shown in FIG. 16. In FIG. 17, MWL _{1 to} MWL _m are first to mth main word lines, and SWL _{1a to} SWL _1b are connected to some of the plurality of memory cells in the first row of the block BL ₁ . Word line, SWL _{2a to} SWL _2b
Is a sub-word line connected to some of the plurality of memory cells in the second row of the block BL ₁ , D101 is connected to the main word line MWL ₁ and the sub-word line SWL _1a , and the _first word of the block BL ₁ is A sub-decode circuit belonging to the sub-decode band in the first column, D102, is connected to the main word line MWL ₁ and the sub word line SWL _2a, and is connected to the block B.
A sub-decode circuit belonging to the sub-decode band of the second column of L ₁ , D103 is a main word line MWL ₁ and a sub word line SW
A sub-decoding circuit connected to L _1b and belonging to the sub-decoding band in the third column of the block BL ₁ , D104
Be a sub-decoding circuits belonging to the main word line MWL ₂ and the first row of sub-decode band blocks BL ₁ is connected to the sub word line corresponding to some of the third row of the memory cell blocks BL ₁ The same reference numerals as those in FIG. 16 are the same portions as those shown in FIG.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

The main word lines MWL _{1 to} MWL _m are arranged in parallel with the sub word lines, that is, the transfer gates in the memory cells, and the sub word lines are n−1 in the main word line direction with respect to the main word line length. Is divided into Sub-decode bands 101 to 104 and the like are arranged at the divided boundary portion. Main word lines MWL _{1 to} MW on this sub-decode band
Sub-decode signal SDA ₁ , bar S so that it is orthogonal to L _m
Signal line 201 for transmitting DA ₁ , SDA ₂ , and bar SDA ₂
~ 204 etc. are arranged. A sub-decode circuit (hereinafter referred to as SRD) is provided at the intersection of the main word line and the sub-decode signal.
To place. The detailed structure of the SRD is shown in FIG. In FIG. 18, Q1 is a P-channel MOS transistor having one current electrode to which the sub-decode signal SDS is applied, the other current electrode connected to the sub word line SWL, and a control electrode connected to the main word line, and Q2 is the sub word line. An N-channel MOS transistor having one current electrode connected to SWL, a control electrode connected to main word line MWL, and the other current electrode grounded, Q3 is a sub word line SW
One current electrode connected to L, sub-decode signal bar S
It is an N-channel MOS transistor having a control electrode to which DS is applied and the other current electrode which is grounded. Table 1 shows the operation of the sub-decode circuit. In Table 1, V _PP is a voltage higher than the voltage V _CC and gnd is a ground voltage.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

When the main word line MWL is activated, the ground voltage gnd is applied to the main word line, and the sub-decode signal SDS is applied to one current electrode of the transistor Q1 to further activate the sub-word line. The voltage V _PP is applied. Therefore, the transistor Q1 is turned on, and the voltage V _PP is applied to the sub word line SWL. Since the high voltage V _PP is applied as the sub-decode signal SDS when activated, the power consumption of the buffer Bu ₁₀₁ or Bu ₁₀₃ that outputs the sub-decode signal SDS is as high as the buffer that outputs the voltage V _CC as the sub-decode signal SDS when inactive. It is larger than Bu ₁₀₂ or Bu ₁₀₄ .

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

[0019]

A dynamic semiconductor memory device according to a first invention is divided into a plurality of blocks including at least first and second blocks, and arranged in a plurality of rows and a plurality of columns. A plurality of memory elements for dynamically storing information by accumulating charges and a plurality of main word lines provided in each of the plurality of blocks and arranged in parallel with each other for selecting the memory elements. And a plurality of sub-word lines, and each of the plurality of blocks is formed to have first and second sides parallel to the row and third and fourth sides parallel to the column. Memory cell array, and a plurality of sense amplifier columns provided corresponding to each of the plurality of blocks and arranged to face the first side or the second side of the corresponding block. , For selectively activating the plurality of main word lines in the corresponding block, which is provided corresponding to each of the plurality of blocks and is arranged on the side of the third side of the corresponding block. A plurality of main row decoding means, a plurality of sub row decoding means connected to the plurality of main word lines and a plurality of sub word lines and provided on the memory cell array, and a plurality of sub row decoding means. A plurality of selection signal lines for transmitting selection signals for activating the connected sub-row decoding means, and a plurality of selection signal lines connected to the plurality of selection signal lines for generating the selection signals. Selection signal generating means, and the plurality of main word lines include at least a plurality of first main word lines arranged in the first block and a plurality of first main word lines arranged in the second block. Two A plurality of first sub-word lines and a plurality of second sub-word lines provided corresponding to at least the plurality of first main word lines. , And a plurality of third sub-word lines and a plurality of fourth sub-word lines provided corresponding to the second main word line, the plurality of selection signal lines being at least the first sub-word line. A plurality of first selection signal lines and a plurality of second selection signal lines arranged in the block, and a plurality of third selection signal lines and a plurality of fourth selection signals arranged in the second block A plurality of sub-row decoding means including at least a signal line and arranged on at least the first block, the plurality of first main word lines, the plurality of first sub-word lines, and the plurality of first sub-word lines. A plurality of first sub-row decoding means connected to one selection signal line, the first block A plurality of second sub-row decoding means arranged above and connected to the plurality of first main word lines, the plurality of second sub-word lines and the plurality of second selection signal lines; A plurality of third sub-row decodes arranged on two blocks and connected to the plurality of second main word lines, the plurality of third sub-row word lines and the plurality of third selection signal lines. Means and a plurality of fourth main word lines, a plurality of fourth main word lines, a plurality of fourth sub word lines, and a plurality of fourth selection signal lines connected to the plurality of fourth main word lines. A plurality of selection signal generating means, each of which includes a sub-row decoding means, is connected to the plurality of first selection signal lines provided at least corresponding to the first block, and generates a first selection signal. first selection signal generating means for outputting, provided corresponding to said first block Multiple provided corresponding to the second is connected to the selection signal line and the second selection signal generating means for generating and outputting a second selection signal, the second block number
The third third of the selection signal generating means for selecting is connected to the signal line and generates a third selection signal output, the second block provided corresponding to the plurality of the fourth selection signal lines And a fourth selection signal generating means for generating and outputting a fourth selection signal, the first main word line of any one of the plurality of first main word lines being activated. Then, the first and second sub-row decoding means corresponding thereto are brought into a state in which the first and second sub-word lines can be simultaneously activated, but the first or second sub-word line is activated. Which of the second main word lines is to be activated is selected in the first block by the first and second selection signals, and the second one of the plurality of second main word lines is selected. When the main word line is activated, the corresponding third and corresponding The third and fourth sub-word lines can be simultaneously activated by the fourth sub-row decoding means. Which of the third and fourth sub-word lines is to be activated is described above. The second block is characterized by being selected by the third and fourth selection signals.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

A dynamic semiconductor memory device according to a seventh invention is the dynamic semiconductor memory device according to the first invention, wherein a plurality of the sub word lines are provided corresponding to a plurality of the first main word lines. A plurality of fifth sub-word lines and a plurality of sixth sub-word lines, and a plurality of seventh sub-word lines and a plurality of eighth sub-word lines provided corresponding to the second main word line. A plurality of the selection signal lines further includes a word line, and the plurality of selection signal lines are arranged in the plurality of fifth selection signal lines and the plurality of sixth selection signal lines and the second block. A plurality of seventh selection signal lines and a plurality of eighth selection signal lines that are provided, wherein the plurality of sub-row decoding means are arranged on the first block and the plurality of first main signal lines are provided. A word line and a plurality of the fifth sub word lines and a plurality of the fifth selections A plurality of fifth sub-row decoding means connected to a signal line, a plurality of the first main word lines, a plurality of the sixth sub word lines, and a plurality of the sixth sub-word lines arranged on the first block. A plurality of sixth signals connected to the selection signal line of
Sub-row decoding means, a plurality of the second main word lines, a plurality of the seventh sub- word lines, and a plurality of the seventh selection signals which are arranged on the second block. A plurality of seventh sub-row decoding means connected to the line and a plurality of the second main word lines, a plurality of the eighth sub-word lines and a plurality of the eighth sub-word lines arranged on the second block. 8 further includes a sub-line decoding means, a plurality of said selection signal generating means, a plurality of the fifth selection signal lines provided corresponding to said first block plurality of connected to the selected signal lines Selected selection signal generating means connected to the first selection signal generating and outputting a fifth selection signal equivalent to the first selection signal, and a plurality of sixth selection signals provided corresponding to the first block. A sixth selection signal which is connected to a line and which generates and outputs a sixth selection signal equivalent to the second selection signal. Selection signal generating means, the generating and outputting the second to block provided corresponding plurality of said seventh is connected to the selection signal line and the third selection signal and the seventh selection signal equivalent 7 selection signal generating means and eight selection signals which are provided corresponding to the second block and are connected to the plurality of eighth selection signal lines, and which generate and output an eighth selection signal equivalent to the fourth selection signal. When the first main word line of any one of the plurality of first main word lines is activated, the eighth selection signal generating means is further included, and the corresponding first and second main word lines are activated. The first and second sub-word lines and the fifth and sixth sub-word lines can be simultaneously activated by the sub-row decoding means and the fifth and sixth sub-row decoding means. The first and fifth sub-word lines and the second and sixth sub-word lines In the first block, which one of the sub word lines is to be activated is selected by the first and second selection signals and the fifth and sixth selection signals, and a plurality of the plurality of the first and second selection signals are selected. the third and fourth sub-row decode means and collateral decoding of the seventh and eighth the any one of the second main word line and the second main word line corresponding to the activated By means of the third and fourth sub-word lines and the seventh
And the eighth sub-word line can be simultaneously activated, but the third and seventh sub-word lines and the fourth and eighth sub-word lines are activated.
Which of the sub-word lines is to be activated is selected in the second block by the third and fourth selection signals and the seventh and eighth selection signals. To do.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction content]

A dynamic semiconductor memory device according to a tenth invention is the dynamic semiconductor memory device according to the first invention, wherein a plurality of the sub word lines are a plurality of the first word lines.
A plurality of fifth sub-word lines and a plurality of sixth sub-word lines provided corresponding to the main word lines of the above, and a plurality of seventh sub-words provided corresponding to the second main word lines. A plurality of fifth selection signal lines and a plurality of sixth selection signal lines, which further include a word line and a plurality of eighth sub-word lines, and wherein the plurality of selection signal lines are arranged in the first block , And a plurality of seventh selection signal lines and a plurality of eighth selection signal lines arranged in the second block, wherein the plurality of sub-row decoding means are arranged on the first block. A plurality of fifth sub-row decoding means connected to the plurality of first main word lines, the plurality of fifth sub-word lines and the plurality of fifth selection signal lines, and the first block A plurality of the first main word lines, a plurality of the sixth sub-word lines, and a plurality of the first main word lines arranged above. Vice of the plurality of sixth sub row decode means coupled to the selection signal lines, are disposed on the second block of the plurality of the second main word lines and a plurality of said seventh
Word lead wires and a plurality of said seventh selection signal line connected to a plurality of seventh sub row decode means and disposed on the second block of the plurality of the second main word lines and a plurality of It further includes a plurality of eighth sub row decoding means connected to the eighth sub word line and a plurality of the eighth selection signal lines, and the plurality of selection signal generating means correspond to the first block. Fifth selection signal generating means connected to the plurality of fifth selection signal lines to generate and output a fifth selection signal, and a plurality of front portions provided corresponding to the first block. br /> Symbol sixth selection signal generating means, the selection of the second plurality are provided corresponding to the block of the seventh sixth selecting signal lines to be connected to generate a sixth selection signal output Seventh selection signal generating means connected to the signal line and generating and outputting a seventh selection signal; Provided corresponding to said second block
It further includes an eighth selection signal generating means connected to the plurality of eighth selection signal lines to generate and output an eighth selection signal, wherein any one of the plurality of first main word lines is included. When the first main word line is activated, the first and second sub-row decoding means corresponding thereto and the fifth sub-row decoding means are provided.
And the first and second sub-row decoding means.
The sub-word line and the fifth and sixth sub-word lines can be activated at the same time, but the first, second and fifth sub-word lines are activated.
And which of the sixth sub-word lines is activated is selected by the first and second selection signals and the fifth and sixth selection signals in the first block, and a plurality of the plurality of sub-word lines are selected. When the second main word line of any one of the second main word lines is activated, the third and fourth sub-row decoding means and the seventh sub-row decoding means corresponding thereto are activated.
And the third and fourth sub-row decoding means.
The sub-word line and the seventh and eighth sub-word lines can be simultaneously activated, but the third, fourth, and seventh sub-word lines are activated.
And which of the eight sub-word lines is activated is selected in the second block by the third and fourth selection signals and the seventh and eighth selection signals. To do.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction content]

A dynamic semiconductor memory device according to a thirteenth invention is the dynamic semiconductor memory device according to the twelfth invention, wherein the high-level voltage applied to the second signal line is the second voltage or the second voltage. One of the third voltages is selectively determined.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0046

[Correction method] Change

[Correction content]

Further, in FIG. 1, 8 is a block BL ₁
One of a plurality of memory cells provided inside, MWL
Is a main word line corresponding to a predetermined row set to which the memory cell 8 belongs, SWL is a sub word line corresponding to the row to which the memory cell 8 belongs in the row set, and 9 is a sub decode signal and a main word line. A decode circuit for deciding whether the sub-word line is active or inactive depending on the state, 10 is a sub-decode band which is a set of decode circuits in the same column as the decode circuit 9 of the decode circuits, and 11 is a decode circuit of the sub-decode band 10. A signal line for transmitting a sub-decode signal, and 12 is a bit line connected to the memory cell 8.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0049

[Correction method] Change

[Correction content]

Here, the sub-decode signals SDS ₁ to SDS _2m are obtained, for example, by taking the logical product of the block selection address BS and the address that selects an odd row or an even row of the block. To generate.

[Procedure Amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0054

[Correction method] Change

[Correction content]

Further, the arrangement of the sub-decoding circuits arranged in the block will be described. FIG. 3 is a block diagram showing an arrangement of sub-decode circuits in the block BL ₁ in FIG. 3, sub-decoding circuit D1~D6, MWL ₁ ~MWL _i primarily word line, SWL _1a ~ S
WL _3b is a sub word line. A sub-decode circuit D1, which controls activation or inactivation of the sub-word lines SWL _1a , SWL _1b, etc. connected to the first row memory cells in the block.
D3 is sub decode signal SDS _1, the bar SDS ₁ receives is connected to the main word line MWL _1. On the other hand, the sub-decode circuit D2 for controlling the activation or inactivation of the sub-words SWL _2a , SWL _2b, etc. in the second row in the block is connected to the main word line MWL ₁ and the sub-decode signals SDS ₂ , SDS ₂ Receive ₂ .

[Procedure Amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0055

[Correction method] Change

[Correction content]

₁ when the main word line MWL ₁ is activated
It is determined whether the sub-word lines SWL _1a , SWL _1b, etc. of the row are activated or the sub-word lines SWL _2a , SWL _2b, etc. of the second row are activated by the odd-numbered sub-decode band SD _1-1. , SD
Sub-decode signals SDS ₁ , SDS ₁ and SDS given to _1-3 etc. and even-numbered sub-decode bands SD _1-2 etc.
₂ , determined by bar SDS ₂ .

[Procedure Amendment 16]

[Document name to be amended] Statement

[Correction target item name] 0059

[Correction method] Change

[Correction content]

Subdecode signal generation circuit SDB10
Reference numeral ₂ denotes an OR gate 44 that takes the logical sum of the block selection addresses BS ₁ and BS _2, an AND gate 45 that takes the logical product of the output of the OR gate 44 and the address SDA ₂ for the subdecode signal, and an AND gate. A buffer 48 for transmitting the output of 45 to the blocks BL ₁ and BL ₂ as a sub-decode signal, a NOT gate 46 for outputting the logical value opposite to the output of the AND gate 45, and an output of the NOT gate 46 Block BL as decode signal
It is composed of a buffer 47 for transmitting to ₁ and BL ₂ .

[Procedure Amendment 17]

[Document name to be amended] Statement

[Correction target item name] 0064

[Correction method] Change

[Correction content]

[0064] For example, when selecting the memory cells in the block BL _2, the address BS ₂ for block selection, sub decode signal generating circuit SDB10 _2, 10 ₃ sub decode signal SDS _2, bars SDS _2, SDS _3, Enable output of bar SDS ₃ .

[Procedure 18]

[Document name to be amended] Statement

[Correction target item name] 0069

[Correction method] Change

[Correction content]

In the dynamic semiconductor memory device according to the first embodiment, the signal line for transmitting the sub-decode signal is arranged on the sense amplifier rows SA _{1 to} SA _m . By using the main and sub word lines in the divided decoder system , the pitch of the first metal wiring used as the wiring of the main word line is relaxed, so that the bus 60 for transmitting the sub decode signal is transmitted.
Can be arranged on each block BL _{1 to} BL _m of the memory cell array, that is, between the main word lines. For example, one signal line may be arranged between one main word line. Further, the position between the main word lines for arranging this signal line does not have to be at the end of the block, and may be in the middle. From this extra eliminates the need to run a signal line on the sense amplifier column SA ₁ -SA _m, can suppress an increase in the width of the sense amplifier column SA ₁ -SA _m. Only the arrangement of the signal line for transmitting the sub-decode signal is changed.
Other effects of using the dynamic semiconductor memory device according to the embodiment are similar to those of the first embodiment.

[Procedure Amendment 19]

[Document name to be amended] Statement

[Correction target item name] 0075

[Correction method] Change

[Correction content]

Although the signal line for transmitting the sub-decode signal is divided in the fifth embodiment as shown in FIG. 10, the sub-decode signal may be supplied from one side to distribute only the gate load. . In FIG. 10, SDB3 ₁
To SDB3 _m are corresponding to the blocks BL _{1 to} BL _m , respectively, and the subdecode signal generation circuit SDB1 ₁ shown in FIG.
～SDB1 _m and sub decode signal generating circuit SDB2 ₁ to S
A sub-decode signal generation circuit combining DB2 _m , 72,
Reference numeral 73 is a bus for transmitting sub-decode signals corresponding to the buses 70 and 71 shown in FIG. 9, respectively. In this case, the number of signal lines for subdecode signals wired in each of the sense amplifier columns SA _{1 to} SA _m increases, but the number of subdecode circuits is reduced and the load of the buffer for transmitting the subdecode signals is reduced. The speed can be increased by the amount of distribution. Here, the sub-decode signal generation circuit is arranged in the region where the main row decoder on the left side of the blocks BL _{1 to} BL _m is provided, but it may be arranged on the right side of the blocks BL _{1 to} BL _m .

[Procedure amendment 20]

[Document name to be amended] Statement

[Name of item to be corrected] 0083

[Correction method] Change

[Correction content]

Next, the operation of this circuit will be described with reference to FIG. For example, here block B shown in FIG.
It is assumed that L ₂ is selected. The block selection address BS ₂ corresponding to the block BL ₂ changes from the low level to the high level in the operating state. At this time,
The voltage level of the selected main word line MWL changes from gnd to V _PP . The other voltage levels of the main word line MWL remain gnd. Also, block BL ₂
As the sub-decode signal supplied to SDS ₁ ,
It is assumed that there are bars SDS ₁ , SDS ₂ and bars SDS ₂ . In the operating state, voltage V _CC is applied as sub-decode signal SDS ₁ to activate a predetermined sub-decode circuit, voltage gnd is applied as sub-decode signal SDS ₁ , and other sub-decode circuits are turned off. voltage gnd given as a sub decode signal SDS ₂ to active, the voltage V _pp is applied as a sub decode signal bars SDS _2.

[Procedure correction 21]

[Document name to be amended] Statement

[Correction target item name] 0084

[Correction method] Change

[Correction content]

Standby state, sub-decode circuits belonging to non-selected blocks and main word lines of selected blocks
There The sub-decoding circuit which is deactivated by the sub decode signal despite the activity, the same signal is given, that is, MWL main word lines of the sub-decoding circuit
Is the voltage gnd, the sub-decode signal SDS is the voltage gnd, and the sub-decode signal SDS is the voltage V _PP.
Is given. At this time, in the sub-decoding circuit shown in FIG. 12, the transistors Q5 and Q6 are turned off,
The transistor Q7 becomes conductive. At this time, the voltage gnd is applied to the sub word line SWL through the transistor Q7.

[Procedure correction 22]

[Document name to be amended] Statement

[Correction target item name] 0088

[Correction method] Change

[Correction content]

Example 8. Next, a dynamic semiconductor memory device according to an eighth embodiment of the present invention will be described with reference to FIGS. 14 and 15. FIG. 14 is a circuit diagram showing a structure of a circuit for converting a sub-decode signal of the dynamic semiconductor memory device according to the eighth embodiment of the present invention. 14
, 80 is a NOT gate that outputs a signal having a logic value opposite to that of the block selection address BS, and 81 is NO.
Output of T gate 80 and subdecode signal S shown in Table 2
An OR gate that takes the logical sum of the sub-decode signal SDE corresponding to DS and Q8 is a source to which the voltage V _PP is applied and O
P having a gate and a drain for receiving the output of the R gate 81
A MOS transistor 82 is an AND gate that takes the logical product of the sub-decode signal SDE and the block selection address BS. Q9 is a source to which the voltage V _CC is applied, a gate to which the block selection address BS is applied, and the transistor Q.
8 is a PMOS transistor having a drain connected to the drain of Q8, and Q10 is an NMOS transistor having a drain connected to the drain of the transistor Q8, a gate connected to the output of the AND gate 82, and a source to which the ground voltage gnd is applied. is there. The sub-decode signal bar SDS is output from the drain of the transistor Q8. Here, the block selection address BS and the sub-decode circuit activation signal SDE become high level when selected. All the logic gates shown in FIG. 14 are driven by the voltage V _PP .

[Procedure amendment 23]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

[Procedure correction 24]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 12

[Correction method] Change

[Correction content]

[Fig. 12]

[Procedure correction 25]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 13

[Correction method] Change

[Correction content]

[Fig. 13]

Claims (13)

[Claims] 1. A plurality of memory elements divided into a plurality of blocks including at least a first block and a second block and arranged in a plurality of rows and a plurality of columns to dynamically store information by accumulating charges, and Each of the plurality of blocks has a plurality of main word lines and a plurality of sub word lines which are provided in each of the plurality of blocks and are arranged in parallel with each other to select the memory element. A memory cell array formed to have first and second sides parallel to the rows and third and fourth sides parallel to the columns; and a memory cell array provided corresponding to each of the plurality of blocks. A plurality of sense amplifier rows arranged facing the first side or the second side of the corresponding block, and a plurality of sense amplifier rows provided corresponding to each of the plurality of blocks. A plurality of main row decoding units arranged on the side of the third side of the block for selectively activating the plurality of main word lines in the corresponding block; A plurality of sub-row decoding means connected to the plurality of sub-word lines and provided on the memory cell array and the sub-row decoding means connected to and connected to the plurality of sub-row decoding means are activated. A plurality of selection signal lines for transmitting a selection signal for, and a plurality of selection signal generation means for generating the selection signal connected to the plurality of selection signal lines, a plurality of the main word line, At least including a plurality of first main word lines arranged in the first block and a plurality of second main word lines arranged in the second block, and the plurality of sub word lines are , At least Number of the first
A plurality of first sub-word lines and a plurality of second sub-word lines provided corresponding to the main word lines of the above, and a plurality of third sub-lines provided corresponding to the second main word lines. A plurality of selection signal lines including at least a plurality of first selection signal lines and a plurality of second selection word lines arranged in the first block;
Selection signal lines, and a plurality of third selection signal lines and a plurality of fourth selection signal lines arranged in the second block, wherein the plurality of sub-row decoding means are at least the first
A plurality of first sub-row decoding means arranged on the block and connected to the plurality of first main word lines, the plurality of first sub-word lines and the plurality of first selection signal lines, A plurality of the first main word lines, a plurality of the second sub-word lines, and a plurality of the second blocks are arranged on the first block.
A plurality of second sub-row decoding means connected to the selection signal line, and a plurality of the second sub-row decoding means arranged on the second block.
A plurality of third sub-row decoding means connected to the main word line, the plurality of third sub-row word lines, and the plurality of third selection signal lines, and a plurality of third sub-row decoding means arranged on the second block. A plurality of fourth main word lines, a plurality of fourth sub-word lines and a plurality of fourth selection signal lines connected to a plurality of fourth
Sub-row decoding means, and the plurality of selection signal generating means include at least the first
First selection signal generating means that is provided corresponding to the first block and that is connected to the first selection signal line and that generates and outputs the first selection signal, and the first selection signal generating means that is provided corresponding to the first block. Second selection signal generating means connected to the second selection signal line and generating and outputting the second selection signal; and third selection signal generating means provided corresponding to the second block and connected to the third selection signal line. Selecting signal generating means for generating and outputting the selecting signal, and a third selecting signal generating means which is provided corresponding to the second block, is connected to the fourth selecting signal line, and generates and outputs the fourth selecting signal. 4 selection signal generating means, and when any one of the plurality of first main word lines is activated, the first and second sub-rows corresponding thereto are activated. The first and second sub-word lines are simultaneously activated by the decoding means. In the first block, which of the first and second sub-word lines is activated is selected by the first and second selection signals. When any one of the second main word lines of the second main word line is activated, the third and fourth sub-row decoding means corresponding thereto activate the third and fourth sub-word lines. Although the sub-word lines can be activated at the same time, in the second block, it is determined whether the third or fourth sub-word line is activated by the third word.
And a dynamic semiconductor memory device which is selected by a fourth selection signal. 2. The dynamic semiconductor memory device according to claim 1, wherein the plurality of selection signal lines are arranged on the plurality of sense amplifier columns. 3. The dynamic semiconductor memory device according to claim 1, wherein the plurality of selection signal generating means are arranged on the side of the third side of the plurality of blocks. 4. The first and second blocks are arranged adjacent to each other, and the second selection signal and the third selection signal are the same, and the second and third selection signal lines and 2. The dynamic semiconductor memory device according to claim 1, wherein the dynamic semiconductor memory device shares the second and third selection signal generating means. 5. The dynamic semiconductor memory device according to claim 1, wherein the plurality of selection signal generation means are arranged on the side of the fourth side of the plurality of blocks. 6. The plurality of selection signal lines are arranged on the plurality of blocks.
The dynamic semiconductor memory device described. 7. The plurality of sub-word lines are a plurality of fifth sub-word lines and a plurality of sixth sub-word lines provided corresponding to the plurality of first main word lines, and the plurality of sub-word lines. A plurality of seventh sub word lines and a plurality of eighth sub word lines provided corresponding to the two main word lines, and the plurality of selection signal lines are arranged in the first block. Further including a plurality of fifth selection signal lines and a plurality of sixth selection signal lines, and a plurality of seventh selection signal lines and a plurality of eighth selection signal lines arranged in the second block. A plurality of the sub-row decoding means are arranged on the first block and are connected to the plurality of first main word lines, the plurality of fifth sub-word lines and the plurality of fifth selection signal lines. A plurality of connected fifth sub-row decoding means, a plurality of said first sub-row decoding means arranged on said first block; Word lines and a plurality of said sixth sub-word lines and a plurality of said sixth sixth sub row decode means of a plurality of connected to the selected signal line of the second
A plurality of seventh sub-row decoding means arranged on the block and connected to the plurality of second main word lines, the plurality of seventh sub-row word lines and the plurality of seventh selection signal lines. And a plurality of eighth sub-lines arranged on the second block and connected to the plurality of second main word lines, the plurality of eighth sub-word lines, and the plurality of eighth selection signal lines. A fifth decoding circuit further includes a row decoding circuit, wherein the plurality of selection signal generation circuits are provided corresponding to the first block and are connected to the fifth selection signal line, and are equivalent to the first selection signal. Fifth selection signal generating means for generating and outputting a signal, a sixth selection signal which is provided corresponding to the first block and is connected to the sixth selection signal line and which is equivalent to the second selection signal. A sixth selection signal generating means for generating and outputting The third selection signal line is provided correspondingly and is connected to the seventh selection signal line.
Second selection signal generating means for generating and outputting a seventh selection signal equivalent to the second selection signal and the fourth selection signal line provided corresponding to the second block and connected to the eighth selection signal line.
Further includes an eighth selection signal generating means for generating and outputting an eighth selection signal equivalent to the first selection word, and the first main word of any one of the plurality of first main word lines. When a line is activated, the first and second sub-row decoding means and the fifth and sixth sub-row decoding means corresponding to the line activate the first and second sub-word lines and the fifth and sixth sub-word lines. The six sub-word lines can be activated at the same time, and which of the first and fifth sub-word lines and the second and sixth sub-word lines is to be activated is determined. The first block is selected by the first and second selection signals and the fifth and sixth selection signals, and the second one of the plurality of second main word lines is selected. The third word corresponding to the activation of the main word line The third and fourth sub-word lines and the seventh and eighth sub-word lines can be simultaneously activated by the fourth and fourth sub-row decoding means and the seventh and eighth sub-decoding means. Which of the third and seventh sub-word lines and the fourth and eighth sub-word lines is to be activated in the second block. 2. The dynamic semiconductor memory device according to claim 1, wherein the dynamic semiconductor memory device is selected by a selection signal and the seventh and eighth selection signals. 8. The first to fourth selection signal generating means include the third block of each of the first and second blocks.
And the fifth to eighth selection signal generating means are arranged on the side of the fourth side of each of the first and second blocks. The dynamic semiconductor memory device according to claim 7. 9. The dynamic semiconductor memory device according to claim 7, wherein the plurality of selection signal generating means are arranged on the side of the third side of each of the plurality of blocks. 10. The plurality of sub-word lines are a plurality of fifth sub-word lines and a plurality of sixth sub-word lines provided corresponding to the plurality of first main word lines, and the plurality of sub-word lines. A plurality of seventh sub word lines and a plurality of eighth sub word lines provided corresponding to the two main word lines, and the plurality of selection signal lines are arranged in the first block. Further including a plurality of fifth selection signal lines and a plurality of sixth selection signal lines, and a plurality of seventh selection signal lines and a plurality of eighth selection signal lines arranged in the second block. A plurality of the sub-row decoding means are arranged on the first block and are connected to the plurality of first main word lines, the plurality of fifth sub-word lines and the plurality of fifth selection signal lines. A plurality of connected fifth sub-row decoding means, a plurality of the first sub-row decoding means arranged on the first block; The main word lines and a plurality of said sixth sub-word lines and a plurality of said sixth sixth sub row decode means of a plurality of connected to the selected signal line of the second
A plurality of seventh sub-row decoding means arranged on the block and connected to the plurality of second main word lines, the plurality of seventh sub-row word lines and the plurality of seventh selection signal lines. And a plurality of eighth sub-lines arranged on the second block and connected to the plurality of second main word lines, the plurality of eighth sub-word lines, and the plurality of eighth selection signal lines. A row decoding means is further included, and the plurality of selection signal generating means are provided corresponding to the first block and are connected to the fifth selection signal line, and a fifth selection signal line is provided.
Selecting signal generating means for generating and outputting the selecting signal, and a fifth selecting signal generating means provided corresponding to the first block and connected to the sixth selecting signal line for generating and outputting a sixth selecting signal. 6 selection signal generating means, 7th selection signal generating means which is provided corresponding to the 2nd block, is connected to the 7th selection signal line, and generates and outputs a 7th selection signal, and the 2nd selection signal generating means. Of the plurality of first main word lines, which further includes an eighth selection signal generation unit which is provided corresponding to the block of FIG. 9 and is connected to the eighth selection signal line to generate and output an eighth selection signal. When any one of the first main word lines is activated, the first and second sub-row decoding means and the fifth and sixth sub-row decoding means corresponding thereto activate the first and second sub-row decoding means. The second sub-word line and the fifth and sixth sub-lines Although the word lines can be activated at the same time, which of the first, second, fifth and sixth sub-word lines is activated in the first block is the first and second sub-word lines. The second main word line selected by the second select signal and the fifth and sixth select signals is activated when any one of the second main word lines is activated. The third and fourth sub-row decoding means and the seventh and eighth sub-decoding means can simultaneously activate the third and fourth sub-word lines and the seventh and eighth sub-word lines. However, in the second block, which of the third, fourth, seventh and eighth sub-word lines is to be activated is selected. To select by the seventh and eighth selection signals The dynamic semiconductor memory device according to claim 1, which is characterized in that: 11. The first to fourth selection signal generation means are arranged on the third side of each of the first and second blocks, and the fifth to eighth selection signal generation means are provided. 11. The dynamic semiconductor memory device according to claim 10, wherein the means is arranged on the side of the fourth side of each of the first and second blocks. 12. A plurality of memory elements arranged in a plurality of rows and a plurality of columns for dynamically storing information by accumulating charges and a set of rows in which the plurality of memory elements are arranged are not selected. A first word voltage or a second voltage higher than the first voltage for making a selection, a main word line, and a third voltage lower than the first voltage and the second voltage. A first signal line for transmitting a binary first sub-decode signal, and a second signal line for transmitting a second sub-decode signal having a logical value complementary to the first sub-decode signal. A signal line, a sub-word line for selecting a predetermined row in the set of rows according to the active state of the main word line and the first and second sub-decode signals, and the main word line One connected current electrode, connected to the second signal line A P-channel first MOS transistor having a controlled control electrode and the other current electrode connected to the sub word line, and one current electrode connected to the main word line and connected to the first signal line. N-channel second MOS transistor having a control electrode and the other current electrode connected to the sub word line, one current electrode connected to the sub word line, and a control electrode connected to the second signal line And a N-channel third MOS transistor having the other current electrode connected to the first voltage, and a dynamic semiconductor memory device. 13. The high-level voltage applied to the second signal line is selectively determined to be either the second voltage or the third potential.
13. The dynamic semiconductor memory device according to claim 12.