JPH08186185A - Non-volatile semiconductor storage and its manufacture - Google Patents

Abstract

PURPOSE: To prevent the data damage of a memory cell adjacent to a memory cell for performing writing-in at the time of writing-in while ensuring a sufficient read-out current or improve the writing efficiency or decrease the writing voltage, and further reduce power consumption. CONSTITUTION: In a split-bit-line NOR system flash EEPROM, a diffusion layer 4 is provided on both sides of a floating gate 3 so that one edge part overlaps with the floating gate 3 and all or one portion of a gate insulation film 2 at a part where the floating gate 3 and one diffusion layer 4 overlap is formed to be thicker than other parts. A part excluding the thickly formed part out of the gate insulation film 2 is made to be thick so that F-N tunneling of electrons is enabled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device and a method for manufacturing the same, and is particularly suitable for application to a so-called flash EEPROM.

[0002]

2. Description of the Related Art In recent years, in flash EEPROMs, as a memory cell structure suitable for miniaturization, a so-called contactless type memory cell structure has been proposed, in which one bit contact is made to many memory cells. . As a flash EEPROM using a memory cell structure most suitable for miniaturization, a virtual ground array (Virtual Ground Arra) of a system called a divided bit line NOR (DINOR) system is used.
There is a y) type flash EEPROM (VLSI Simp. 19
93, p.57).

This DINOR type virtual ground array type flash EEPROM is composed of a memory cell array as shown in FIG. 13 and has word lines WL1, WL2, WL3 as control gates.
, And bit lines D1, D2, D3, D4 ,.
In this flash EEPROM, data is written by applying + 5V to a bit line connected to a memory cell to be written and applying -9V to a word line as a control gate, so that electrons in a floating gate of the memory cell are removed by a Fowler. -It is performed by pulling out to the bit line by Nordheim (F-N) tunneling. Data can be erased by applying +10 V to the word line as a control gate and -9 V to the substrate and source lines to inject electrons from the substrate to the floating gate to collectively erase all the memory cells or blocks of the memory cell array. Then do. Further, data reading is performed by adding +1. To the bit line connected to the memory cell to be read.
5V is applied, the bit line (source line) paired with this bit line is set to 0V, + 3V is applied to the word line as the control gate, and the current conduction of the memory cell is performed. At this time, the other bit lines are opened and the substrate is set to 0V.

In this DINOR type virtual ground array type flash EEPROM, there is no distinction between a bit line and a source line, and one diffusion layer line is connected to one of a pair of memory cells adjacent to each other. As a line, the other will be shared as a source line. Therefore, when data is written to a specific memory cell, the floating gate and the diffusion layer should be overlapped in order to prevent the electrons in the floating gate of the memory cell adjacent to the memory cell from being extracted. It is necessary to make asymmetry between memory cells adjacent to each other.

In the above document (VLSI Simp. 1993, p.57), a DINOR type virtual ground array type flash EEP having such an asymmetric structure is described.
A ROM as shown in FIG. 14 has been proposed. As shown in FIG. 14, this flash EEPROM
In the above, the floating gate 103 is provided on the p-type silicon (Si) substrate 101 with the gate insulating film 102 interposed therebetween. Reference numeral 104 denotes an n ⁺ type diffusion layer provided in the p type Si substrate 101. This n ⁺ type diffusion layer 10
4 overlaps the floating gate 103 of one memory cell of the pair of memory cells adjacent to each other, but the floating gate 10 of the other memory cell
It does not overlap with 3. Here, the n ⁺ -type diffusion layer 104 in which the overlapping with the floating gate 103 is asymmetrical between a pair of memory cells adjacent to each other is such that after the floating gate 103 is formed, arsenic (As) which is an n-type impurity is formed. Is formed by performing ion implantation (oblique ion implantation) from a direction inclined with respect to the normal to the substrate surface. Reference numeral 105 is an interlayer insulating film, and 106 is a word line as a control gate.

On the other hand, as a stack gate type DINOR type flash EEPROM, FIGS.
The following is proposed. Here, FIG. 16 is an enlarged cross-sectional view taken along line XVI-XVI of FIG. As shown in FIG. 15 and FIG. 16, in this flash EEPROM, a field insulating film 202 is selectively provided on the surface of a p-type Si substrate 201, thereby performing element isolation. The p-type Si substrate 201 in a predetermined portion surrounded by the field insulating film 202
A floating gate 204 is provided over the gate insulating film 203. A word line 206 as a control gate is further provided on the floating gate 204 via an interlayer insulating film (coupling insulating film) 205. Reference numerals 207 and 208 denote n ⁺ type diffusion layers provided in the p type Si substrate 201 in a predetermined portion surrounded by the field insulating film 202 in a self-aligned manner with respect to the floating gate 204 and the word line 206. These n ⁺ type diffusion layers 207 and 208
Are used as a source region and a drain region, respectively. Here, these n ⁺ type diffusion layers 207 and 208
One end portion of the memory cell overlaps with the floating gate 204 (in FIG. 15, the overlapping portion of one memory cell is indicated by a stippled line). Reference numeral 209 indicates an interlayer insulating film, and 210 indicates a contact hole for contacting a bit line (not shown) to the n ⁺ type diffusion layer 208 used as a drain region.

The DINOR shown in FIGS. 15 and 16
In the flash EEPROM of the system, as shown in FIG. 17, for writing data, a positive voltage (about +5 V) is applied to the n ⁺ type diffusion layer 208 as the drain region of the memory cell to be written, and the word line 206 as the control gate is used. Negative voltage (about -8V) is applied to the
V, the n ⁺ type diffusion layer 207 as a source region is opened, and the floating gate 204 of the memory cell is opened.
This is performed by extracting the electrons therein to the n ⁺ type diffusion layer 208 as the drain region by FN tunneling. On the other hand, when erasing data, as shown in FIG. 18, a positive voltage (about 10 V) is applied to the word line 206 as a control gate.
Is applied to apply a negative voltage (about −8 V) to the n ⁺ type diffusion layer 207 serving as the substrate and the source region, and the n ⁺ type diffusion layer 208 serving as the drain region is opened to form the p-type S layer.
By injecting electrons from the i substrate 201 to the floating gate 204, this is performed for all memory cells or blocks.

[0008]

However, in the above-mentioned conventional DINOR virtual ground array type flash EEPROM shown in FIG. 14, the n ⁺ type diffusion layers 104 used as the source regions are adjacent to each other. Since the structure is offset with respect to the floating gate 103 of one of the memory cells, the sufficient read current can be obtained when data is read from a specific memory cell. There is a problem that you cannot do it.

On the other hand, the stack gate type DINOR flash EEPR shown in FIGS. 15 and 16 described above.
The OM has the following problems.

That is, the stack gate type DINOR type flash EE shown in FIGS. 15 and 16 described above.
In a PROM, in order to meet the demands such as improving the writing efficiency and enabling writing at a low voltage in the future, when the same voltage is applied to each terminal, the drain region is formed. The voltage V _D −V _F (see FIG. 19) applied between the n ⁺ -type diffusion layer 208 and the floating gate 204 must be increased. However, V _D is the potential of the n ⁺ type diffusion layer 208 as the drain region, and V _F is the potential of the floating gate 204.

Here, the potential V _F of the floating gate 204 is the capacitance C _C between the floating gate 204 and the word line 206 as a control gate,
A capacitance C _S between the floating gate 204 and the n ⁺ type diffusion layer 207 serving as a source region, a capacitance C _B between the floating gate 204 and the substrate, and an n ^{+ serving} as the drain region and the drain region.
Using the capacitance C _D with the type diffusion layer 208 (see FIG. 19), V _F = (C _C / C _T ) V _C + (C _S / C _T ) V _S + (C _B / C _T ). It is expressed as V _B + (C _D / C _T ) V _D (C _T = C _C + C _S + C _B + C _D ). Note that V _C is the potential of the word line 206 as a control gate, and V _S is n ⁺ as a source region.
The potential of the diffusion layer 207, C _B is the potential of the substrate, and V _D is the potential of the n ⁺ type diffusion layer 208 as the drain region.

Therefore, V _D -V _F = (1-C _D / C _T ) V _D- (C _C / C _T )
It becomes V _C − (C _S / C _T ) V _S − (C _B / C _T ) V _B. From this, in order to increase V _D −V _F ,
Floating gate 204 and n as drain region
^It can be seen that it is necessary to make the capacitance C _D between the ⁺ type diffusion layer 208 smaller.

However, FIG. 15 and FIG.
In the stacked gate type DINOR flash EEPROM shown in FIG. 1, the capacitance C _D is equal to the floating gate 204 and the n ⁺ type diffusion layer 20 as the drain region.
Since it is determined by the area of the overlapping portion with 8, the reduction is naturally limited. Therefore, it has been difficult to improve the writing efficiency and to be able to write even at a low voltage.

Further, this DINOR flash E
In the EPROM, a floating gate 204 and an n ⁺ type diffusion layer 208 as a drain region are used at the time of writing.
Since a high voltage is applied between the n ⁺ type diffusion layer 208 as the drain region and the p type Si substrate 201, a leak current caused by band-to-band tunneling flows, and in terms of power consumption. It's a problem.

Therefore, an object of the present invention is to ensure that a read current is sufficiently secured at the time of reading data, while destroying data held in a memory cell adjacent to a memory cell to be written at the time of writing data. It is an object of the present invention to provide a non-volatile semiconductor memory device that can be prevented and a manufacturing method thereof.

Another object of the present invention is to improve the writing efficiency or lower the writing voltage.
Moreover, it is to provide a low power consumption non-volatile semiconductor memory device and a manufacturing method thereof.

[0017]

To achieve the above object, the first invention of the present invention is a floating gate (3) provided on a semiconductor substrate (1) via a gate insulating film (2). And one end of the floating gate (3) overlaps with the floating gate (3).
A non-volatile semiconductor memory device having diffusion layers (4) respectively provided in the semiconductor substrate (1) on both sides of the floating gate (3) and one diffusion layer (4) Gate insulation film (2)
Is characterized in that at least a part thereof is formed thicker than the other parts.

In the first aspect of the present invention, writing is performed by extracting the electrons in the floating gate to the other diffusion layer or one diffusion layer. This electron extraction is performed by FN tunneling.

In one embodiment of the first aspect of the present invention, the entire gate insulating film in the portion where the floating gate and one diffusion layer overlap is formed thicker than the other portions.

In another embodiment of the first aspect of the present invention, a part of the gate insulating film in a portion where the floating gate and one diffusion layer overlap each other is formed thicker than other portions. .

In the first aspect of the present invention, typically, the semiconductor substrate is made of silicon, the gate insulating film is made of silicon dioxide, and the floating gate is made of polycrystalline silicon.

In a second aspect of the present invention, the floating gate (3) provided on the semiconductor substrate (1) via the gate insulating film (2) and one end of the floating gate (3) overlap the floating gate (3). A method of manufacturing a non-volatile semiconductor memory device, comprising: a diffusion layer (4) provided in a semiconductor substrate (1) on both sides of a floating gate (3). After sequentially forming the gate insulating film (2) and the semiconductor film,
Forming a floating gate (3) by patterning the semiconductor film; and selectively insulating at least a part of one end of the floating gate (3) to form a gate insulating film (2) in that part. It has a step of increasing the thickness and a step of forming a diffusion layer (4) by introducing impurities into the semiconductor substrate (1) using the floating gate (3) as a mask.

In one embodiment of the second aspect of the present invention, the entire one end of the floating gate is selectively made into an insulator. Specifically, for example, the entire one end of the floating gate is selectively oxidized to become an insulator.

In another embodiment of the second aspect of the present invention, a part of one end of the floating gate is selectively made into an insulator. Specifically, for example, a part of one end of the floating gate is selectively oxidized to make that part an insulator.

In the second aspect of the present invention, typically, the semiconductor substrate is made of silicon, the gate insulating film is made of silicon dioxide, and the semiconductor film is made of polycrystalline silicon.

In the present invention, the non-volatile semiconductor memory device is, for example, a virtual ground array type flash EEPROM.

In the present invention, the nonvolatile semiconductor memory device is typically divided bit line NOR (DIN
It is an OR type flash EEPROM.

[0028]

According to the nonvolatile semiconductor memory device of the first aspect of the present invention configured as described above, at least a part of the gate insulating film in the portion where the floating gate and one diffusion layer overlap each other is Since it is formed thicker than the part, for example, DINOR type virtual
In the ground array type flash EEPROM, when data is written by drawing out electrons in the floating gate to the other diffusion layer, especially the entire gate insulating film in the portion where the floating gate and one diffusion layer overlap each other By forming it thicker than the portion of FIG. 3, it is possible to prevent the electrons in the floating gate from being extracted to this one diffusion layer by F-N tunneling during the writing of data, and the electrons in the floating gate to the other side by F-N tunneling. The diffusion layer can be extracted only. by this,
It is possible to prevent the data held in the memory cell adjacent to the memory cell to be written from being destroyed. Further, since the floating gate and the one diffusion layer and the other diffusion layer are not offset from each other,
A sufficient read current can be secured when reading data.

On the other hand, in the case of writing data by extracting electrons in the floating gate to one diffusion layer in a DINOR type flash EEPROM, for example, gate insulation in a portion where the floating gate and one diffusion layer overlap each other. By forming a part of the film thicker than the other part, floating is achieved through the part of the gate insulating film in the part where the floating gate and one diffusion layer overlap, except for the part where the part is thickly formed. The electrons in the gate can be extracted to one diffusion layer by FN tunneling. Therefore, the area of the region where electrons are extracted by F-N tunneling at the time of writing can be reduced, which can improve the writing efficiency or lower the writing voltage. Even when a high voltage is applied between the floating gate and one diffusion layer at the time of writing, a part of the gate insulating film formed thickly in the portion where the floating gate and the one diffusion layer overlap each other. Since the electric field applied to is weak, band-to-band tunneling can be suppressed in this portion. Therefore, the area of the region where band-to-band tunneling occurs at the time of writing can be reduced, so that the leak current can be reduced correspondingly, and thus the power consumption can be reduced.

According to the method of manufacturing a non-volatile semiconductor memory device of the second aspect of the present invention configured as described above, at least a part of one end of the floating gate is selectively made into an insulator. By increasing the thickness of the gate insulating film in the portion, at least a portion of the gate insulating film in the portion where the floating gate and one diffusion layer overlap is formed thicker than the other portions. The non-volatile semiconductor memory device according to the first invention can be manufactured.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a DINOR type virtual ground array type flash EEPROM according to a first embodiment of the present invention. The equivalent circuit of this flash EEPROM is similar to that shown in FIG.

As shown in FIG. 1, in the DINOR virtual ground array type flash EEPROM according to the first embodiment, a gate insulating film 2 is provided on a p-type Si substrate 1 and the gate insulating film 2 is provided. A floating gate 3 is provided on the upper surface 2. The floating gate 3 is provided for each memory cell. Here, the gate insulating film 2 is made of a SiO ₂ film, and the floating gate 3 is made of, for example, a polycrystalline Si film having a thickness of about 100 nm doped with n-type impurities or p-type impurities.

In the p-type Si substrate 1 on both sides of the floating gate 3, the n ⁺ -type diffusion layer is self-aligned with the floating gate 3 and one end thereof overlaps with the floating gate 3. 4 are provided respectively. The n ⁺ type diffusion layer 4 extends in the direction perpendicular to the arrangement direction of the floating gates 3 and is used as a bit line or a source line.

Reference numeral 5 indicates an interlayer insulating film such as a SiO ₂ film. The interlayer insulating film 5 is provided so as to cover the floating gate 3. Then, the word line 6 as a control gate is formed on the interlayer insulating film 5.
Are provided so as to overlap the floating gate 3.

In the first embodiment, one floating gate 3 and a word line 6 laminated on the floating gate 3 with an interlayer insulating film 5 interposed therebetween and p on both sides thereof are formed.
One memory cell is formed by the pair of n ⁺ type diffusion layers 4 provided in the type Si substrate 1.

In the first embodiment, one end 3a of the floating gate 3 overlapping the n ⁺ type diffusion layer 4 on the side where electrons are not extracted at the time of writing data is rounded. The gate insulating film 2 in 3a is formed thicker than other portions. The thickness of the portion of the gate insulating film 2 excluding this thickly formed portion is set to a thickness that allows F-N tunneling of electrons, for example, about 10 nm.

Next, the DINOR virtual ground according to the first embodiment constructed as described above.
Writing, erasing and reading operations of the array type flash EEPROM will be described.

First, consider the case where data is written to the memory cell A shown in FIG. That is, in order to write to the memory cell A, the bit line D
For example, + 5V is applied to 3, the other bit lines are opened, -9V is applied to the word line WL1, and 0 is applied to the substrate.
By setting V, electrons in the floating gate 3 are selectively extracted to the bit line D3.

Erasing is performed for each block of all memory cells or memory cell arrays. All word lines or word lines of blocks to be erased are set to, for example, +10 V, bit lines and substrates are set to, for example, -9 V, and all memory cells or blocks are collectively set. Then, electrons are injected from the substrate into the floating gate 3.

Next, in order to read the memory cell A, for example, +1.5 V is applied to the bit line D3, and the bit line (source line) D2 paired with the bit line D3 is set to 0.
V. Then, for example, +3 V is applied to the word line WL1 and the data is read by the current conduction of the memory cell A. At this time, the other bit lines are opened and the substrate is set to 0V.

Next, the DINOR virtual ground according to the first embodiment constructed as described above.
A method of manufacturing the array type flash EEPROM will be described.

As shown in FIG. 2, first, the p-type Si substrate 1
A gate insulating film 2 made of a SiO ₂ film is formed on the surface of the SiO ₂ film by, for example, a thermal oxidation method. Next, a polycrystalline Si film is formed on the gate insulating film 2 by, for example, a CVD method, and the polycrystalline Si film is doped with impurities by, for example, an ion implantation method or a thermal diffusion method to reduce the resistance. The crystalline Si film is patterned into a predetermined shape by etching. As a result, the floating gate 3 is formed.

Next, as shown in FIG. 3, an interlayer insulating film 5 such as a SiO ₂ film and S are formed on the entire surface by, eg, CVD method.
The i ₃ N ₄ film 7 is sequentially formed. The thickness of the SiO ₂ film constituting the interlayer insulating film 5 is, for example, 20nm approximately, Si ₃
The N ₄ film 7 has a thickness of, for example, about 10 nm.

Next, as shown in FIG. 4, a Si ₃ N ₄ film 7 is formed.
A resist pattern 8 having an opening at a predetermined portion is formed thereon by a lithography method, and then the resist pattern 8 is used as a mask, for example, reactive ion etching (RIE).
The the Si ₃ N ₄ film 7 is etched on the substrate surface and the direction perpendicular by anisotropic etching such as law, to remove the Si ₃ N ₄ film 7 which is not covered by the resist pattern 8.

Next, after removing the resist pattern 8,
Thermal oxidation is performed using the Si ₃ N ₄ film 7 as an oxidation mask. As a result, as shown in FIG. 5, one end portion 3a of the floating gate 3 not covered with the Si ₃ N ₄ film 7 is selectively thermally oxidized and rounded, and the gate insulating film 2 at the one end portion 3a is covered. The thickness is increased compared to other parts. Here, this thermal oxidation is performed by, for example, a wet oxidation method, and the oxidation temperature is, eg, about 850 ° C. The oxidation time is determined by the shape of the one end 3a of the floating gate 3 and device characteristics.

Next, after the Si ₃ N ₄ film 7 is removed by etching, the floating gate 3 is used as a mask to form p-type Si.
N-type impurities such as As are ion-implanted into the substrate 1.
Then, a heat treatment for electrically activating the implanted impurities is performed if necessary. As a result, as shown in FIG. 1, the p-type Si substrate 1 on both sides of the floating gate 3 is self-aligned with the floating gate 3 and one end thereof overlaps the floating gate 3. The n ⁺ type diffusion layer 4 is formed.

Next, SiO 2 is formed on the entire surface by, for example, the CVD method.
After forming the _two films, the SiO ₂ film is etched back in the direction perpendicular to the substrate surface by, for example, the RIE method, and the recesses between the floating gates 3 adjacent to each other are formed in the Si.
It is filled with an O ₂ film and is used as a part of the interlayer insulating film 5.
Then, a polycrystalline Si film is formed on the entire surface by, for example, a CVD method, and the polycrystalline Si film is doped with impurities by an ion implantation method or a thermal diffusion method to reduce the resistance.
The film is patterned into a predetermined shape by etching. As a result, the word line 6 is formed as shown in FIG.

From the above, the desired DINOR virtual ground array type flash EEP
The ROM is manufactured.

As described above, according to the first embodiment,
The gate insulating film 2 in a portion of the floating gate 3 where one end 3a on the side where electrons are not extracted at the time of writing data and the n ⁺ type diffusion layer 4 overlap is formed thicker than other portions. Therefore, when writing data, it is possible to suppress the extraction of electrons due to the FN tunneling between the one end 3a and the n ⁺ type diffusion layer 4, and the other end 3b of the floating gate 3 and the other end 3b. Electrons can be extracted by FN tunneling only between the other end 3b and the overlapping n ⁺ type diffusion layer 4. This makes it possible to prevent the data in the memory cells adjacent to the memory cell from being destroyed when writing data to the memory cell. Further, the n ⁺ type diffusion layers 4 provided in the p-type Si substrate 1 on both sides of the floating gate 3 are not offset from the floating gate 3 and both overlap with the floating gate 3. A sufficiently large read current can be secured when reading data.

Next, a stack gate type DINOR type flash EEPROM according to a second embodiment of the present invention.
Will be described.

FIG. 6 is a plan view of a stack gate type DINOR flash EEPROM according to the second embodiment, and FIG. 7 is an enlarged sectional view taken along line VII-VII of FIG.

As shown in FIGS. 6 and 7, in the stack gate type DINOR flash EEPROM according to the second embodiment, a field insulating film 22 such as a SiO ₂ film is formed on the surface of the p type Si substrate 21. It is selectively provided, and thereby element isolation is performed. P in a predetermined portion surrounded by the field insulating film 22
A floating gate 24 is provided on the type Si substrate 21 via a gate insulating film 23 such as a SiO ₂ film. Here, the gate insulating film 23 is made of a SiO ₂ film, and the floating gate 24 is made of, for example, a polycrystalline Si film with a thickness of about 100 nm doped with an n-type impurity or a p-type impurity.

A word line 26 as a control gate is further provided on the floating gate 24 via an interlayer insulating film (coupling insulating film) 25. Reference numerals 27 and 28 denote n ⁺ -type diffusion layers provided in the p-type Si substrate 21 in a predetermined portion surrounded by the field insulating film 22 in a self-aligned manner with respect to the floating gate 24 and the word line 26. These n ⁺ type diffusion layers 27 and 28 are used as a source region and a drain region, respectively. Here, these n ⁺ type diffusion layers 2
One end of each of the reference numerals 7 and 28 overlaps with the floating gate 24 (in FIG. 6, this overlapped portion of one memory cell is indicated by stippling).

Reference numeral 29 is an interlayer insulating film such as a SiO ₂ film, and 30 is used as a drain region.
A contact hole for contacting a bit line (not shown) to the ⁺ type diffusion layer 28 is shown.

In the second embodiment, a portion 24a in the extending direction of the word line 26 of one end portion of the floating gate 24 which overlaps the n ⁺ type diffusion layer 28 is rounded, and this portion 24a is formed. The gate insulating film 23 in is formed thicker than other portions. Reference numeral 23a indicates this thickly formed portion of the gate insulating film 23 (in FIG. 6, this portion 23a is shaded). The thickness of the portion of the gate insulating film 23 excluding the thickly formed portion is set to a thickness that allows FN tunneling of electrons, for example, about 10 nm. In addition,
Reference numeral 26 a indicates a rounded one end of the word line 26, similarly to the rounded one end 24 a of the floating gate 24.

In the stack gate type DINOR type flash EEPROM according to the second embodiment, data writing and erasing are performed in the same manner as the above-mentioned conventional stack gate type DINOR type flash EEPROM. That is, when writing data, n as the drain region of the memory cell to be written is
For example, about +5 V is applied to the ⁺ type diffusion layer 28, about -8 V is applied to the word line 26 as the control gate, the substrate is OV, and the n ⁺ type diffusion layer 27 as the source region is opened to float the memory cell. The electron in the gate 24 is extracted by F-N tunneling to the n ⁺ type diffusion layer 28 as the drain region.
On the other hand, erasing of data is performed by applying to the word line 26 for example about + 10V as a control gate, applying, for example, about -8V the n ⁺ -type diffusion layer 27 as a substrate and source region, also serving as a drain region n ⁺ This is performed for all memory cells or blocks by injecting electrons from the p-type Si substrate 21 to the floating gate 24 with the type diffusion layer 28 opened.

Next, a method of manufacturing the stack gate type DINOR flash EEPROM according to the second embodiment having the above-described structure will be described.

As shown in FIGS. 6 and 8, first, the surface of the p-type Si substrate 21 is selectively thermally oxidized by, for example, the LOCOS method to form the field insulating film 22, thereby performing element isolation. Then, the surface of the p-type Si substrate 21 in a predetermined portion surrounded by the field insulating film 22 is thermally oxidized to form the gate insulating film 23. Next, a polycrystalline Si film is formed on the entire surface by, for example, the CVD method, and then the polycrystalline Si film is doped with impurities by, for example, an ion implantation method or a thermal diffusion method to reduce the resistance. Then, for example, CVD
An interlayer insulating film 25 such as a SiO ₂ film is formed on the entire surface by the method. Next, polycrystalline Si is formed on the entire surface by, for example, the CVD method.
After forming the film, the polycrystalline Si film is doped with impurities by, for example, an ion implantation method or a thermal diffusion method to reduce the resistance.
Next, a resist pattern (not shown) having a shape corresponding to the word line 26 is formed on the polycrystalline Si film by a lithography method, and then the polycrystalline Si film and the interlayer insulating film 25 are used as a mask. Then, the lower-layer polycrystalline Si film is sequentially patterned into a predetermined shape by etching. As a result, the floating gate 24 and the word line 26 are formed.

Next, after removing the resist pattern, the word line 26 and the floating gate 24 are used as masks in the p-type Si substrate 21 to form n such as As.
Type impurities are ion-implanted. Then, a heat treatment for electrically activating the implanted impurities is performed if necessary. As a result, in the p-type Si substrate 21 on both sides of the word line 26 and the floating gate 24, the one end of the floating gate 24 is self-aligned with the word line 26 and the floating gate 24.
The n ⁺ type diffusion layers 27 and 28 are formed so as to overlap with.

Next, as shown in FIG. 9, an interlayer insulating film 29 such as a SiO ₂ film and a Si ₃ N ₄ film 31 are sequentially formed on the entire surface by, eg, CVD method. Where Si ₃ N ₄
The thickness of the film 31 is, for example, about 100 nm.

Next, as shown in FIG. 10 and FIG.
The floating gate 24 and n are formed on the Si ₃ N ₄ film 31.
^The opening 3 including a part of the portion where the ⁺ type diffusion layer 28 overlaps
After the resist pattern 32 having 2a is formed by the lithography method, the Si ₃ N ₄ film 31 is etched in the direction perpendicular to the substrate surface by an anisotropic etching method such as the RIE method using the resist pattern 32 as a mask. The portion of the Si ₃ N ₄ film 31 not covered by the pattern 32 is removed.

Next, after removing the resist pattern 32, thermal oxidation is performed using the Si ₃ N ₄ film 31 as an oxidation mask. As a result, as shown in FIG. 12, one end portion 24a of the floating gate 24 not covered with the Si ₃ N ₄ film 31 is selectively thermally oxidized and rounded, and the gate insulating film 23 at the one end portion 24a is covered with the gate insulating film 23. The thickness is increased compared to other parts. At this time, the Si ₃ N ₄ film 3
One end 26a of the word line 26 not covered with 1 is also selectively thermally oxidized and rounded. This thermal oxidation is performed by, for example, a wet oxidation method, and the oxidation temperature is, eg, about 850 ° C. The oxidation time is determined by the shape of the one end 24a of the floating gate 24, device characteristics, and the like.

From the above, the objective DINOR type virtual ground array type flash EEP
The ROM is manufactured.

As described above, according to the second embodiment,
A portion 23a of the gate insulating film 23 in the extending direction of the word line 26 in the portion where the floating gate 24 and the n ⁺ type diffusion layer 28 on the side where electrons are extracted at the time of writing data overlap each other compared to other portions. And the gate insulating film 23 is formed in a portion where the floating gate 24 and the n ⁺ type diffusion layer 28 overlap each other.
The portion other than this portion 23a has a thickness capable of F-N tunneling of electrons. Therefore, when writing data, the electrons in the floating gate 24
Since only the thin portion of the gate insulating film 23 is extracted by the F-N tunneling to the n ⁺ -type diffusion layer 28 as the drain region, the F-
The area of the region where N tunneling occurs becomes small. As a result, the capacitance C _D between the floating gate 24 and the n ⁺ type diffusion layer 28 as the drain region can be effectively reduced. Therefore, when the voltage V _D applied to the n ⁺ type diffusion layer 28 at the time of writing is constant, the writing efficiency can be improved as compared with the conventional case, and thus the writing speed can be improved. Alternatively, the writing voltage can be reduced.

Further, at the time of writing, since a high electric field is applied only to a portion of the gate insulating film 23 where the floating gate 24 and the n ⁺ type diffusion layer 28 overlap each other with a small thickness, a band-to-band tunneling is caused. N ⁺ type diffusion layer 28 as a drain region and p type Si substrate 2
The leak current flowing between 1 and 1 is smaller than that in the conventional case.

The embodiments of the present invention have been specifically described above, but the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the above-mentioned first embodiment, D
The case where the present invention is applied to an INOR type virtual ground array type flash EEPROM has been described. The present invention, however, is a virtual ground array type in which writing is performed by extracting electrons in the floating gate to the diffusion layer. Type flash EE
It can be applied to all PROMs, and DINOR
It is not limited to the system type.

Similarly, in the above-described second embodiment, the stacked gate type DINOR flash EEPR is used.
The case where the present invention is applied to the OM has been described, but the present invention is a flash EE in which writing is performed by drawing out electrons in the floating gate to the diffusion layer.
It can be applied to all PROMs, and DINOR
It is not limited to the system type.

[0069]

As described above, according to the present invention,
It is possible to prevent the destruction of the data held in the memory cell adjacent to the memory cell to be written at the time of writing the data while ensuring a sufficient read current at the time of reading the data, or to improve the write efficiency. It is possible to realize a non-volatile semiconductor memory device which can be improved or the write voltage can be lowered and which has low power consumption.

[Brief description of drawings]

FIG. 1 is a DINOR virtual ground array flash EEP according to a first embodiment of the present invention.
It is sectional drawing which shows ROM.

FIG. 2 is a DINOR type virtual ground array type flash EEP according to the first embodiment of the present invention;
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the ROM.

FIG. 3 is a DINOR type virtual ground array type flash EEP according to the first embodiment of the present invention;
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the ROM.

FIG. 4 is a DINOR type virtual ground array type flash EEP according to the first embodiment of the present invention;
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the ROM.

FIG. 5 is a DINOR type virtual ground array type flash EEP according to the first embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the ROM.

FIG. 6 is a plan view showing a stack gate type DINOR type flash EEPROM according to a second embodiment of the present invention.

FIG. 7 is an enlarged cross-sectional view taken along the line VII-VII of FIG.

FIG. 8 is a cross-sectional view for explaining the method of manufacturing the stack gate type DINOR flash EEPROM according to the second embodiment of the present invention.

FIG. 9 is a cross-sectional view for explaining the method of manufacturing the stack gate type DINOR flash EEPROM according to the second embodiment of the present invention.

FIG. 10 is a cross-sectional view for explaining the method of manufacturing the stack gate type DINOR flash EEPROM according to the second embodiment of the present invention.

FIG. 11 is a plan view for explaining a method of manufacturing a stack gate type DINOR flash EEPROM according to the second embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining the method for manufacturing the stack gate type DINOR flash EEPROM according to the second embodiment of the present invention.

FIG. 13 is an equivalent circuit diagram of a conventional DINOR virtual ground array type flash EEPROM.

FIG. 14 is a cross-sectional view of a main part of a conventional DINOR virtual ground array type flash EEPROM.

FIG. 15 is a plan view showing a conventional stack gate type DINOR type flash EEPROM.

16 is an enlarged cross-sectional view taken along line XVI-XVI of FIG.

FIG. 17 is a cross-sectional view for explaining a writing method of a conventional stack gate type DINOR type flash EEPROM.

FIG. 18 is a sectional view for explaining a reading method of a conventional stack gate type DINOR type flash EEPROM.

FIG. 19 is a schematic diagram showing capacitors formed in respective parts of a conventional stack gate type DINOR flash EEPROM.

[Explanation of symbols]

1, 21 p-type Si substrate 2, 23 gate insulating film 3, 24 floating gate 4, 27, 28 n ⁺ type diffusion layer 5, 25, 29 interlayer insulating film 6, 26 word line 7, 31 Si ₃ N ₄ film 8 , 32 resist pattern 22 field insulating film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/115 27/10 471

Claims (15)

[Claims] 1. A floating gate provided on a semiconductor substrate via a gate insulating film, and one end of the floating gate overlaps with the floating gate, and the floating gate is provided in the semiconductor substrate on both sides of the floating gate. In the nonvolatile semiconductor memory device having a diffusion layer, at least a part of the gate insulating film in a portion where the floating gate and one of the diffusion layers overlap each other is formed thicker than other portions. A characteristic non-volatile semiconductor memory device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein writing is performed by extracting electrons in the floating gate to the other diffusion layer or the one diffusion layer. 3. The non-volatile according to claim 1, wherein the entire gate insulating film in a portion where the floating gate and the one diffusion layer overlap each other is thicker than other portions. Semiconductor memory device. 4. The part of the gate insulating film in a portion where the floating gate and the one diffusion layer overlap each other is formed thicker than other portions. Nonvolatile semiconductor memory device. 5. The nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor substrate is made of silicon, the gate insulating film is made of silicon dioxide, and the floating gate is made of polycrystalline silicon. 6. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is a virtual ground array type flash EEPROM. 7. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is a split bit line NOR type flash EEPROM. 8. A floating gate provided on a semiconductor substrate with a gate insulating film interposed between the floating gate and the floating gate, wherein one end of the floating gate overlaps with the floating gate. A method for manufacturing a nonvolatile semiconductor memory device having a diffusion layer, wherein the gate insulating film and the semiconductor film are sequentially formed on the semiconductor substrate, and then the semiconductor film is patterned to form the floating gate. A step of increasing the thickness of the gate insulating film in at least a part of one end of the floating gate by selectively insulating the floating gate, and using the floating gate as a mask in the semiconductor substrate. A process for forming the diffusion layer by introducing impurities. Method of manufacturing a nonvolatile semiconductor memory device characterized by having and. 9. The method of manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein the entire one end of the floating gate is selectively made into an insulator. 10. The method of manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein a part of the one end of the floating gate is selectively made into an insulator. 11. The method for manufacturing a nonvolatile semiconductor memory device according to claim 9, wherein the entire one end of the floating gate is selectively oxidized to become an insulator. . 12. The non-volatile semiconductor memory device according to claim 10, wherein a part of the one end of the floating gate is selectively oxidized to become an insulator. Method. 13. The semiconductor substrate is made of silicon,
9. The method for manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein the gate insulating film is made of silicon dioxide, and the semiconductor film is made of polycrystalline silicon. 14. The non-volatile semiconductor memory device is a virtual ground array type flash EEPROM.
9. The method for manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein: 15. The method of manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein the nonvolatile semiconductor memory device is a split bit line NOR type flash EEPROM.