JPH0818563A - Exchange - Google Patents

Abstract

PURPOSE:To considerably improve the processing efficiency of software processing by processing data while a processing unit such as physical layer processing is in matching with a data width of a processor mounted on an exchange. CONSTITUTION:A receiver side FIFO 2701 provides an output of received serial data in the unit of n-bits being a data width of a CPU 2703. The CPU 2703 reads data in n-bit width from the receiver FIFO 2701 and applies prescribed processing to the data. On the other hand, the CPU converts the data in n-bit width outputted from the transmitter side into serial data and provides an output. The physical layer processing in the CPU 2703 is more efficient than the case of serial or 8-bit parallel processing having been executed in a conventional hardware by forming a width of data sent/received between the FIFO 2701, 2702 and the CPU 2703 to be equal to a data width (n) read/written at once by the CPU 2703 in this way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching device, and more particularly, it accommodates a plurality of interface points and transfers an ATM cell input from an input port of each interface point to an output port of a desired interface point according to its header information. It relates to a switching device for transferring.

[0002]

2. Description of the Related Art Conventionally, ATM (Asynchronous Transfer Mode) technology has been attracting attention as a technology aiming at speeding up of transmission / switching technology. The ATM is a technology aiming at hardware implementation of packet switching by transferring all information in fixed length and short packets called cells and facilitating high speed information transmission / exchange. In order to realize an ATM communication network that performs information communication using this method, a switching device that transfers cells from a certain transmission line to a desired transmission line according to the header information of the cell is essential.

However, the conventional exchange apparatus has the following problems. The ATM communication network basically provides the information transfer function of the ATM layer with hardware. Functions implemented by hardware generally have high throughput, but are costly. Even in the conventional switching device, the ATM layer function is realized by hardware, resulting in high cost. In particular, ATM-
This is an unbearable cost for a switching device used in a communication system for the purpose of providing information transfer capability by ATM cells to terminals existing in a relatively narrow range, which has recently been drawing attention as a LAN. In addition, in the case of a hardwareized function, it is necessary to recreate the hardware even when the function is slightly changed, and there is a problem that it lacks flexibility.

In order to solve such a problem, it is considered that the function of the exchange apparatus is realized by software. In that case, how to suppress the decrease in throughput becomes a big problem.

Further, when considering software processing, the processing time varies depending on the given information. In the ATM switching apparatus that must input and output information at a predetermined speed from the interface point, how to absorb the fluctuation of the processing time is a big problem.

As means for solving the above problems,
A method of performing the processing by software can be considered. In such a switching device, the physical layer processing is executed on a register inside the processor to speed up the physical layer and ATM layer processing.

By the way, a processor whose performance has been remarkably improved in recent years and is well known as a RISC processor (for example, M
R3000) manufactured by IPS Co., Ltd. largely bears the speed improvement by having an instruction execution pipeline. By pipelining instruction execution, a plurality of instructions can be executed at the same time, and thus the number of executed instructions per clock approaches 1 as much as possible.

However, as is well known,
In order for the pipeline to operate without contradiction, it is desirable that the instructions included in the pipeline have no relationship between the data read and written. It is almost impossible for a human to directly write an assembler program having such a character, and as is well known, in order to make the most of the power of the RISC processor, it is written in a so-called high-level language such as C. An optimizing compiler for converting the created program into an assembler program having the above-mentioned character is essential.

In a switching device which performs the above-mentioned processing by software, it is possible to obtain high speed by using a register as an interface between the functions.
However, a general C compiler does not have a method of explicitly specifying registers in order to make the program independent of the processor architecture. That is,
In the case of the above-mentioned exchange device, there is a problem that the developer needs to write a program in the assembler, which deteriorates the development efficiency.

Furthermore, the current frame structure and cell structure are not made in consideration of the data width of recent high-performance microprocessors such as 32 bit width and 64 bit width. In the switching device disclosed in the above patent, the ATM
In the cell exchange process, the internal cell structure was designed with 32 bit width and 64 bit width taken into consideration, but the internal data structure in the physical layer process, the frame synchronization process and the cell synchronization process follows the current one. It was As a result, there is also a problem that the efficiency of copying frames or cells from the main memory to the register is deteriorated when performing frame synchronization processing or cell synchronization processing.

[0011]

As described above,
In a switching device that performs processing by software, high speed performance was achieved by using a register, so that the descriptiveness in a high-level language such as C and the independence from the processor architecture were low, and the development efficiency was poor. was there. Furthermore, in a switching device that performs processing by software, the frame structure and the cell structure are 32 bits or 64 bits.
As a result of not being aware of the data width of recent high-performance processors such as bit, there is a problem that the data transfer between the memory and the register is inefficient.

The present invention has been made in view of the above-mentioned problems, and in an exchange device which performs processing by software, data exchange between a exchange device and a memory and a register in a CUP in which programming in C language is easy. It is an object of the present invention to provide a switching device that is efficient.

[0013]

According to the present invention, in a switching device, a function by software processing (particularly a physical layer processing function) is implemented in a form matched with a data width of a processor.

That is, the present invention performs an exchange process of outputting an ATM cell input from each of a plurality of reception lines to any of a plurality of transmission lines based on the destination information added to the information, and the exchange processing. In a switching device that performs at least a part of the processing by causing a processor to execute a predetermined program, a data unit that can process the information in the processing that is executed by using the processor in the switching processing is It is characterized in that the data width that can be processed is set.

Preferably, the processing executed by using the processor in the exchange processing includes at least one of bit synchronization processing, frame creation processing, cell synchronization processing, HEC creation processing, scramble processing and descrambling. Is characterized by.

Further, the present invention performs an exchange process of outputting an ATM cell input from each of a plurality of reception lines to any one of a plurality of transmission lines based on destination information added to the information, and the exchange processing. In a switching device for performing at least a part of processing by causing a processor to execute a predetermined program, A from the receiving line
First data width conversion means provided in each of the reception lines and converting the serial data forming the TM cell into parallel data having a data width that can be processed by the processor, and the data width conversion means A first processing unit for receiving the parallel data from the data width converting means, and causing the processor to execute a predetermined program to perform the physical layer processing on the receiving side and the ATM layer processing on the receiving side for the parallel data; A first processing means, and a switch means for exchanging information from the first processing means and outputting the information to any one of a plurality of output terminals.
A second physical layer processing and a transmission ATM layer processing for the information from the switching means by causing the processor or a processor provided separately at each of the output terminals to execute a predetermined program. A processing means and the second processing means, respectively.
And a second data width conversion means for converting the information from the second means into serial data and outputting the serial data to the accommodated transmission line.

Preferably, each of the first data width conversion means is a clock extraction means for extracting a clock signal from given serial data, and the serial data is converted into parallel data according to the extracted clock signal. It is characterized by comprising serial-parallel conversion means for converting and outputting.

Further, preferably, each of the second data width conversion means is means for generating information indicating an effective bit width of parallel data, and based on this information, the parallel data is converted into serial data. It is characterized in that it comprises a parallel-serial conversion means for outputting the same.

On the other hand, the present invention is realized by exclusively controlling and managing the right of use of the common memory between the functional processes of the plurality of physical layer processing functions and the plurality of ATM layer processing functions.

That is, the present invention performs an exchange process for outputting an ATM cell input from each of a plurality of reception lines to any one of a plurality of transmission lines based on the destination information added to the information, and the exchange processing. The processing is composed of a plurality of processings, and in a switching device that performs at least two or more processings of the plurality of processings by causing a processor to execute a predetermined program, the processings are performed when the respective two or more processings are executed. Common information storage means for storing target common information, and access control means for performing control to selectively give a usage right for accessing the common information storage means to each of the two or more processes. It is characterized by having.

Further, the present invention performs an exchange process for outputting an ATM cell input from each of a plurality of reception lines to any one of a plurality of transmission lines based on destination information added to the information, and the exchange processing. A process is composed of a plurality of processes, and in a switching device that performs at least two or more processes of the plurality of processes by causing a processor to execute a predetermined program, the processor executes the physical layer process. The AT using the physical layer processing means and the same processor as the processor used by the physical layer processing means or a processor provided separately.
ATM layer processing means for executing M layer processing, common information storage means for storing common information to be processed by both the physical layer processing means and the ATM layer processing means, the physical layer processing means, and The A
Access control means for controlling the TM layer processing means to selectively give a use right for accessing the common information storage means.

Further, preferably, the access control means gives the use right by giving a pointer indicating a position in the common information storage means in which the information is stored.

[0023]

According to the present invention, various processings (especially physical layer processings) required for the exchange function up to now are processed in bit units, which are processing units by conventional hardware, or in byte units at most. Then, the software processing efficiency did not increase so much. That is, a high-performance processor that is supposed to be used in a switching device by software processing usually has a data width of 32 bits or 64 bits, whereas the physical layer processing is performed in byte units. is there.

In software processing, the time for processing such as reading data from a memory and writing it in a register occupies most of the overall processing efficiency. Therefore, the data processing width is set to the data width of the processor as in the present invention. By thinking about programming so that it fits well,
The software processing efficiency of the physical layer is dramatically improved.

For example, the process of calculating the cell header is
In hardware, for example, a header is fetched in bit units or byte units, division is performed, and 1 byte of the result is stored, and the like processing is repeated. The number of repetitions is 40 in the bit unit and 5 in the byte unit. If this process is implemented by software as it is, even if it is processed in byte units, it takes 5 times to read the data from the memory and 5 times to store the result. It occupies more than half of the amount. However, if this is processed by a 32-bit processor and data of 32 bits is read at one time and a processing program is created in accordance with it, the number of times of reading can be reduced to two. With a 64-bit processor, the processing up to the point where the calculation result is created by one reading is possible by using a program suitable for it.

As described above, when at least a part of various processes (especially physical layer process) necessary for the exchange function is matched with the data width of the processor, there is an advantage that the processing efficiency is improved.

Further, according to the present invention, when a plurality of software programs are simultaneously operating in order to perform one exchange process, the plurality of software programs are:
Share the same memory.

Of these, for example, if the cell data has a separate memory or memory area for each processing program, the efficiency becomes poor due to useless processing for transferring it. Therefore, it is necessary to use the one placed in the same memory, but if there is a state where multiple programs are processed at the same time, there is a data conflict between those processes, so Disturbance of pipeline processing occurs in the above, which causes a decrease in processing speed.

Therefore, as in the present invention, for example, by using a pointer, one program can occupy cells that can be processed between programs or other data, so that the processing can be pipelined. The processing efficiency is improved.

For example, it is general that the same memory is shared by the physical layer and the ATM layer in the processing of the communication path on the receiving side. Regarding the cell data written in the memory, the physical layer has a process for confirming whether the cell header is correct, while the ATM layer has a process for referring to the switching table from the header. is there. When the physical layer program and the ATM layer program exist independently as described above, the same cell header portion may be accessed at the same time. Use a pointer to prevent this,
In this example, since it is the receiving side, the access right is given to the physical layer program first, cell data is first written in the area, and the physical layer processing is performed on the cell of the written portion. Then, when the physical layer processing is completed, a processing of passing the pointer of the access right to the ATM layer is performed. When the ATM layer finishes processing, it returns to the physical layer and a new cell can be written therein.

Not limited to the case of the ATM layer processing and the physical layer processing as described above, depending on the configuration, for example, a memory may be shared among a plurality of ATM layer processings. In such a case, by exclusively controlling the access right to the memory by using the pointer, memory conflict does not occur, and the pipeline processing is not disturbed by the exclusive control on the program execution. Even a program in a high level language such as can execute the exchange process efficiently.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 1, the exchange apparatus of this embodiment includes a receiving side input section 1a, a receiving side physical layer processing section 2, and a receiving side AT.
A receiving side interface section including an M layer processing section 3 and a receiving side output section 1b, and a transmitting side including a transmitting side input section 7a, a transmitting side ATM layer processing section 5, a transmitting side physical layer processing section 6, and a transmitting side output section 7b. A plurality of interface units are connected to the input side and the output side of the switch unit 4, respectively.

As shown in FIG. 2, the exchange apparatus is provided with a processor (hereinafter abbreviated as CPU) 11, and each of the above-mentioned processing units which are easily stored in the program storage unit 13 in advance will be described later. The CPU 11 executes the program 14 corresponding to each function. Communication information input from the outside and information necessary for exchange processing are stored in the main memory 12 and the cache memory 16 of FIG. 2 as needed, and each function (process) provided by the program is stored in the main memory 12. Also, the processing is executed while accessing the cache memory 16 and the transmission / reception FIFO (not shown). The program is loaded from the program storage unit 13 into the main memory 12 in advance before its execution.

The receiving side input unit 1a, the receiving side output unit 1b, the transmitting side input unit 7a, and the transmitting side output unit 7b are assumed to be realized by hardware, and the respective processes executed by the other processing units are Although it is supposed to be realized by software, it may be realized by hardware as necessary for each process.

In the present embodiment, it is assumed that the switch section 4 is a hardware-configured switch that reads cell data in a fixed time cycle. Hereinafter, this switch section 4 will be described as an ATM switch 4. However,
Instead of the ATM switch, it is also possible to adopt a method in which the switch process is also realized by software as a process integrated with the receiving side communication channel process described later.

First, with reference to FIG. 3, what kind of processing is performed by the exchange apparatus of this embodiment until the received data is transmitted will be roughly described along the flow.

FIG. 3 is a diagram showing a flow of processing in each receiving side interface section and each transmitting side interface section in the exchange apparatus of this embodiment. The processing executed by this exchange is the communication path process 101 and the OAM (Ope).
(Ration And Maintenance) process 102.

The call path process 101 is further composed of two processes. That is, data from the receiving side line is received via the receiving side input section 1a, physical layer processing and ATM layer processing are sequentially performed on this, and output to the ATM switch 4 via the receiving side output section 1b. And the data from the ATM switch 4 is received via the input unit 7a on the transmission side, and ATM layer processing and physical layer processing are sequentially performed on the process and the line on the transmission side is output via the output unit 7b on the transmission side. It is a transmission side channel process output to.

The outline of the processing of the reception side channel process is as follows. At the receiving side input section 1a, a network clock is extracted from the received signal, bit synchronization is performed, and the signal is converted into a data string in bit representation. It is assumed that the processing up to this point is realized by hardware rather than software.

Line decoding 1 from this bit string
An ATM cell is extracted by receiving physical layer processing such as 21, frame synchronization 122, cell synchronization 123, and descrambling 124 of the cell payload portion. Then ATM
As layer processing, header conversion 125, routing tag addition 126 for intra-switch routing, and flow rate monitoring (policing) 127 are performed, and cells are sent to the ATM cell switch 4 via the reception side output unit 1b.

On the other hand, the outline of the processing of the transmission side call path process is as follows. On the transmission side, the cells exchange-processed by the ATM switch 4 are passed to the transmission side speech path process via the transmission side input unit 7a. This cell data contains A
Flow rate monitoring (shaping) 13 as TM layer processing
7. Routing tag deletion 136 and header conversion 135 are performed. Further, as physical layer processing, scrambling 134 of the cell payload portion and HEC (Header Error Control) of the cell header are added to this data.
l) Field generation 133, frame creation 132, and line encoding 131 are performed, and the transmission side output unit 7
Bit data is sent to the transmission side line via b.

Next, the processing of the OAM process will be described. The data input / output between the transmission / reception line and this switching apparatus includes OAM data in addition to user data. User data is handled in each of the above call path processes, but OAM
For data, a dedicated process for OAM data is prepared.

The OAM data is OH on the transmission frame.
It is divided into physical layer OAM information transmitted using bytes in the (overhead) portion and ATM layer OAM information transmitted in the form of OAM cells in the frame payload. The OAM information of the physical layer is the O of the physical layer / ATM layer such as abnormality detected in the switching device.
The AM information is passed to another process (hereinafter referred to as an OAM process) that processes the OAM data through the supervisory control interface 114 as it is or after performing statistical processing such as addition. On the other hand, OAM
In general, cells are defined for performance management, fault management, activation / deactivation, and loopback.
From the value written in the header, it can be determined whether or not the cell should be terminated in the switching device. Therefore, the OAM cell dropping / inserting unit 113 of the ATM layer looks at the value of the cell header, and if it is an OAM cell to be dropped, it is passed to the supervisory control processing unit 141 of the OAM process. In addition, OAM cells that should not be branched are passed through the switching device in the same manner as normal user data.

It is necessary for the OAM cell to analyze the detailed information by looking at the payload portion, and normally, the communication path processing does not perform such a complicated operation. The cell payload is passed as it is, and detailed processing is performed in the supervisory control processing 141 in the OAM process. In addition, the switching device is also required to perform processing such as updating the routing tag table by changing the connection state and notifying the statistical information generated in the communication path processing to the outside. These processes are also performed by the OAM process. That is, the OAM process sets the routing tag, and the speech path process looks at it and performs cell header conversion. The data output from the OAM cell is incorporated in the transmission frame in the OH portion of the frame for the physical layer and in the form of the OAM cell for the ATM layer and transmitted to the outside.

The message sending unit 142 and the message receiving unit 143 are parts having an interface function for communicating with higher-level functions. here,
FIFO of CPU and receiving side input section 1a, transmitting side output section 7
FIG. 4 shows an example of a rough hardware configuration showing a data flow with the FIFO of b.

In the reception side FIFO 2701, the received serial data is transferred to the CPU 2703 having a data width n.
Output in bit units. In the CPU 2703, the receiving side F
Data having an n-bit width is read from the IFO 2701, and the data is subjected to predetermined processing.

On the other hand, in the output processing on the transmission side, the transmission-side FIFO 2702 converts the n-bit wide data output by the CPU 2703 into serial data and outputs the serial data. In this way, each FIFO 2701, 2702 and CP
The width of the data exchanged with U2703 is set to CP
By configuring the U2703 to be equal to the data width n that can be read and written at one time, as shown below, the physical layer processing in the CPU 2703 is more efficient than the case of serial or 8-bit parallel that was implemented in conventional hardware. Will also be efficient.

2 and 4, it is written that the entire CPU is shared for transmission and reception, but this is merely an example, and various configurations such as providing a CPU for each transmission and reception are conceivable.

Next, ITU-TS Recommendation I. The cell according to ITU-TS Recommendation G.432 is used. 804 according to TTC standard JT-G. Each program for processing these speech path processes for the data mapped to the frame 703-a will be described in detail separately for the reception side speech path process and the transmission side speech path process. Note that each program is preferably written in a high-level language such as C.

First, the respective subroutines constituting the reception side speech path process and their details will be described. (Regarding sub-routine division) When performing multiple processes on data with software, it is not possible to perform those processes at the same time, so divide the data into appropriate sizes and assign multiple data to one. A method is considered in which the processes are sequentially performed, and when the series of processes is completed, the processes are performed again on the next data. The flow of each subroutine that is sequentially performed on a certain data block and the flow of data at that time and information such as pointers and valid cells will be described below with reference to FIG. In FIG. 5, thick arrows indicate the flow of data, and thin arrows marked P indicate the flow of pointers.

First, in the reception side input section 1a, the reception data converted into a data string of bit representation and accumulated in the reception side input FIFO (not shown) is a fixed amount of data set by the reception data input subroutine 203. Then, it is written in the frame data accommodating buffer 209 on the memory inside the CPU 11. This subroutine 203 is
A pointer indicating where in the memory the data has been written is passed to the next frame synchronization subroutine 204.

The frame synchronization subroutine 204 received from the data input subroutine 203 reads and processes only the necessary portion of the data in the frame data accommodation buffer 209. That is, in the state where the frame synchronization is not obtained at all, all the data are sequentially read from the beginning of the data and inspected, and after the frame synchronization is established, only the frame synchronization bit portion is read and the confirmation is performed. The position information of the frame synchronization bit obtained by the frame synchronization is passed to the next cell synchronization subroutine 205.

The cell synchronization subroutine 205, based on the information received from the frame synchronization subroutine 204,
Again, only the necessary portion of the data in the frame data accommodating buffer 209 is read and the procedure such as cell synchronization is performed. In other words, when the cell synchronization is not achieved, the cell data part in the data is read in order from the beginning to search the cell header, and after the cell synchronization is established, only the cell header part is read and the error Detect and correct. Further, after the cell synchronization is established, the read data is written in the cell header accommodating buffer 210 in which the first 4 bytes of the header are combined into one word and only the cell header on the memory is newly collected.

Following the cell synchronization subroutine 204 are two subroutines, descramble and ATM layer processing. Information such as the number of cells in the data in the frame data accommodating buffer 209, the start position, and their validity / invalidity is passed from the cell synchronization subroutine 204 to the descramble subroutine 206, and the descrambling subroutine 206 is stored in the frame data accommodating buffer 209 based on the information. Read the payload part of the cell. The read data is descrambled, and the descrambled data is written in the cell payload accommodating buffer 212 for each cell.

On the other hand, the ATM layer subroutine 207 is provided with information on the position of the header accommodating buffer and the number of headers accommodated, and the cell header on the header accommodating buffer 210 is read based on this information. The read header is subjected to policing, routing tag addition, header rewriting, etc., and a new header is written in the header accommodating buffer 211 with a routing tag.

These two subroutines 206, 20
The position of the cell payload or the position of the header with the routing tag is passed from 7 to the final reception data output subroutine 208, and based on this, the data output subroutine 2
At 08, the cell data is combined and output.

By adopting such a subroutine structure, it is not necessary to transfer useless data between the respective subroutines, and it is possible to reduce the number of times data is loaded and stored, which imposes a heavy load on the CPU, and high speed is achieved. Can be realized.

Further, by making the respective sub-routines separate and independent so that data is transferred to a pointer or the like in another memory, each sub-routine can be easily replaced by hardware.
For example, it is possible to relatively freely select a combination such that hardware is used up to frame synchronization and subsequent processing is performed by software, or processing up to descrambling is performed by hardware.

Next, each procedure and subroutine will be described in more detail. (Reception Side Input Section) FIG. 6 shows a reception side communication path data input section 1
It is a schematic block diagram which shows a.

First, the data inputted from the speech path is taken into an internal register (not shown) by using the clock extracted from the data itself by the clock extracting circuit 301, and further into the serial-parallel converter 302. Communication path input FIFO3 after serial-parallel conversion
It is stored in 03.

When a certain amount of data is accumulated in the speech path input FIFO 303, a signal is issued from the FIFO 303, and in response to this, the CPU 304 activates a data input subroutine (a subroutine for fetching data into the internal memory of the CPU 304). In the present embodiment, since it is assumed that a CPU with a data width of 32 bits is used, one word of data is taken in with a 32-bit width.

At this time, in order to facilitate the processing in the CPU 304, the timing for performing serial-parallel conversion is set from the CPU 304 to serial-parallel as shown in FIG.
It is sent to the parallel converter 302 to reflect the result of frame synchronization or the like. When the timing of serial-parallel conversion is designated from the CPU 304, the head of each frame of data having a frame length that is not a multiple of 32 bits, such as 789 bits, is always used by using the counter 305 by designating the number of bits and the like. It is also conceivable to perform serial-parallel conversion so that it comes at the beginning of a word.

On the other hand, there may be a method in which the timing of serial-parallel conversion is entirely left to the hardware and the CPU is not involved. The program shown in this embodiment is
It is created assuming that there is no designation from these CPUs.

(Received Data Input Subroutine 203) The TTC standard JT-G. In the frame structure 703-a, one frame can be synchronized with one multi-frame consisting of four 789-bit frames. Each process (each sub-routine) for the data received by the CPU is equivalent to the data for eight multiframes,
That is, data of 25,248 bits and 789 words is used as one unit (of course, this number may be another value). At this time, the amount of data to be loaded into the frame data accommodating buffer 209 at one time is set so that it can be confirmed even between data fetched by two frame synchronization signals in one multiframe.
Read next 789 so that the last bit of the cell containing the last bit of the 89 word can be read
814 with the top 25 words of word data added
It is a word. That is, as shown in FIG. 7, the input serial data is divided into 789 words, and 25 words of data are read while overlapping between the preceding and following data. Hereinafter, the 814-word data captured at one time is referred to as a data block.

The data input subroutine 203 writes this data block in the frame data accommodating buffer 209 and informs other subroutines of the position of the buffer.

(Frame Sync Subroutine 204) First, frame synchronization is performed on the data block fetched in the frame data accommodating buffer 209, and the frame bit, the position of the user information transfer area, and whether the frame is valid or not. To clarify. Some variables are defined so that the result of frame synchronization and other information can be used in the subroutine of cell synchronization to be performed next and frame synchronization for the next data block. The three variables are a frame synchronization status display variable, an effective frame start display variable, and a frame synchronization signal start display variable.

The frame synchronization status display variable represents the status of frame synchronization and the number of consecutive arrivals of frames having an erroneous frame bit depending on its value. If the value of the frame synchronization status display variable is -4, the frame is not synchronized at all, and if it is -3 to -1, three consecutive correct frame synchronization signals are confirmed to establish frame synchronization (value The absolute value of indicates the number of correct sync signals that need to be confirmed until a sync state is reached), and if 0 to 6 the frame sync is established (the value indicates an erroneous sync signal received continuously). It represents the number of frames you have).

The valid frame start display variable represents the start of a valid frame found by frame synchronization. Cell synchronization will be performed for data after this value. If this value is 0, all data are considered valid,
If the value is 26049, it is determined that all data are not valid.

The frame synchronization signal start display variable represents how far the frame synchronization signal is checked. When this value exceeds 25248, the value obtained by subtracting 25248 from that value is set as a new frame synchronization signal start display variable, End the synchronization subroutine. The rewritten frame synchronization signal display variable represents the point at which frame synchronization for the next data block should be started.

Next, the actual frame synchronization subroutine 2
04 will be described with reference to FIG. When a new data block is written in the frame data accommodating buffer, the last state of the frame synchronization state of the immediately previous data block is known from the value of the frame synchronization state display variable at this time. be able to.

When the value of the frame synchronization status display variable is -4, a search 2401 for a frame bit synchronization pattern for each new data is performed. That is, the data in the frame data accommodating buffer 209 is sequentially read word by word from the beginning, and the sync pattern of the frame bit is searched for the data.

When the synchronization pattern is correctly confirmed in two frame bits, 1 is set in the frame synchronization status display variable.
To move the search to the next multi-frame and enter the pre-sync processing state 2402 which confirms that there are two sync patterns at the corresponding positions. When this confirmation is performed, only necessary data in the frame data accommodation buffer 209 is read. And if the synchronization pattern is correct,
Further, 1 is added to the frame synchronization status display variable to confirm the synchronization pattern of the next multiframe. If an incorrect sync pattern is detected, the frame sync status display variable is set to -4 and the process returns to the bit-by-bit search 2401.

When the correct synchronization pattern is detected three times in a row and frame synchronization is established, the valid frame start display variable is set to the start bit of the frame, and the synchronization state 2403 is entered. At this time, the frame synchronization status display variable is 0.

In the sync state 2403, it is checked whether or not the correct sync pattern exists in the frame bits for all multiframes in the data. When an incorrect multi-frame is detected, 1 is added to the frame synchronization status display variable, while the frame synchronization status display variable is set to 0 whenever a correct frame comes. If the variable has reached 7, the variable is set to -4 again and the effective frame start display variable is set to 260 indicating the end of the frame.
The setting is set to 49, and the process returns to the frame pattern synchronization pattern search 2401 in bit units.

When these procedures are performed until the frame synchronization signal start display variable exceeds the 789th word of the data block, 25248 is subtracted from the value of the frame synchronization signal start display variable at that time (step 3000).
The frame synchronization subroutine 204 ends.

There are several possible methods for actually searching the frame bit synchronization pattern. For example, it is a method of checking the synchronization pattern divided into two at a time for each bit. Otherwise, the first frame synchronization pattern 1100 is searched bit by bit, and if the pattern is found, it is confirmed whether or not there is a second synchronization pattern 10100 after 789 bits. Is the way.

In the latter method, if the second synchronization pattern does not exist correctly, the bit immediately after the first synchronization pattern is searched again for a portion that matches the first synchronization pattern. In this method, a method of searching for the first synchronization pattern 1100 is also performed, for example, by directly comparing with 1100, and if they do not match, by shifting 1-bit data and performing comparison again, as shown in FIG. A method of examining the data bit by bit according to the state transition may be considered.
According to this method, since the search is performed independently for each bit, even if the synchronization pattern 1100 exists over two words, the search can be performed without any special processing, so that the processing can be simplified and therefore the high speed is achieved. Can be measured.

Further, since the search 2401 of the synchronization pattern for each bit in FIG. 8 is performed for all the bits of the input data,
This is a very heavy processing for the CPU. Therefore, it is expected that this process will rate limit the input data rate. Therefore, although it takes some time for the frame synchronization pull-in, it is possible to process the input data by performing the search for the synchronization pattern not for all input data in 1-bit units but for only a part of the data. A method to raise the rate is also possible.

As an example, the input data is divided into multi-frame sizes, and the sync pattern is applied to the first half of the data for the first multi-frame and the latter half of the second. , The synchronous pull-in time is doubled, but it is possible to double the input data rate and process even with the same CPU processing capacity.

Furthermore, once frame synchronization is established,
It is also conceivable to omit the confirmation of the frame synchronization after establishing the cell synchronization and entering the steady state, and to establish only the cell synchronization. This is because even if frame synchronization is not performed, it can be understood that the frame has arrived correctly because the cell synchronization is correct. At this time, when cell synchronization is lost,
It is necessary to start the frame synchronization process again and check whether the frame has arrived correctly.

In the conventional frame synchronization method realized by hardware, only bits of a necessary frame synchronization pattern (4 bits of "1100" in this embodiment) are fetched from bit serially input data and compared. What you do is common. Therefore, if this is realized as it is in software without changing the method, it is as follows.

First, only 4 bits are taken out from the input data stored in the buffer and it is checked whether it is "1100". If they match, the process moves to the search for the next multi-frame pattern "10100". If they do not match, the 4 bits searched for "1100" are shifted by 1 bit (that is, the lower 3 bits called from the previous memory). The next 1 bit (total 4 bits) will be searched for new 4 bits.

When this method is used, it is necessary to always read once from the FIFO outside the CPU each time one search is performed. Then, as shown in FIG. 10, for example, the number of times of reading 8-bit data is 5 because the data is read in units of 4 bits while shifting by 1 bit. This consumes a lot of CPU processing time and is not a good method.

However, as shown in FIG.
By reading in bits, it is possible to complete the data that was read 5 times in 1 time. It is possible to read once and perform 5 searches in 4-bit units while shifting it one bit at a time as described above. If the next read is performed so that it overlaps with the immediately preceding read by only 3 bits, the search can be performed without causing omission in the search. In the present embodiment, since a CPU having a data width of 32 bits is assumed, the maximum data width of 32 bits is set to 1
If it is read once, the number of times of reading becomes the smallest. Therefore, the software processing time required for reading can be significantly reduced.

Therefore, in the frame synchronization, if the data read width is set to the data width of the CPU, the number of data read times, which is the rate-determining step in software processing, can be reduced.

(Cell synchronization subroutine 205) By performing frame synchronization, it is possible to identify the cell information area in the data on the frame data accommodating buffer 209 and the synchronization of the cell data in byte units. Therefore, next, cell synchronization is performed on the data in the area in which the cell information exists, the position of the cell header and the position of the cell payload are clarified, and the error in the header part is corrected and detected.

Some variables are defined so that the result of cell synchronization and other information can be used in the descrambling to be performed next and the cell synchronization subroutine for the next data block. It is a cell synchronization state display variable, the number of synchronization cells, a synchronization cell start bit array, a cell start bit, an invalid cell display array, and the like.

The cell synchronization status display variable represents the cell synchronization status, the number of erroneous cell header arrivals, etc., as in the case of frame synchronization. If the value of the cell synchronization status display variable is -7, the cell is not synchronized at all (hunting state), and if it is -6 to -1, 6 consecutive correct cell headers are confirmed for cell synchronization. State (pre-synchronization state), 0 indicates that cell synchronization is established and header error correction mode, and 1 to 6 indicates that cell synchronization is established and header error detection mode. In the pre-synchronization state, the value of the cell synchronization state display variable represents the correct number of cells required until the synchronization state.In the synchronization state header error detection mode, the value of the cell synchronization state display variable is continuously observed. Represents the number of cells with a header.

The number of sync cells represents the total number of cells existing in the cell-synchronized portion of the data block, and the start bit of each cell is indicated by the sync cell start bit array. The cell start bit always represents the start bit of the target cell when performing cell synchronization. Cell synchronization is performed up to the cell including the last bit of the 789th word of the data block. That is, the cell synchronization subroutine ends when the cell start bit exceeds 25248. At this time, a value obtained by subtracting 25248 from the value of the last cell start bit is stored as a new cell start bit as the first bit of the cell in which cell synchronization in the next data block should be started.

The invalid cell display array indicates the number of the cell invalidated by the header error among the above-mentioned synchronization cells. The actual cell synchronization subroutine 205 is shown in FIG.
Follow along to explain.

A new frame data accommodating buffer 209
When the frame synchronization of the data block taken in is completed, the cell synchronization subroutine 205 is activated next. When the value of the effective frame start display variable from the frame synchronization subroutine 204 is 26049, it is determined that the data block does not include a valid frame (step 600a), and the cell synchronization subroutine 205 determines the cell synchronization state. The value of the display variable is set to -7 and the process ends.

If the value of the valid frame start display variable is 0, it can be determined that all the frames of this data block are valid (step 600b). Therefore, the last synchronization state display variable in the previous cell synchronization subroutine 205 is determined. The process starts from the state according to the value of.

When the previous cell synchronization subroutine 205 ends in the previous synchronization state 602 or the synchronization state 603, the data in accordance with the cell start bit from the previous cell synchronization subroutine 205 is read from the frame data accommodating buffer 209 and the data is read. Cell synchronization processing.

In the hunting state 601, data is read word by word from the beginning of a valid frame and the cell header is searched according to the byte synchronization given by the frame synchronization. When the value of the effective frame start display variable points to a frame in the middle of the data block, the process starts from the data of the frame by hunting. When the correct cell header portion is found in the hunting state 601, the value of the cell synchronization state display variable is set to -6 and the pre-synchronization state 602 is entered.

In the pre-synchronization state 602, the header is confirmed every cell cycle, and if the correct one can be confirmed, 1 is added to the cell synchronization state display variable, and if the wrong one is detected, the cell synchronization state display variable is set to -7. Set and change state to hunting state. When 6 correct headers are continuously confirmed and the cell synchronization status display variable becomes 0, the synchronization status error correction mode 603 is entered.

In the error correction mode 603 in the synchronous state, the cell header is confirmed according to the cell cycle, the value of the number of synchronous cells is incremented, and the start bit of the cell is set to the value of the current number of synchronous cells in the synchronous cell start bit array. Is recorded in the element indicated by and the cell header is stored in the header accommodating buffer 2
It is stored in 09. If an erroneous cell header is observed, the value of the number of sync cells is also incremented by one at this time, the sync cell start bit array is recorded, and then the cell header is corrected. If the correction is successful, the header is stored in the header accommodating buffer in the same manner as above, and if the correction is unsuccessful, the cell is recorded as the invalid cell in the invalid cell display array with the value of the current number of synchronization cells. Also, the header of the empty cell is output to the header accommodation buffer 209. When an erroneous cell header is observed, 1 is added to the cell synchronization status display variable and the error detection mode 604 of the synchronization status is entered.

In the error detection mode 604 in the synchronization state, the header is confirmed every cell cycle, the number of synchronization cells is incremented by 1, and the synchronization cell start bit is recorded as in the correction mode, and the correct header is observed. In this case, the cell synchronization state display variable is set to 0 and the state is changed to the synchronization state correction mode 603. When an erroneous header is observed, the header is not corrected, the cell is recorded as an invalid cell in the invalid cell display array, and 1 is added to the cell synchronization status display variable. If the value of the cell synchronization state display variable reaches 7, the cell synchronization state display variable is set to -7 and the state is changed to the hunting state 601.

In any state, when the start bit of the cell or the byte for confirming the hunting exceeds 789 words of the data block, the cell synchronization process ends, and 25248 is subtracted from the current value of the cell start bit. As a new cell start bit, the subroutine ends.

There are several possible methods for actual cell synchronization and header error correction. When it is realized by hardware as in the past, for example, Japanese Patent Laid-Open No. 4-3
There is a method disclosed in 63927. According to this method, for cell synchronization, the portion assumed to be the header is taken in bit by bit or byte by byte, and division is performed on GF (2), and the total value of 5 bytes becomes the desired value. It is determined whether or not there is. Further, when performing error correction in a state where synchronization is established, a process of finding the correction position by setting the result of division for 5 bytes as an initial value and continuing the same division in 1-bit units or 1-byte units To do.

As the cell synchronization method adopted here,
A method in which the above cell synchronization method is directly applied to a software program can be considered. First, when cell synchronization is established, as shown in the flowchart of FIG. 13, continuous 1-byte data D1, D2, D3, D4, D5 in the header part
Are read in order (steps 701 to S70).
5) The division processing 706 and the addition on GF (2), that is, the processing of the bitwise exclusive OR 707 are alternately performed, and the determination 708 as to whether or not it is a header is finally performed.
In this case, 5 readings are required for one processing.

When each division process 706 is expressed by a polynomial, input is DI and output is DO. DO = DI * X ^ 8 modG (X) (1) where G (X) = X ^ 8 + X ^ 2 + X + 1
It is expressed as

On the other hand, in the hunting state, as described above, since it is determined whether the cell header is shifted by shifting one byte at a time, the above-mentioned Japanese Patent Laid-Open No. 4-36392.
By making good use of the result of the previous processing as in the method of 7, it is possible to reduce the reading processing.

As an example, it is assumed that the 5-byte continuous data D1, D2, D3, D4 and D5 are processed for cell synchronization at a certain timing. At this time, the value of the division and the exclusive OR is set to H5. At this time,
Data shifted by 1 byte, D2, D3, D4, D
The next processing for 5 and D6 is as shown in FIG.

First, D1 is read again (step 8).
10), division processing 802 different from the above is performed. When this division process 802 is expressed by a polynomial, the input is DI and the output is DO, which is expressed as DO = DI * X ^ 32 modG (X) (2).

Then, the exclusive OR 803 for each bit of the result and H5 is taken, and the whole is expressed by the equation (1).
The division processing B804 represented by is performed. Further, the exclusive OR 806 with the read data D6 is performed, and if the value is a desired value (binary number 01010101), it is determined that the portion is the header, and otherwise. If it is not the header part, it is determined.

In this system, the number of times of reading is 5 in FIG. 13, whereas the number of times of reading is 2; therefore,
The throughput can be reduced. However, in the invention disclosed in the above-mentioned JP-A-4-363927,
The data width for reading once is limited to 8 bits,
However, when a high-performance CPU having a 32-bit width or a 64-bit width is used as in the present embodiment, there is a problem that the efficiency becomes poor.

Therefore, as another method, for example, when a CPU having a width of 32 bits is used, the first 4 bytes are read at a time so that the header is inspected 5 times as shown in FIG. A method that can reduce the number of times of reading as compared with the case of performing it is also conceivable.

For example, as shown in FIG. 15, first, the first 4 bytes D1, D2, D3, D4 of the header are read at once (step 901). Then, division processing 902 is performed on it. If the 32-bit data is divided by G (X) in the equation (1) in order, the division process takes a very long time, and the advantage of reducing the number of reading times to two is lost. .

However, looking at the above division processing bit by bit, it can be seen that each bit and its result have the following relationship. D1 = (d [1], d [2], ..., d [8]) ... (3a) D2 = (d [9], d [10], ... , D [16]) (3b) D3 = (d [17], d [18], ..., d [24]) ... (3c) D4 = (d [25], d [26], ... , D [32]) (3d) D5 = (d [33], d [34], ..., d [40]) (3e).

Then, the 8 bits of the result of the division are set as r [i] (i = 1 to 8) in order from the upper bit, and r [1] = d [2] + d [3] + d [5] + d [10 ] + D [12] + d [14] + d [15] + d [17] + d [19] + d [21] + d [25] + d [26] + d [27] + d [33] (4a) r [2] = d [3] + d [4] + d [6] + d [11] + d [13] + d [15] + d [16] + d [18] + d [20] + d [22] + d [26] + d [27] + d [ 28] + d [34] (4b) r [3] = d [1] + d [4] + d [5] + d [7] + d [12] + d [14] + d [16] + d [17] + d [19 ] + D [21] + d [23] + d [27] + d [28] + d [29] + d [35] (4c) r [4] = d [ 1] + d [2] + d [5] + d [6] + d [8] + d [13] + d [15] + d [17] + d [18] + d [20] + d [22] + d [24] + d [28] + D [29] + d [30] + d [36] (4d) r [5] = d [2] + d [3] + d [6] + d [7] + d [9] + d [14] + d [16] + d [18] + d [19] + d [21] + d [23] + d [25] + d [29] + d [30] + d [31] + d [37] (4e) r [6] = d [3] + d [ 4] + d [7] + d [8] + d [10] + d [15] + d [17] + d [19] + d [20] + d [22] + d [24] + d [26] + d [30] + d [31] + D [32] + d [38] (4f) r [7] = d [2] + d [3] + d [4] + d [8] + d [9] + d [10 ] + D [11] + d [12] + d [14] + d [15] + d [16] + d [17] + d [18] + d [19] + d [20] + d [23] + d [26] + d [31] + d [32] + d [39] (4g) r [8] = d [1] + d [2] + d [4] + d [9] + d [11] + d [13] + d [14] + d [16] + d [ 18] + d [20] + d [24] + d [25] + d [26] + d [32] + d [40] (4h). However, + represents an exclusive OR for each bit.

Therefore, by using this, instead of normal division, these bits are directly added by an exclusive OR operation and programming is performed so that the same result as in the case of division is obtained, thereby significantly increasing the processing time. Can be reduced.

Specifically, as shown in FIG. 16, first, 32 bits of D1, D2, D3, and D4 of the header are read out, and these are read one bit at a time, up to 7 bits on the left side, and up to 2 bits on the right side. Shift up bit by bit. And
When there is no shift, the first bit position of each of D1 to D4 is for r [1], the second bit position is for r [2], and so on. Exclusive data is extracted by extracting only the data.

When the processing is completed, the data D5 is read this time. In D5, d [33] becomes r [1], d
Since [34] is sequentially entered in r [2], and so on, the 8 bits obtained as a result of the exclusive OR of the above 32 bits and each bit of D5 are simply exclusive ORed. When summed, the value r for the final header determination
[1] to r [8] are complete. These 8 bits are 01 described above.
If it is 010101, it is determined to be the header part.

The program of FIG. 16 will be described in more detail. Here, only the part for which r [1] is calculated is shown in FIG.
As described above, the register points for r [1] are the four leftmost points from D1 to D4. In the register 1101 in the case of no shift, d [1], d, which are the first bits of D1 to D4, respectively.
[9], d [17], and d [25] are visible. By shifting this to the left and right in order, d [1] to d
The data up to [27] will be visible.

Therefore, first, the register 1102 of the D1 portion.
Then, only d [2] and d [3] are extracted and subjected to exclusive OR. d [1] is ignored at this time. Similarly, D2
In the partial register 1103, d [5] + d [10], D
In the three-part register 1104, d [12] + d [14]
+ D [15] + d [17] + d [19], and in the D1 register 1105, d [21] + d [25] + d [2
6] + d [27] are calculated respectively. In addition, these four registers and the first v bits of D5, d
[33] is exclusive-ORed to complete r [1]. The same applies to the other r [i] (i = 2 to 8).

At this time, d [28] to d [32] are not visible in the register for r [1], but this is not necessary because these bits do not need to be used as the result of division. Not. For this reason, essentially all bits (that is, d [1] to d [3
2]) must be shifted by 7 bits on each of the left and right sides, but by omitting the unaffected portion, the shift on the left side can be up to 2 bits.

For the data used repeatedly several times in the data processing, if the calculation is made to proceed on the register by using the register variable declaration in the C language, for example, it is unnecessarily loaded from the memory. Can be reduced, and as a result, the processing speed can be increased.

Next, as a method for error correction, a method of performing division in the same manner as described above using equation (1) as in Japanese Patent Laid-Open No. 4-363927 can be considered. There is a problem that the processing is troublesome on software because it requires repeated processing once.

It is known that when r [i] (i = 1 to 8) is determined, whether or not error correction is possible and which bit should be corrected are uniquely determined. Therefore, a table of correctability and a correction bit pattern is built in for all sets of r [i] (64 ways), r [i] is obtained, and this is (0101010).
By using a procedure in which a table is drawn when the condition is not 1) and the correction pattern is known, error correction can be instantaneously performed. However, as a matter of course, it is needless to say that a mode in which cell synchronization is established and error correction is possible is an essential condition.

An extension of the method of drawing such a table can be applied to the case of cell synchronization. That is, of the 5 bytes assumed to be the header, the first 4 bytes are used as an address, the corresponding 5th byte value is subtracted, and this is compared with the actually read 5th byte value. . Since this requires a number of addresses of 2 to the 32nd power, it increases the table amount, but is an effective method for reducing the processing amount.

As described above, in the cell synchronization processing, the unit of data read is set as the processing width of the CPU, and the exclusive OR processing is performed on the entire data or the table search is performed. The software processing can be reduced as compared with the method using the reading and division processing in.

Also in the error correction processing of the cell header, the method of subtracting the table from the surplus pattern to derive the correction pattern is software processing as compared with the conventional method of performing division processing for error correction in byte units. The amount is reduced.

In particular, in the table search, it is not necessary to correct the value of the HEC field as long as it is possible to obtain information as to whether correction is possible. Therefore, since it is only the remaining 4 bytes of the header that needs to be corrected, this embodiment is 32.
The CPU having a bit data width can read the correction pattern table once, which further improves the efficiency.

(Descramble Subroutine 206) Since the number of synchronous cells included in the data block and its start bit are clarified by the cell synchronous subroutine 205, the data of the cell payload is read from the frame data accommodating buffer 209 accordingly. Dashi, sequentially
While performing the descrambling 214, the data is collectively written into the payload accommodating buffer 212 in 12 words for each cell.

In order to descramble a certain bit of the cell payload data, the data that arrived 43 bits before the cell payload is required. Therefore, the last two words of the payload of the last cell of the previous data block are stored as descramble data.

The actual operation is performed as follows. The first 32 bits of the payload of the first cell of the data block are extracted and written to the extract register. The data and the data for descrambling are shifted to the left and right, and the exclusive OR is taken with each bit corresponding to the data of 43 bits before. The obtained data is written to the payload output memory. The first 32 bits written to the register are erased after being used as descramble data for two subsequent descrambles. By declaring the register variables also for the data used for this descrambling, it is possible to reduce the number of times data is loaded from memory and speed up.

When this operation is repeated and the descrambling of the last one word of the payload of the last cell in the data block is completed, the descrambling for this data block is completed. The last two words of data in this cell are then stored for use at the time of descrambling the next data block.

Finally, in accordance with the invalid cell display array, empty cell data is written in the payload portion of the invalid cell. Further, a fixed pattern is applied to the invalid cell portion from the beginning without descrambling the cell payload accommodating buffer 212.
It is also possible to write it in.

In the conventional descrambling method using the concept of hardware, the descrambling process is performed bit by bit or byte by byte, but the payload for one cell is 48 bytes. Yes,
Since this must be repeatedly read at least once for descrambling, the number of readings from the memory is performed by processing in units of 32 bits, which is the maximum value of the CPU data width as in this embodiment. Can be drastically reduced, and thus the software processing amount can be suppressed.

(ATM Layer Subroutine 207) The receiving side ATM layer processing section 3 is composed of a layer processing section 1201 and a header conversion table 1202 as shown in FIG. The ATM layer processing unit 1201 extracts information about the ATM cell extracted by the physical layer processing unit 2 from the header conversion table 1202, converts the header based on the information, adds a routing tag in the switch, A for flow rate monitoring (polishing)
TM layer processing is performed and the data is sent to the data output process 1204.

Further, in the header conversion table 1202,
Information necessary for performing ATM layer processing is stored. Specifically, a connection identifier for a new VPI / VCI or copy connection, in-switch route information (routing tag), policing parameters, and arrival time of a certain number of past cells (counter value; Tp (n)) ) Is written on the table. New VP
If the values of the I / VCI and the routing tag are set at the time of call setup, they will not be changed until the next setting change. The policing declared values (T0, X0, T1, X1) are not changed either. Arrival time information is the corresponding VPI
/ Updated every time the VCI arrives.

The receiving side ATM layer processing section 3 will be described below with reference to the flow chart shown in FIG. (Passing data to and from the physical layer; step 300
1) The ATM cell extracted by the physical layer processing on the receiving side is divided into a cell header and a payload. The ATM layer processing section 3 on the receiving side receives only the header portion of the ATM cell, and the payload section directly outputs the switch output section. 1
Sent to 204. Here, when the data width is 32 bits, since the ATM cell header originally has 5 octets as shown in FIG. 20A, if the header is transferred as it is, 2 words are required as shown in FIG. 20B. .

Therefore, as shown in FIG. 20B, the header sent from the physical layer to the ATM layer is set to 1 word by deleting the HEC field that is not used in the processing on and after the receiving side physical layer. When the data width is 64 bits or more, as shown in FIG. 20 (c), the header fits in one word without deleting the HEC field, but a control information field (routing tag, copy information, etc.) in the ATM switch is added. In this case, the HEC field may be deleted to make the field wider.

(Counting up the number of cells; Step 30)
02) The receiving-side ATM layer processing unit 3 performs flow rate monitoring (policing). For this policing, it is necessary to know the arrival time of the cell to the switching device or the elapsed time from the previous cell of the same VPI / VCI. is there. Here the receiving AT
The M layer processing unit 3 receives all the ATM cells (valid cells, invalid cells, empty cells) input from the physical layer processing unit 2.
Is received, it is possible to know the arrival time of the cell in units of one cell time by counting all these cells. With this method, it is possible to know the exact cell arrival time at this interface without using the external clock used in the switching device, CPU, etc., and there is no need to change the program even if the interface speed is changed. . The real time can be obtained by multiplying this counter value by one cell time.

Here, if the data width that can be used to count the number of cells is m bits, the counter value is incremented by 1 from 0, and when 2 ^ m−1, the counter value is reset to 0. , Will be incremented again.

(VPI / VCI retrieval; step 30)
03) From the received header information, as shown in FIG.
The values of VPI / VCI required for routing and policing are extracted. VPI is the physical layer processing unit 2
It is obtained by shifting the header data (HD) handed over from the unit to the right by (VCI bit length) +4 bits and masking other than the VPI bit length. VCI is H
It is obtained by shifting D to the right by 4 bits and masking other than the bit length of VCI. In this way, VPI /
Even if the VCI bit length changes, it can be easily dealt with by simply changing the parameter of the VPI / VCI bit length.

(Calculation of conversion table address; step 3)
004) From the VPI / VCI extracted earlier, the VP
The reference position of the conversion table 1202 corresponding to the I / VCI is calculated. The reference length of VPI / VCI is set to VPI / VCI.
A (bit) and b (bit) less than the bit length of
Using the lower a (bit) and b (bit) of PI / VCI, the conversion table 1202 corresponding to each VPI / VCI is referred to as shown in FIG.

(Reading out each information; Step 3005) Referring to the conversion table 1202, each information is read out. (Policing-Peak Rate Calculation and Average Rate Calculation; Step 3006) Policing is performed based on the UNI standard defined by the ATM Forum, and a specific implementation method will be described below.

(1. Peak Rate Calculation) In this embodiment,
The time T0 and the maximum number of cells X0 that can exist during the time T0 are used as the declared values for the peak rate monitoring, and the peak rate is represented by X0 / T0. As shown in FIG. 23, assuming that the cell flow arrives at time Tk (k = ..., n−X0, ..., N, ...), the arrival time Tn of the cell to be measured T0 before the arrival time Tn of the measurement target cell is X0. -If T0 hours have not passed since X0, this cell violates the declared peak rate. That is, if Tac = Tn-Tn-X0 is smaller than T0, this cell violates the peak rate.

However, even if the terminal does not send the cell in compliance with the declared value, the cell flow may fluctuate due to buffering of the switching device while passing through the switching device, resulting in a violation state. There is. Therefore, a certain time τ is set to allow a certain amount of fluctuation, and Tac>
If it is T0-τ, it is within the fluctuation range, and it is not regarded as a violation cell. However, the arrival time Tn at this time is Tn = Tn-1 + T0, not the counter value.

Here, when a cell arrives after the counter has been reset, the arrival time interval of the cell before that becomes a negative value, which is not a correct value. Therefore, it is assumed that the cell arrives at Trb, the counter is reset thereafter, and the next cell arrives at Tra. The maximum value of the counter is Tcm
Suppose Then, the arrival interval of cells is Tra-T.
It becomes (Tcm-Trb) + Tra instead of rb. The interval of arrival time between resets of the counter may be calculated by this formula, but it becomes complicated to determine whether or not the counter is reset. Therefore, the calculation of the arrival interval is calculated as (Tra-Trb + Tc
By setting m) mod Tcm, the arrival time interval can be calculated regardless of the reset of the counter.

(2. Average Rate Calculation) To monitor the average rate, the time T1 and the number of cells X1 are used as declared values,
As a result, the average rate that is the monitored value is expressed as X1 / T1. As shown in FIG. 24, the cell flow has time Tk (k = ...,
, n), each time a cell arrives, the difference between the time between the cell and the cell that arrived immediately before and T1 / X1 is integrated. That is, Tad ← Tad + for each cell arrival
((Tk-Tk-1) -T1 / X1) (k = ..., n, ...)
If the value is negative, the cell violates the declared average rate.

The cell arrival time interval is calculated in the same manner as in the case of peak rate monitoring, and in this case as well, it is calculated without being affected by the reset of the counter value. (VPI / VCI reassignment; step 3012) The cells determined not to violate in the above policing are:
The header is overwritten by the new VPI / VCI obtained from the portion corresponding to the VPI / VCI attached to the cell header in the header conversion table 1202 or the connection identifier for the copy connection.

(Add Routing Tag; Step 301)
3) The cell uses VPI / VCI from the header conversion table 1202 to perform self-routing in the switch.
A routing tag that describes the switching information of the switch drawn based on is added to the header part according to the switch cell format.

(Processing when Violation of Peak Rate and Average Rate; Step 3007 to Step 3011)
On the other hand, when the input ATM cell flow violates any of the above policings (peak rate, average rate), the ATM layer processing unit 3 performs the following processing. ATM switch 4 when adding a routing tag
A routing tag determined to be an invalid cell or an empty cell is added in step (steps 3011 and 3013).
Alternatively, a flag indicating that it is a violating cell is added to the corresponding cell (step 3010), and the header conversion is performed as it is (step 3012).

(Updating cell arrival time for polishing; step 3014) Adding routing tag (step 301)
After performing 3), the polishing cell arrival time is updated. Each VPI / VCI as a variable for policing
Regarding the above declared values X0, T0, X1, T1, X
The cell arrival time up to 0 cells before is required. In the present embodiment, in the example of FIG. 25, the arrival times are the array Tp.
(N) (n = 0, 1, ..., X0-1). The contents of this array are updated according to the following algorithm.

If Tp (k) = Tn, then Tp
(K-1) = Tn-1, Tp (k-2) = Tn-2, ...
, Tp (0) = Tn-k, Tp (X0-1) = Tn-k-1
, ..., Tp (k + 1) = Tn-X0. When the next cell arrives, Tp (k + 1) = Tn + 1 and Tp
Update (k + 1). Thus, when the next cell arrives, k is used to perform policing and Tp
(K), Tp (k + 1) (Tp if k = X0-1)
(X0-1), Tp (0)) may be referred to / updated.

(Received data output subroutine (2 in FIG. 1
(Corresponding to 01)) As a result of the processing of the ATM layer subroutine, the header of the cell to be output to the ATM switch 4 with the routing tag added is accommodated in the header accommodating buffer with routing tag 211. At the same time, among the cells obtained by the cell synchronization subroutine, A
Information that is not output to the TM switch 4 can be obtained. From these information and the data in the cell payload accommodating buffer 212 as a result of the descrambling subroutine, A
The cells to be output to the TM switch 4 are reformed and output.

(Reception Side Output Unit) The cell data from the data output subroutine is stored in the reception side output unit 1b, that is, the reception side output FIFO. The receiver output FIFO is A
Cell data is output to the ATM switch 4 according to the timing from the TM switch 4.

The output FIFO of the receiving side sends out an empty cell when there is no data inside. Also, the receiving side output F
If there is no free space in the IFO, the cell data from the data output subroutine is discarded.

Next, the structure and details of the transmission side speech path process subroutine will be described. (Subroutine division) Regarding the communication path process on the transmission side, the same process as on the reception side is performed. The flow of each subroutine in the transmission side communication path process and the flow of information such as data, pointers, and valid cells at that time will be described below with reference to FIG. In FIG. 26, the thick arrow indicates the data flow, and the thin arrow marked P indicates the pointer flow.

First, the cell output from the ATM switch 4 is input to the transmission side input section 7a, that is, the transmission side input FIFO. The cell data in the transmission side input FIFO is written in the switch cell accommodating buffer 2009 on the CPU memory by the transmission side input subroutine 2003.
Here, when the capacity of the transmission side input FIFO can be made sufficiently large, it is not necessary to hold the cell data once in the switch cell accommodating buffer 2009, and the portion 2014 surrounded by the dotted line in the upper part of FIG. 26 is unnecessary.

Only the pointer of the switch cell accommodating buffer 2009 is passed from the transmitting side input subroutine 2003 to the transmitting side ATM layer processing subroutine 2004.
The ATM layer processing subroutine 2004 stores the cell data in the switch cell accommodating buffer 200 based on this pointer.
Take out from 9. When the switch cell accommodating buffer 2009 is omitted as described above, the cell data is directly sent to the transmitting side ATM layer processing section 5.

In the transmitting side ATM layer processing section 5, the routing tag added in the receiving side ATM layer processing section 3 is deleted from the cell of the switch format, and A
Convert to TM format cell. Also, VPI / VCI conversion and shaping are performed as necessary.

As a result of shaping, the ATM on the transmitting side
Since the cell order is different from that when input to the layer processing unit 5, the cell order after shaping is recorded in the cell order accommodation buffer 2012, and the pointer is passed to the physical layer processing subroutine 2005.

The cell is separated into a header and a payload and accommodated in the header accommodation buffer 2010 and the payload accommodation buffer 2011, and only the pointer is passed to the physical layer processing subroutine 2005.

In the physical layer processing subroutine 2005, mainly the scrambling of the payload part and the HEC of the header are performed.
It calculates parts and incorporates cell data into frames. First, the data necessary for framing is read from the payload accommodating buffer in cell units according to the cell transmission order in the cell order accommodating buffer 2012, and scrambled sequentially. At the time of this incorporation, a header corresponding to the payload is separately read from the header accommodating buffer 2010, HEC corresponding to the read 4-byte header is calculated, added to the HEC, and combined with the scrambled payload part to form cell data. Then incorporate that data into the frame. This data is written in the output frame data accommodating buffer 2013 and is delivered to the output process 2008. At this time, if the output FIFO of the transmission side is sufficiently large, or if the physical layer processing subroutine is activated by sensing that the output FIFO of the transmission side is empty, the frame data is once stored in the output frame data accommodating buffer 2013. It is not necessary to save the data, and it is possible to directly pass the data to the transmission side output subroutine 2006 and write it in the external FIFO. In this case, the portion 2015 surrounded by the dotted line at the bottom of FIG. 26 is unnecessary.

As described above, the transmission side speech path process is divided into subroutines like the reception side speech path process. As a result, it is possible to freely combine software and hardware, for example, to replace the scramble of the payload with hardware.

As for the physical layer processing on the transmitting side, the software processing can be reduced by processing with the data width of the CPU similarly to the physical layer on the receiving side.

In the HEC generation, in the processing according to the conventional hardware concept, the header is divided into 4 bytes by 1 byte.
It was necessary to read the data twice and perform the division processing each time, but in the 32-bit CPU of this embodiment, the header 4
The value of HEC can be easily obtained by reading the byte once and performing an exclusive OR operation or drawing a table.

For scrambling as well as for descrambling, 48 bytes of data must be read for each cell. Therefore, it is necessary to read this with a data width of 32 bits or the like as compared with the conventional method of reading this in 1-bit and 1-byte units. Thus, the number of times of reading can be reduced.

Further, by writing the scrambled data directly into the FIFO for frame transmission, there is no need to write once into the internal cache memory,
Therefore, the number of writings can be reduced.

Generally, a lot of processing is performed by the CPU for writing to and reading from the memory and the FIFO. Therefore, by effectively using the CPU data width exceeding 1 byte as described above to process the data, the number of times of writing and reading is reduced, and therefore the CPU processing is reduced.

FIG. 27 shows a comparison between the conventional processing by the physical layer described above and the processing in this embodiment. Next, each procedure and subroutine will be described in more detail.

(Sending side input processing subroutine 2003)
The cell data output from the ATM switch 4 is held in the transmission side input FIFO. Transmitting side input subroutine 2
003 writes the data in the FIFO into the switch cell accommodating buffer 2009 on the CPU memory. ATM layer processing subroutine 2 which is the next subroutine
A pointer of the switch cell accommodating buffer 2009 and the number of accommodating cells are given to 004. If the portion 2014 surrounded by the dotted line in the upper part of FIG. 26 is omitted, this subroutine simply passes the data from the FIFO to the ATM layer processing subroutine 2004.

(Sending ATM layer processing subroutine 2
004) Delete the cells added with information such as routing tag, copy tag, etc. in the receiving side ATM layer processing section 3 and changed to the switch cell format in the transmitting side ATM layer section 5 at the receiving side. AT
Return to M cell format. At the same time, in order to facilitate the scrambling of the payload section performed by the transmission side physical layer processing section 6 described later, the cell header and the payload section are separated.

When the ATM switch 4 has a copy function, the ATM layer processing unit 3 on the receiving side performs VPI / VCI.
Instead of performing the above conversion, a connection identifier valid only within the switching device is added, and the transmitting side ATM layer processing unit 5
Then, with this connection identifier, VPI / VCI
Referring to the conversion table 1202, the new VPI / VCI
The method of rewriting is effective.

Furthermore, due to congestion control in the ATM switch and multiplexing with cells from other paths, the state of the cell flow changes from the state when it is input. Therefore,
It is effective to execute the shaping process for shaping the cell flow so as to match the declared value in the transmission side ATM layer processing unit 5.

When performing shaping, it is necessary to know the temporal position in the output cell flow of the cell to be shaped. Therefore, the number of cells passed from the ATM layer processing unit 5 to the physical layer processing unit 6 is counted, and this counting number is used for shaping in a unit of one cell time, so that the CPU needs to have a clock function. Absent. As described above, by counting the number of cells delivered to the physical layer processing unit 6, for example, the ATM switch 4 having a cell transfer rate higher than the cell transfer rate at the interface point for the purpose of improving cell discard characteristics. Even in the ATM layer processing subroutine corresponding to the above, this method enables shaping at the cell transfer rate in the physical layer processing unit 6.

(Physical layer processing subroutine 2005)
When a frame is generated, it is generated in units of one frame. In the frame structure used as a model here, the cell data included in one frame is 96 bytes, and the number of cells is less than 2 cells, and it is rare that a cell break and a frame generation break match. . Therefore, it becomes necessary to transfer the following data between the subroutines that generate frames. These are frame write points, cell read points, scrambled data, in-memory cell write variables, in-memory cell read variables and the like. The frame writing point represents the position where the next writing is performed in the frame in byte units, and takes a value from 0 to 95. The cell read point represents the position where data is read next in a cell on the internal memory of the CPU in byte units, and takes a value from -52 to 52.

When the value is negative, it means that there is no outputtable cell on the memory and therefore an empty cell is being output. The absolute value indicates the number of bytes of the empty cell. The scramble data is data used to scramble the first two words of data in this data block, and is the last two words of data after scrambling in the previous data block. Of course, when the framing of this data block ends, the last two words after scrambling of this data block are inserted.

The in-memory cell write variable represents the point at which the next cell is written in the memory of the CPU. By comparing this value with the value of the in-memory cell read variable indicating the point at which the cell is read, Determine the presence or absence. When the value of the write variable is equal to the value of the read variable, there is no readable cell, and when the write variable is larger than the read variable, there is a readable cell. When the reading of one cell is completed, the reading point of the cell is incremented by 1 and a comparison with the write variable is made.

Next, the procedure for actually generating a new frame will be described with reference to FIG. First, the data (0 to 3 bytes) left over from the last word in the previous frame generation is inserted into the beginning of the current frame (step 4001). Actually, the operation to write all 1 word is performed, but the frame writing point according to the number of bytes of the remaining data is received,
By starting writing the next data according to the value, the remaining data is written to the frame.

Next, the state of the previous physical layer processing is checked by the value of the cell read point. If the previous framing of the physical layer processing was completed while the empty cell was being output (step 4002)
If Yes in step 4003, if the output is from the HEC (Yes in step 4003; cell read point is −).
4) First, the HEC of the empty cell is written in the output frame data accommodating buffer 2013 (step 4004), and thereafter, the data of the empty cell is scrambled and written in the buffer (step 4005). Here, since the header pattern of an empty cell has a fixed value, HEC
Has a constant value, and it is only necessary to output the empty cell HEC data. On the other hand, if it is from the output of the payload portion (No in step 4003; cell read point is -5 or less), the rest of the payload of the empty cell is scrambled and written in the buffer (step 4005).

If the previous framing was in the process of outputting a valid cell (Yes in step 4006), H
If it is from the output of EC (Yes in step 4007; the value of the cell read point is 4), HEC is first calculated from the value of the header and written in the buffer (step 4008), and then the payload part is scrambled. While writing to the buffer (step 400
9). On the other hand, if it is from the payload part (step 4
If No in 006; the value of the cell read point is 5 or more), the remaining payload portion is scrambled and written into the buffer (step 4009).

Next, after performing the above steps 4005 and 4009, or in the case of No in step 4006, that is, when the previous processing has just ended at the end of the cell (the value of the cell read point is 0), The following processing is performed.

Notify whether there is a valid outputable cell in the memory on the CPU (step 4010 or 40).
15), and output the valid cells accordingly (step 401
1-4013 or 4016-4018) or an empty cell is output (step 4014 or 4019).
All data writing positions in these buffers are performed according to the value of the frame writing point. Also, when writing is performed, the values of the frame writing point and the cell reading point are always updated. When outputting to the end of one cell in the case of output of either empty cell or valid cell, the cell read point is initialized to 0, 1 is added to the in-memory cell read variable, and the valid cell that can be output again is It is checked whether it exists on the CPU and the next cell is output accordingly.

The above processing is continuously performed until the frame data is filled, that is, until the frame writing point becomes 96 or more. When the frame is filled, the physical layer processing subroutine ends by saving the data for scrambling, saving the extra data from the frame data, and setting the frame writing point for the next framing.

The cell payload scrambling procedure will be described below with reference to FIG. To scramble a bit in the cell payload, use 43 from that bit.
The scrambled data that is output before the bit is required. Therefore, in order to scramble the current data word, the latest two words of the scrambled data are always held in the register.
At this time, by designating this variable as a register variable on C, it is possible to reduce unnecessary load to the memory and speed up. The actual descrambled data is
Exclusive of the 1-word data read from the cell payload accommodating buffer and the scrambled data of 2 words, the older one of which is shifted 21 bits to the left and the newer data is shifted to the right by 11 bits. It is obtained by processing logical disjunction. The newly obtained data is output as cell data on the frame and held in a register inside the CPU as data for scrambling to the next data. In addition, the older one of the scrambled two-word data is discarded. If there is no readable cell in the internal memory, an empty cell is output in the framing subroutine. At that time, a method of not scrambling the payload part of the data may be considered.

As described in detail in the cell synchronization, the HEC calculation is performed by shifting the data of the header having a length of 1 word to the left by up to 7 bits and to the right by up to 2 bits in total.
Mask each of the data and set the required bits to 4
Act on any of the two bytes, and finally the 4
It is possible to calculate by taking the exclusive OR of each bit of one byte.

(Transmission side output processing subroutine 2006)
When outputting data, the data of one frame passed to the FIFO of the output unit 7b on the transmission side is 24 words and 21 bits, but there are several methods for how to output this data continuously between frames. Can be considered. First, there is a method of storing odd data in internal memory by software and adding it to the beginning of the next frame. In addition, by using the hardware shown in FIG.
2301 outputs the information of the effective bit width of the data together with the parallel data, and the data is the FIF for the data.
A method of storing effective bit width information in the O2302 in the effective data width storage FIFO 2304 and performing parallel-serial conversion in the parallel-serial converter 2303 according to the information may be considered.

As described above, the software processing efficiency has not been improved so much in the idea that the physical layer processing is performed in the unit of bit which is the processing unit of the conventional hardware or in the unit of byte at most. That is, a high-performance processor that is supposed to be used in a switching device by software processing usually has a data width exceeding 8 bits such as 32 bits or 64 bits, whereas the physical layer processing is performed in byte units. It was because I was doing. In software processing, the time for processing such as reading data from the memory and writing it in the register occupies most of the overall processing efficiency, so that the data processing width matches the data width of the processor well as in the present embodiment. By thinking about programming in this way, the software processing efficiency of the physical layer is dramatically improved.

Next, an embodiment according to another invention will be described. In the above embodiment, the physical layer process and the AT
It has been described that the header part and the payload part are spatially divided and managed as the cell transfer with the M layer process. Below, information indicating where these data were actually written in the memory in the CPU or information indicating which cell was read is exchanged so that the flow of data between these two processes will be successful. The method will be described. Here, an embodiment of a method of performing exclusive control of shared memory using a pointer will be shown.

FIG. 31 shows the flow of data on the receiving side and the transmitting side and the state of the pointer. First, on the receiving side, the input data is stored in the receiving side FIFO 2801,
Physical layer processing is performed by the reception side physical layer process 2802, and the data in the form of cells is written in the reception side buffer 2803 on the CPU memory. At the time of this writing, the memory area of the cell which has not been read yet by the ATM layer process 2804 on the receiving side should not be overwritten. Therefore, the receiving side writable address pointer column 2805 has a CPU
An address pointer of an area where a cell is not written is entered on the receiving side buffer 2803 on the memory, and the cell is written in the pointer portion contained therein. A pointer corresponding to the area of the written cell is output from the receiving side writable address pointer column and is moved to the receiving side readable address pointer column 2806.

The receiving ATM layer process 2804 is
The process may be allowed to execute when the receiver readable address pointer column 2806 is not empty. Then, the cell is read from the area on the memory buffer 2803 indicated by the address pointer at the beginning of the reception side readable address pointer 2806, and A
The TM layer processing is performed and the cell is output to the ATM switch (not shown).

Here, the receiving side writable address pointer sequence 2805 does not need to be a FIFO, and the receiving side physical layer process 2802 can select any of the pointers included in the pointer sequence. However,
The readable address pointer column 2806 on the receiving side is FI
FO structure, ATM layer process 2 on the receiving side
804 must select the one at the top of the pointer sequence. This is A unless it is a FIFO structure.
This is because the processing order of TM cells is changed.

The procedure on the transmitting side is exactly the same. A
The ATM cell arriving from the TM switch is the ATM on the transmitting side.
After being subjected to ATM layer processing by the layer process 2807, it is written in the transmission side buffer 2808 on the CPU memory. At this time, the transmitting side physical layer process 2
It must be ensured that no cells are overwritten in the area where cells have not yet been read by 809.
Therefore, the transmitting ATM process first refers to the transmitting side writable address pointer column 2810 before writing a cell in the transmitting buffer 2808 on the CPU memory.

Then, one of the pointers written therein is selected, and the cell is written in the area on the memory buffer 2808 indicated by the pointer. Then, the pointer is moved to the transmission side readable address pointer column 2811 on the opposite side.

The transmitting side physical layer process 2809 can read a cell from the transmitting side buffer on the CPU memory when the transmitting side readable address pointer column 2811 has a pointer. The pointer column 281
The pointer at the head of 1 is referred to, the cell is read from the area of the memory buffer 2808 indicated by the pointer, the physical layer processing is performed on the cell, and the cell is sent to the transmission side FIFO 2812.
The data is output to the line side. Further, the referenced pointer can be written again when the cell is read out, and is therefore returned to the transmitter-side writable address pointer column 2810.

Similar to the receiving side, in order to guarantee the cell order,
The transmission side readable address pointer column 2811 is FI.
It has a FO structure and must be read from the beginning. On the other hand, the transmitter side writable address pointer column 2
810 is not limited to this.

As described above, the physical layer process and the ATM are identified by the pointers on the transmitting side and the receiving side.
Exclusive control of the memory with the layer process can be easily realized. According to the present embodiment, a plurality of software programs running at the same time to perform one exchange process share the same memory, thereby eliminating unnecessary processing for transfer and improving processing efficiency, and using a pointer. Cell or other data that can be processed between programs
By performing exclusive control so that one program can occupy, it is possible to prevent the pipeline processing from being disturbed due to data competition among a plurality of processing, and to improve processing efficiency. Further, by exclusively controlling the access right to the memory by using the pointer, memory conflict does not occur, and the pipeline processing is not disturbed by the exclusive control during program execution. Efficient exchange processing can also be executed by a language program.

The memory buffers 2803 and 283
The number 08 is not necessarily required to be two physically. Also, physical layer processes 2802 and 2809,
The ATM layer processes 2804 and 2807 do not necessarily have to be in the form of separate processes. Furthermore, when the memory buffer is shared, the writable address pointer columns 2805 and 2810 may be shared for transmission and reception.

Further, instead of using the address pointer sequence, a ring buffer may be used and an address pointer may be inserted therein to indicate the read and write head positions, respectively.

Further, not limited to the case of the ATM layer processing and the physical layer processing, depending on the configuration, for example, a plurality of ATMs may be used.
It is possible that a memory is shared between layer processes and the like.
Of course, it is also possible to apply the memory exclusive control as described above to the embodiments of FIG. 5 and FIG. Further, the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0195]

As described above, according to the present invention, by processing the processing unit in each processing such as physical layer processing so as to match the data width of the processor mounted in the switching device, the conventional bit can be processed. By processing on a byte-by-byte or byte-by-byte basis, the processing efficiency of inefficient software processing (especially physical layer processing) can be dramatically increased, especially in terms of copying frames or cells from memory to registers. .

Further, according to the present invention, when the memory is shared between the ATM layer processing and the physical layer processing, or the plurality of ATM layer processings, etc., the memory access right is exclusively controlled, and the memory Does not occur, and there is no disturbance in the pipeline processing due to exclusive control on program execution, and therefore, efficient exchange processing can also be executed by a program in a high-level language such as C language.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of this embodiment.

FIG. 2 is a diagram for explaining a method of realizing a layer processing unit by software.

FIG. 3 is a diagram showing an overall configuration of an exchange apparatus including a processor exchange processing package.

FIG. 4 is a diagram for explaining division of a receiving side call path process subroutine.

FIG. 5 is a configuration diagram of an interface in this embodiment.

FIG. 6 is a diagram showing an example of a reception side communication channel data input portion.

FIG. 7 is a diagram showing a reception side communication channel data input format.

FIG. 8 is a flow chart of reception side speech path frame synchronization processing.

FIG. 9 is a state transition diagram for detecting a frame bit synchronization pattern 1100.

FIG. 10 is a diagram showing data reading for conventional frame synchronization according to a hardware concept.

FIG. 11 is a diagram showing data reading for frame synchronization in the present embodiment.

FIG. 12 is a flow chart of reception side call path cell synchronization processing.

FIG. 13 is a flowchart of conventional cell synchronization processing.

FIG. 14 is a flow chart of cell synchronization processing in which each byte is shifted in the hunting state.

FIG. 15 is a flowchart of cell synchronization processing when D1 to D4 of FIG. 11 are read at once.

FIG. 16 is a diagram for explaining a calculation for cell synchronization.

FIG. 17 is a diagram for explaining details of an operation for cell synchronization regarding r [1] in FIG. 16;

FIG. 18 is a schematic configuration diagram of a receiving side ATM layer processing section.

FIG. 19 is a flow chart of ATM layer processing on the receiving side.

FIG. 20 is a diagram for explaining HEC deletion processing.

FIG. 21 is a diagram for explaining VPI / VCI extraction processing.

FIG. 22 is a diagram for explaining a header conversion table reference procedure.

FIG. 23 is a diagram for explaining the principle of policing (peak rate monitoring).

FIG. 24 is a diagram for explaining the principle of policing (average rate monitoring).

FIG. 25 is a diagram for explaining a cell arrival time storage procedure.

FIG. 26 is a diagram for explaining division of a transmission side call path process subroutine.

FIG. 27 is a diagram for comparing the physical layer processing of the related art with that of the present embodiment.

FIG. 28 is a flow chart of a transmission side communication path physical layer process.

FIG. 29 is a flowchart of data descramble processing.

FIG. 30 is a diagram showing a transmission side speech path data output portion.

FIG. 31 is a schematic configuration diagram for explaining memory buffer exclusive control by an ATM layer process and a physical layer process.

[Explanation of symbols]

1a ... Reception side input section, 1b ... Reception side output section, 2 ... Reception side physical layer processing section, 3 ... Reception side ATM layer processing section, 4
... switch section, 5 ... transmission side ATM layer processing section, 6 ... transmission side physical layer processing section, 7a ... transmission side input section, 7b ... transmission side output section, 11 ... processor, 12 ... main memory,
13 ... Program storage unit, 16 ... Cache memory, 1
01 ... Channel process, 102 ... OAM process, 11
1 ... Bit synchronization, 112 ... Network synchronization, 113 ... OAM cell drop / insert, 114 ... Supervisory control interface, 121 ...
Line decoding, 122 ... Frame synchronization, 123
... cell synchronization, 124 ... descramble, 125 ... header conversion, 126 ... routing tag addition, 127 ... flow monitoring (policing), 128 ... cell transmission, 129 ... empty cell generation, 131 ... line encoding, 132 ... frame creation, 133 ... HEC generation, 134 ... Scrambling, 135 ... Header conversion, 136 ... Routing tag deletion, 137 ... Flow rate monitoring (shaping), 138 ... Cell reception, 141 ... Monitoring control processing, 142 ... Message transmission, 143 ... Message reception, 201 ... CPU procedure,
202 ... CPU memory buffer, 203 ... Received data input subroutine, 204 ... Frame synchronization subroutine, 205 ... Cell synchronization subroutine, 206 ... Descramble subroutine, 207 ... ATM layer processing subroutine, 208 ... Received data output subroutine, 209
... Frame data accommodating buffer, 210 ... Cell header accommodating buffer, 211 ... Routing header-added header accommodating buffer, 212 ... Cell payload accommodating buffer, 27
01 ... FIFO on receiving side, 2702 ... FIFO on sending side, 2
703 ... n-bit data width processor, 301 ... Clock extraction part, 302 ... Serial-parallel conversion part, 3
03 ... Receiving side data input FIFO, 304 ... CPU, 3
05 ... Counter, 1001 ... No shift register, 1
002 ... left 1-bit shift register, 1003 ... left 2-bit shift register, 1004 ... right 1-bit shift register, 1005 ... right 2-bit shift register, 1006
... right 3 bit shift register, 1007 ... right 4 bit shift register, 1008 ... right 5 bit shift register,
1009 ... right 6-bit shift register, 1010 ... right 7
Bit shift register, 1011 ... Exclusive OR, 11
01 ... Register without shift, 1102 ... Register display of D1 portion, 1103 ... Register display of D2 portion, 110
4 ... D3 part register display, 1105 ... D4 part register display, 1106 ... D1 part register value addition,
1107 ... D2 part register value addition, 1108 ... D
Addition of register values of 3 parts, 1109 ... Addition of register values of D4 parts, 1110 ... Register values of D5 parts, 11
11 ... Exclusive OR, 1201 ... ATM layer processing unit,
1202 ... Header conversion table, 1203 ... Physical layer processing process, 1204 ... Switch output process, 20
01 ... CPU procedure, 2002 ... CPU memory buffer, 2003 ... Transmission side input processing, 2004 ... ATM layer processing, 2005 ... Physical layer processing, 2006 ... Transmission side output processing, 2009 ... Switch cell accommodating buffer, 20
10 ... Cell header accommodation buffer, 2011 ... Cell payload accommodation buffer, 2012 ... Cell order accommodation buffer,
2013 ... Output frame data accommodating buffer 2014
... Switch cell accommodating buffer input / output process, 2015
... Output frame accommodating buffer input / output process, 2301
... CPU, 2302 ... Transmission side data output FIFO, 23
03 ... Transmission side parallel-serial converter, 2304 ...
Transmitting side effective data width storage FIFO, 2801 ... Receiving side F
IFO, 2802 ... Receiving side physical layer process, 280
3 ... Receiving side buffer on CPU memory, 2804 ... Receiving side ATM layer process, 2805 ... Receiving side writable address pointer sequence, 2806 ... Receiving side readable address pointer sequence, 2807 ... Sending side ATM layer process, 2808 ... On CPU memory Transmitter buffer, 28
09 ... Transmission side physical layer process, 2810 ... Transmission side writable address pointer sequence, 2811 ... Transmission side readable address pointer sequence, 2812 ... Transmission side FIF
O

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yasuro Masahata No. 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Research and Development Center, a stock company (72) Inventor Yoshiaki Takahata Ko-ko, Kawasaki-shi, Kanagawa Muko Toshiba Town No. 1 in Toshiba Research & Development Center Co., Ltd. (72) Inventor Kimura Adult Komukai Toshiba Town No. 1 in Komu Toshiba City, Kawasaki City, Kanagawa Prefecture (72) Inventor Mikio Hashimoto Kawasaki, Kanagawa Prefecture Komukai Toshiba-cho, Sachi-ku, Yokohama-shi Incorporated company Toshiba Research and Development Center

Claims (8)

[Claims] 1. An AT input from each of a plurality of receiving lines
By performing an exchange process for outputting the M cell to any of the plurality of transmission lines based on the destination information added to the information, and causing a processor to execute a predetermined program for at least a part of the exchange process. In the exchange device for performing, the data unit that can be processed by the information in the process executed by using the processor in the exchange process is set to a data width that can be processed by the processor. 2. Among the exchange processing, processing executed by using a processor is bit synchronization processing, frame creation processing,
The switching device according to claim 1, further comprising at least one of a cell synchronization process, an HEC creation process, a scramble process, and a descramble process. 3. An AT input from each of a plurality of receiving lines
By performing an exchange process for outputting the M cell to any of the plurality of transmission lines based on the destination information added to the information, and causing a processor to execute a predetermined program for at least a part of the exchange process. In the switching device for performing the serial communication, which constitutes the ATM cell from the reception line,
First data width conversion means provided in each of the reception lines for converting data into parallel data having a data width processable by a processor and outputting the parallel data, and the data provided in each of the data width conversion means. By inputting the parallel data from the width converting means and causing the processor to execute a predetermined program, the receiving side physical layer processing and the receiving side A are performed on the parallel data.
First processing means for performing TM layer processing; switching means for exchanging information from each of the first processing means and outputting the information to any one of a plurality of output terminals; Second processing means for performing transmission side physical layer processing and transmission side ATM layer processing on the information from the switch means by causing a processor or a separately provided processor to execute a predetermined program; and the second processing. Second data width conversion means provided in each of the means for converting the information from the second means into serial data and outputting the serial data to the accommodated transmission line. Exchange device. 4. The first data width conversion means each include clock extraction means for extracting a clock signal from given serial data, and convert the serial data into parallel data according to the extracted clock signal. 4. The exchange device according to claim 3, further comprising serial-parallel conversion means for outputting the output. 5. The second data width conversion means each generate means for generating information indicating an effective bit width of parallel data, and based on this information, the parallel data are converted into serial data and output. The exchange device according to claim 3, comprising parallel-serial conversion means. 6. An AT input from each of a plurality of receiving lines
An exchange process for outputting the M cell to any of the plurality of transmission lines based on the destination information added to the information is performed, and the exchange process is configured by a plurality of processes, and at least two of the plurality of processes are performed. In a switching device that performs the above processing by causing a processor to execute a predetermined program, common information storage means for storing common information to be processed when performing each of the two or more processing, An exchange apparatus comprising an access control means for performing control to selectively give a use right for accessing the common information storage means to each of two or more processes. 7. An AT input from each of a plurality of receiving lines
An exchange process for outputting the M cell to any of the plurality of transmission lines based on the destination information added to the information is performed, and the exchange process is configured by a plurality of processes, and at least two of the plurality of processes are performed. In a switching device that performs the above processing by causing a processor to execute a predetermined program, a physical layer processing unit that executes the physical layer processing by using the processor, and a processor that is the same as the processor used by the physical layer processing unit. An ATM layer processing means for executing the ATM layer processing using a processor or a processor provided separately, and a common for storing common information to be processed by both the physical layer processing means and the ATM layer processing means. The information storage means, the physical layer processing means and the ATM layer processing means An exchange apparatus comprising: an access control unit that performs control for selectively giving a right to use for accessing the common information storage unit. 8. The access control means gives the usage right by giving a pointer indicating a position in the common information storage means in which the information is stored. Exchange device.