JPH08181032A - Laminated ceramic capacitor - Google Patents
Laminated ceramic capacitorInfo
- Publication number
- JPH08181032A JPH08181032A JP33599394A JP33599394A JPH08181032A JP H08181032 A JPH08181032 A JP H08181032A JP 33599394 A JP33599394 A JP 33599394A JP 33599394 A JP33599394 A JP 33599394A JP H08181032 A JPH08181032 A JP H08181032A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- ceramic capacitor
- layers
- internal electrode
- laminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003985 ceramic capacitor Substances 0.000 title claims abstract description 37
- 239000000919 ceramic Substances 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 12
- 239000000203 mixture Substances 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 2
- 238000009413 insulation Methods 0.000 abstract description 7
- 238000000926 separation method Methods 0.000 abstract 1
- 230000032798 delamination Effects 0.000 description 9
- 238000010304 firing Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002003 electrode paste Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、携帯電話・ＶＴＲ・カメ
ラ等の電子機器に使用される積層セラミックコンデンサ
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monolithic ceramic capacitor used in electronic devices such as mobile phones, VTRs and cameras.
【０００２】[0002]
【従来の技術】従来、この種の積層セラミックコンデン
サは、次のように製造される。まず、ドクターブレード
工法やロール工法により、セラミック粉末を有機バイン
ダと混合したセラミックスラリーをセラミックグリーン
シート（以下、単にシートと称す）に成形する。次に、
このシート上に内部電極用ペーストをスクリーン印刷し
て、図２に示すように、内部電極層３を形成したシート
を複数枚積み重ね合わせて有効層５を形成する。更に、
この有効層５の上下に非有効層４となる、内部電極ペー
ストを印刷していないシートを複数枚積み重ね合わせ
る。その後、熱圧着し、特定形状に切断し、焼成して、
積層セラミックコンデンサ素子１が形成される。次い
で、内部電極が露出する取り出し端面に導電性ペースト
を塗布・焼付けして、外部電極を形成して積層セラミッ
クコンデンサが得られる。2. Description of the Related Art Conventionally, this type of laminated ceramic capacitor is manufactured as follows. First, a ceramic slurry in which ceramic powder is mixed with an organic binder is formed into a ceramic green sheet (hereinafter simply referred to as a sheet) by a doctor blade method or a roll method. next,
The internal electrode paste is screen-printed on this sheet, and a plurality of sheets each having the internal electrode layer 3 formed thereon are stacked to form an effective layer 5, as shown in FIG. Furthermore,
A plurality of sheets on which the internal electrode paste is not printed, which will be the ineffective layer 4, are stacked above and below the effective layer 5. After that, thermocompression bonding, cutting into a specific shape, firing,
The monolithic ceramic capacitor element 1 is formed. Next, a conductive paste is applied and baked on the extraction end surface where the internal electrodes are exposed, and external electrodes are formed to obtain a monolithic ceramic capacitor.
【０００３】[0003]
【発明が解決しようとする課題】しかし、セラミックと
内部電極とに収縮差があるために、内部電極層を積層し
ている有効層と、内部電極層を積層していない非有効層
との境界面に収縮歪みが発生して、セラミックコンデン
サ内に残留歪みとして残存し、その残留応力が電圧印加
等により解放され、図３に示すように、層間剥離（デラ
ミネーション）８や割れ９が発生して、絶縁抵抗劣化等
の信頼性不具合を発生するという問題があった。However, due to the difference in shrinkage between the ceramic and the internal electrode, the boundary between the effective layer having the internal electrode layer laminated and the ineffective layer having no internal electrode layer laminated. A contraction strain is generated on the surface and remains as a residual strain in the ceramic capacitor, and the residual stress is released by voltage application or the like, and as shown in FIG. 3, delamination 8 or crack 9 occurs. Therefore, there is a problem in that reliability problems such as deterioration of insulation resistance occur.
【０００４】本発明の課題は、積層セラミックコンデン
サの信頼性に大きく影響する層間剥離（デラミネーショ
ン）の発生原因の一つであるセラミック層と内部電極層
の収縮差を緩和させて、残留応力の発生をなくして、信
頼性の高い積層セラミックコンデンサを提供することで
ある。An object of the present invention is to alleviate the difference in shrinkage between the ceramic layer and the internal electrode layer, which is one of the causes of delamination, which greatly affects the reliability of the monolithic ceramic capacitor, to reduce residual stress. It is an object to provide a highly reliable multilayer ceramic capacitor that eliminates the occurrence.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決・改善す
るために、本発明は、従来法における積層セラミックコ
ンデンサの内部電極層の積層されていない非有効層内
に、少なくとも一層以上、外部電極と電気的に接続しな
い、かつ内部電極層と同一組成の金属層を設けたもので
あり、このことにより、内部電極層を積層している有効
層と、内部電極層を積層していない非有効層の焼成収縮
差を緩和して、残留応力を発生させず、従って、層間剥
離（デラミネーション）及び割れのない、信頼性の高い
積層セラミックコンデンサを得ようとするものである。In order to solve and improve the above problems, the present invention provides at least one or more external electrodes in the non-effective non-laminated internal electrode layers of the multilayer ceramic capacitor in the conventional method. A metal layer that is not electrically connected to the internal electrode layer and that has the same composition as the internal electrode layer is provided, which allows an effective layer in which the internal electrode layer is laminated and an ineffective layer in which the internal electrode layer is not laminated. An object of the present invention is to obtain a highly reliable multilayer ceramic capacitor which relaxes the difference in firing shrinkage of layers so as not to generate residual stress, and therefore has no delamination and cracks.
【０００６】即ち、本発明は、内部電極層及び強誘電体
セラミック層を複数層積層して有効層を形成し、この有
効層の両面に前記強誘電体セラミック層と同材の層を積
層して非有効層を形成してなる積層セラミックコンデン
サにおいて、前記非有効層の内側に外部電極と電気的に
接続せず、かつ前記内部電極層と同一組成からなる金属
層を設けたことを特徴とする積層セラミックコンデンサ
である。That is, according to the present invention, a plurality of internal electrode layers and ferroelectric ceramic layers are laminated to form an effective layer, and layers of the same material as the ferroelectric ceramic layer are laminated on both surfaces of the effective layer. A non-effective layer is formed on the inside of the non-effective layer, a metal layer not electrically connected to an external electrode and having the same composition as the internal electrode layer is provided. It is a multilayer ceramic capacitor.
【０００７】[0007]
【作用】本発明においては、内部電極層の積層されてい
ない非有効層内に、内部電極層と同一組成の金属層を設
けることにより、焼成時の有効層と非有効層の収縮差が
緩和される。従って、セラミックコンデンサ内に収縮歪
みが残存せず、残留応力が発生しない。よって、電圧印
加の際、層間剥離（デラミネーション）が生じず、かつ
絶縁抵抗不良が起きない。In the present invention, by providing a metal layer having the same composition as the internal electrode layer in the non-effective layer in which the internal electrode layers are not laminated, the difference in shrinkage between the effective layer and the ineffective layer during firing is relaxed. To be done. Therefore, shrinkage strain does not remain in the ceramic capacitor, and residual stress does not occur. Therefore, when voltage is applied, delamination does not occur, and insulation resistance failure does not occur.
【０００８】[0008]
【実施例】以下、本発明の実施例を図面に基づいて詳細
に説明する。図１は、本発明の積層セラミックコンデン
サ素子の説明図である。図１（ａ）は、その斜視図、図
１（ｂ）は、その断面図である。図１（ａ）、図１
（ｂ）に示すように、本発明の積層セラミックコンデン
サ素子６は、セラミック層２、内部電極層３で構成され
る有効層５と、セラミック層２、金属層７で構成される
非有効層４とからなる。Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is an explanatory diagram of a monolithic ceramic capacitor element of the present invention. FIG. 1A is a perspective view thereof, and FIG. 1B is a sectional view thereof. 1 (a), FIG.
As shown in (b), the multilayer ceramic capacitor element 6 of the present invention comprises an effective layer 5 composed of a ceramic layer 2 and an internal electrode layer 3, and an ineffective layer 4 composed of a ceramic layer 2 and a metal layer 7. Consists of.
【０００９】本発明の積層セラミックコンデンサ素子６
は、次のように製造される。鉛系ペロブスカイトセラミ
ック粉末と有機バインダを混合し、スラリーを得た後、
セラミックグリーンシートを成形した。次に、このシー
ト上に内部電極としてＡｇ−Ｐｄ系ペーストをスクリー
ン印刷し、これを積層して有効層５を形成した。Multilayer ceramic capacitor element 6 of the present invention
Is manufactured as follows. After mixing the lead-based perovskite ceramic powder and the organic binder to obtain a slurry,
A ceramic green sheet was molded. Next, an Ag-Pd paste was screen-printed as an internal electrode on this sheet, and this was laminated to form an effective layer 5.
【００１０】一方、その上下に内部電極を形成していな
いセラミックシートを複数枚積層して、非有効層４を形
成し積層体を得た。この非有効層を形成する際、外部電
極を取り出す端面に露出しないように、前記のＡｇ−Ｐ
ｄ系ペーストと同一組成の金属ペーストを前記セラミッ
クグリーンシート上にスクリーン印刷し、非有効層に金
属層を一層設けた。On the other hand, a plurality of ceramic sheets having no internal electrodes formed thereon were laminated to form an ineffective layer 4 to obtain a laminate. When forming this non-effective layer, the Ag-P is formed so as not to be exposed at the end face where the external electrode is taken out.
A metal paste having the same composition as the d-based paste was screen-printed on the ceramic green sheet to provide a metal layer as an ineffective layer.
【００１１】このセラミック積層体を１００〜１５０ｋ
ｇ／ｃｍ2の圧力、１００〜１４０℃の温度で熱圧着
し、１０００〜１２００℃の温度にて焼成して、図１
（ａ）に示す、幅２.５ｍｍ、長さ３.２ｍｍ、厚さ２.
０ｍｍの大きさの積層セラミックコンデンサ素子６を得
た。This ceramic laminate is 100 to 150 k
Thermocompression bonding at a pressure of g / cm 2 and a temperature of 100 to 140 ° C. and firing at a temperature of 1000 to 1200 ° C.
Width 2.5 mm, length 3.2 mm and thickness 2. shown in (a).
A multilayer ceramic capacitor element 6 having a size of 0 mm was obtained.
【００１２】次に、その焼結体の内部電極が露出する取
り出し端面に導電性ペーストを塗布・焼付けして、外部
電極を形成して積層セラミックコンデンサを得た。この
得られた積層セラミックコンデンサを実施例１とした。
実施例２として、前記の金属層を３層とした以外は、実
施例１と同様にして積層セラミックコンデンサを得た。
又、実施例３として、前記の金属層を５層とした以外
は、実施例１と同様にして積層セラミックコンデンサを
得た。同様に、比較例として従来法により同形状の積層
セラミックコンデンサを作製した。Next, a conductive paste was applied and baked on the take-out end surface of the sintered body where the internal electrodes were exposed, and external electrodes were formed to obtain a monolithic ceramic capacitor. The obtained multilayer ceramic capacitor was named as Example 1.
As Example 2, a laminated ceramic capacitor was obtained in the same manner as in Example 1 except that the above-mentioned metal layers were three layers.
Further, as Example 3, a laminated ceramic capacitor was obtained in the same manner as in Example 1 except that the above-mentioned metal layers were 5 layers. Similarly, as a comparative example, a monolithic ceramic capacitor having the same shape was manufactured by a conventional method.
【００１３】以上のようにして得られた実施例１、実施
例２、実施例３、及び比較例の積層セラミックコンデン
サを、厚さ１.５ｍｍのアルミナ基板上に半田付け実装
させ、４０℃−９０％RHの環境下にて定格電圧を印加し
て、１０００Ｈｒ稼動後の層間剥離発生状況、及び絶縁
抵抗劣化を各々コンデンサ１０００個について測定し
た。なお、絶縁抵抗は、１.０×１０9Ω以下を不良とし
た。又、静電容量・ｔａｎδの電気特性についても測定
した。表１、表２に、これらの結果を比較して示した。The monolithic ceramic capacitors of Example 1, Example 2, Example 3 and Comparative Example obtained as described above were mounted by soldering on an alumina substrate having a thickness of 1.5 mm, and a temperature of 40 ° C. A rated voltage was applied in an environment of 90% RH , and the occurrence of delamination after 1000 hours of operation and insulation resistance deterioration were measured for each of 1000 capacitors. The insulation resistance was determined to be 1.0 × 10 9 Ω or less. In addition, the electric characteristics of capacitance and tan δ were also measured. Table 1 and Table 2 show these results in comparison.
【００１４】 [0014]
【００１５】 [0015]
【００１６】以上のように、本発明の積層セラミックコ
ンデンサは、従来の積層セラミックコンデンサと比較し
て、層間剥離（デラミネーション）が見られず、絶縁抵
抗の劣化もないため、高い信頼性を有することがわか
る。又、静電容量・ｔａｎδの諸特性についても、従来
法と同等であり、問題がない。As described above, the monolithic ceramic capacitor of the present invention has higher reliability than the conventional monolithic ceramic capacitor because delamination is not observed and insulation resistance is not deteriorated. I understand. Also, the various characteristics of capacitance and tan δ are the same as those of the conventional method, and there is no problem.
【００１７】[0017]
【発明の効果】以上のように、本発明によれば、内部電
極の積層されている有効層の上下に形成される非有効層
内に外部電極と電気的に接続しない、かつ内部電極層と
同一組成の金属層を設けることにより、有効層と非有効
層との焼成収縮差が緩和され、焼成収縮差により発生し
ていた残留応力が発生せず、そのために、層間剥離（デ
ラミネーション）の発生はなく、かつ絶縁抵抗の劣化も
ない、高信頼性の積層セラミックコンデンサが提供でき
た。As described above, according to the present invention, the internal electrodes are not electrically connected to the external electrodes in the ineffective layers formed above and below the effective layer in which the internal electrodes are laminated. By providing the metal layer having the same composition, the difference in firing shrinkage between the effective layer and the ineffective layer is relaxed, and the residual stress generated due to the difference in firing shrinkage is not generated. Therefore, delamination of delamination does not occur. It was possible to provide a highly reliable monolithic ceramic capacitor that did not generate and did not deteriorate the insulation resistance.
【図１】本発明の積層セラミックコンデンサ素子の説明
図。図１（ａ）は、本発明の積層セラミックコンデンサ
素子の斜視図。図１（ｂ）は、本発明の積層セラミック
コンデンサ素子の断面図。FIG. 1 is an explanatory diagram of a monolithic ceramic capacitor element according to the present invention. FIG. 1A is a perspective view of a monolithic ceramic capacitor element of the present invention. FIG. 1B is a sectional view of the monolithic ceramic capacitor element of the present invention.
【図２】従来の積層セラミックコンデンサ素子の説明
図。図２（ａ）は、従来の積層セラミックコンデンサ素
子の斜視図。図２（ｂ）は、従来の積層セラミックコン
デンサ素子の断面図。FIG. 2 is an explanatory view of a conventional monolithic ceramic capacitor element. FIG. 2A is a perspective view of a conventional monolithic ceramic capacitor element. FIG. 2B is a sectional view of a conventional monolithic ceramic capacitor element.
【図３】従来の積層セラミックコンデンサ素子の不良を
説明する断面図。FIG. 3 is a cross-sectional view illustrating a defect of a conventional monolithic ceramic capacitor element.
１ （従来の）積層セラミックコンデンサ素子 ２ （強誘電体）セラミック層 ３ 内部電極層 ４ 非有効層 ５ 有効層 ６ （本発明の）積層セラミックコンデンサ素子 ７ 金属層 ８ 層間剥離 ９ 割れ 1 (Conventional) Multilayer Ceramic Capacitor Element 2 (Ferroelectric) Ceramic Layer 3 Internal Electrode Layer 4 Ineffective Layer 5 Effective Layer 6 (Inventive) Multilayer Ceramic Capacitor Element 7 Metal Layer 8 Delamination 9 Crack
Claims (1)
複数層積層して有効層を形成し、この有効層の両面に前
記強誘電体セラミック層と同材の層を積層して非有効層
を形成してなる積層セラミックコンデンサにおいて、前
記非有効層の内側に外部電極と電気的に接続せず、かつ
前記内部電極層と同一組成からなる金属層を設けたこと
を特徴とする積層セラミックコンデンサ。1. An ineffective layer formed by laminating a plurality of internal electrode layers and ferroelectric ceramic layers to form an effective layer, and laminating layers of the same material as the ferroelectric ceramic layer on both surfaces of the effective layer. A multilayer ceramic capacitor formed by forming a metal layer not electrically connected to an external electrode and having the same composition as the internal electrode layer inside the ineffective layer. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33599394A JPH08181032A (en) | 1994-12-22 | 1994-12-22 | Laminated ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33599394A JPH08181032A (en) | 1994-12-22 | 1994-12-22 | Laminated ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08181032A true JPH08181032A (en) | 1996-07-12 |
Family
ID=18294599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33599394A Pending JPH08181032A (en) | 1994-12-22 | 1994-12-22 | Laminated ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08181032A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002015941A (en) * | 2000-06-28 | 2002-01-18 | Matsushita Electric Ind Co Ltd | Chip-type electronic component |
| JP2002033236A (en) * | 2000-07-13 | 2002-01-31 | Matsushita Electric Ind Co Ltd | Chip-type electronic component |
| US8564930B2 (en) | 2011-04-13 | 2013-10-22 | Taiyo Yuden Co., Ltd. | Laminated capacitor |
| US10224147B2 (en) | 2013-07-10 | 2019-03-05 | Taiyo Yuden Co., Ltd. | Multilayer ceramic capacitor |
-
1994
- 1994-12-22 JP JP33599394A patent/JPH08181032A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002015941A (en) * | 2000-06-28 | 2002-01-18 | Matsushita Electric Ind Co Ltd | Chip-type electronic component |
| JP2002033236A (en) * | 2000-07-13 | 2002-01-31 | Matsushita Electric Ind Co Ltd | Chip-type electronic component |
| JP4581194B2 (en) * | 2000-07-13 | 2010-11-17 | パナソニック株式会社 | Chip-type electronic components |
| US8564930B2 (en) | 2011-04-13 | 2013-10-22 | Taiyo Yuden Co., Ltd. | Laminated capacitor |
| US8810993B2 (en) | 2011-04-13 | 2014-08-19 | Taiyo Yuden Co., Ltd. | Laminated capacitor |
| US10224147B2 (en) | 2013-07-10 | 2019-03-05 | Taiyo Yuden Co., Ltd. | Multilayer ceramic capacitor |
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