JPH08180696A - Nonvolatile semiconductor device provided with verify function - Google Patents

Abstract

PURPOSE: To provide a nonvolatile semiconductor memory unit which is capable of sharply shortening the writing time and erase time of a high-integration flash memory. CONSTITUTION: Flash memory cells are arranged in a matrix in the nonvolatile semiconductor memory and each memory cell 2nk is connected to a word line WLi and a bit line BLi. Each word line WLi is connected with a verify cell 4n which is verified instead of the memory cell 2nk when the memory cell 2nk is verified. The memory cell 2nk and the verify cell 4n are formed to have almost the same structure of NAND type EEPROM with a floating structure whereas the gate couple ratio of the verify cell 4n is set to be smaller than the gate couple ratio of the memory cell 2nk. Consequently when a sufficient amount of electrons are injected into these two cells, the threshold value of the verify cell 4n is invariably smaller than the threshold value of any of memory cells 2nk. Hence, confirmation of the verify of the verify cell 4n means that the memory cell is verified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a verify function, and more particularly to a nonvolatile semiconductor memory device having a verify memory cell.

[0002]

2. Description of the Related Art In a nonvolatile memory such as an EEPROM or a flash memory, after writing / erasing data, it is necessary to confirm whether or not the data is really written / erased. This confirmation operation is called verify. Verify
It is executed by comparing the current of the cell after writing / erasing with the current of the reference cell via a sense amplifier. Generally, writing / erasing is performed for a certain period of time, and then verification is performed. When the current value of the cell reaches the specified value by this repetition, the verification is completed and the writing / erasing is completed.

[0003] Here, although it is simply described as writing and erasing, the writing operation and the erasing operation are generally independent, and the term "program verify" for writing and the term "erasable verify" for erasing are used.

[0004]

As the integration density of the flash memory increases, the ratio of verify in the write and erase operations increases, and the time required for writing or erasing increases. In particular, the program verify is an obstacle to reducing the write time because it is executed bit by bit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a non-volatile semiconductor memory device which has been made in view of the above circumstances and which can significantly reduce the writing time and erasing time of a highly integrated flash memory.

[0006]

According to the present invention, a large number of programmable flash memory cells arranged in a matrix, word lines and bit lines connecting the memory cells arranged in a matrix, and parallel to the memory cells. A verify cell having the same structure as the memory cell and having a couple ratio different from that of the memory cell, the verify cell being connected to each other by a common bit line and connected to a common bit line; There is provided a non-volatile semiconductor device having a verifying function, which comprises:

According to the embodiment of the present invention, the verifying means includes a means for selecting a word line and a reading means for reading an output of the verifying cell from a verifying cell connected to the selected wording line via a bit line. There is provided a non-volatile semiconductor device including:

Further, according to the embodiment of the present invention, it is characterized in that it includes a reference cell for generating a reference signal and a comparison circuit for comparing the reference signal from this reference cell with the output from the verify cell. A semiconductor device is provided.

Further, according to the embodiment of the present invention, there is provided a non-volatile semiconductor device characterized in that a verify cell includes a verify cell group of first and second columns arranged in parallel with a memory cell. .

[0010]

The memory cell connected to the word line can be verified only by verifying the verify cell, and the verify can be performed for each word line, so that the verify time can be greatly shortened.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A non-volatile semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, in a nonvolatile semiconductor device according to an embodiment of the present invention, a nonvolatile memory cell, in the example shown in FIG. 1, a flash memory cell in which bit data is written and erased. 2nk are arranged in the X row and the Y column. A verify cell 4n for verifying the flash memory cell 2nk arranged in X rows and Y columns.
Is added in one column. The memory cell 2nk and the verify cell 4n are formed in a floating gate type memory structure having substantially the same floating gate as will be described later, but are manufactured so that their gate couple ratios are different. As shown in FIG. 1, the control gates of the memory cell 2nk and the verify cell 4n are connected to the X- via the word lines WLi, WLi + 1, WLi + 2 ,.
The drain of the memory cell 2nk is connected to the decoder 10 and is connected to the write and sense amplifier 6 via the bit lines BLi, BLi + 1, ... And the bit line selecting transistor 8n, and the source of the memory cell 2nk is the source line. It is connected to the ground via SLi, SLi + 1, .... The gate of the transistor 8n for selecting a bit line is connected to the Y decoder 12.

The drain of the verify cell 4n has a bit line BLvi and a bit line selecting transistor 8v.
Connected to the sense amplifier 14 for verification via
The source of the verify cell 4n is connected to the ground via the source line SLvi like the memory cell 2nk. The output side of the reference cell 16 having the same structure as the memory cell 2nk or the verify cell 4n is connected to the sense amplifier 14.

The memory cell 2nk and the verify cell 4n shown in FIG. 1 are the EEPROM as shown in FIGS.
Is formed into a structure. That is, as shown in FIGS. 2 and 3, in these cells 2nk and 4n, a p-type silicon substrate 20 is doped with n-type impurity ions to form a high-concentration impurity diffusion region (n +) as a drain region 21 and a source. Region 22 is formed. A tunnel oxide film 23 is formed on the silicon substrate 20 including the drain and source regions 21 and 22. A floating gate 24 made of a polysilicon film is formed on the tunnel oxide film 23 on the channel region between the source and drain regions 21 and 22. An interlayer insulating film 25 made of silicon oxide is formed on the tunnel oxide film 23 other than the floating gate 24.

A cap 26 (Cap) made of polysilicon is formed which covers the exposed surface of the floating gate 24 and covers the surface of the interlayer insulating film 25 and the regions above the source and drain regions 22 and 21. ing. On the cap 26 and the interlayer insulating film 27, an ONO film 27 as an insulating layer having a structure in which silicon oxide / silicon nitride is laminated is further formed on the surface of the interlayer insulating film 25 including the cap 26. ing. A control gate 28 made of polysilicon is formed on the ONO film 27.

The dimension of the cap 26 is different between the memory cell 2nk and the verify cell 4n shown in FIGS. That is, in the memory cell 2nk shown in FIG. 2, the cap 26 has a length Lx1 along the direction in which the source region 22 and the drain 21 are arranged and a direction orthogonal to the direction in which the source region 22 and the drain region 21 are arranged. It has a parallel length Ly1 and has a substantially rectangular cap area S1 (= Lx1 × Ly1) represented by Lx1 × Ly1. On the other hand, in the verify cell 4n shown in FIG. 3, the length Lx2 along the direction in which the source region 22 and the drain region 21 are arranged and the length along the direction orthogonal to the direction in which the source region and the drain region are arranged. Has a length Ly2, and has a substantially rectangular cap area S2 (= Lx2 × Ly2) represented by Lx2 × Ly2. 2 and 3
As is clear from the comparison, the cap length Lx1 of the memory cell 2nk is set larger than the cap length Lx2 of the verify cell 4n. The cap length Ly1 of the memory cell 2nk is the cap length Ly of the verify cell 4n.
Since it is set equal to 2, the cap area S1 of the memory cell 2nk is larger than the cap area S2 of the verify cell 4n.

Memory cell 2 having the structure as described above
In nk and verify cell 2n, the gate couple ratio of verify cell 4n is set smaller than the gate couple ratio of memory cell 2nk. The gate couple ratio increases as the capacitance between the channel region and the floating gate 24 and the capacitance between the floating gate 24 and the control gate 28 increase.
In the memory cell 2nk and the verify cell 4n shown in FIGS. 2 and 3, since the areas where the channel region and the floating gate 24 face each other are the same, the capacitance between the channel region and the floating gate 24 is the same. ,equal. On the other hand, the memory cell 2
The areas S1 and S2 in which the floating gate 24 and the control gate 28 face each other are different in the nk and the verify cell 2n, and the floating gate 24 and the control gate 28 face the memory cell 2nk more than the verify cell 2n. Since the area S1 is large, the floating gate 24 and the control gate 28 are larger in the memory cell 2nk than in the verify cell 2n.
The capacitance between them becomes large. The gate couple ratio of the memory cell 2nk is larger than that of the verify cell 2n.

As described above, the verify cell 4n having a gate couple ratio different from that of the memory cell 2nk is incorporated in the semiconductor device, and the verify cell 4n is simply verified. The memory cells 2nk of 1, ... Can be verified.

The cells having different couple ratios are as follows.
The simplest method is simply to adjust the area of the tunnel oxide film of the cell and the surface area of the floating gate. That is, the structure shown in FIG. 2 and FIG.
As shown in S patents 4, 833, and 514, a cell with a small coupling ratio can be obtained by shortening the verify cell from the array cell by devising the photomask with the hatched polysilicon cap. Is clear.

Generally, writing or erasing to the flash memory cell 2nk is performed by Fowler-Nordheim tunnel current (hereinafter, FN current) or hot electron injection (hereinafter, HE injection). A verify cell 4n having a smaller gate couple ratio than the array memory cell 2nk is prepared, and each floating gate 2n is prepared.
4 shows electron injection characteristics into the floating gate 24, electron extraction characteristics from the floating gate 24, and hot electron injection characteristics into the floating gate 24.
It becomes like (a), (b), and (c). This Figure 4
As is clear from (a), (b), and (c), the array cell having a large couple ratio has a faster change in the threshold value Vth regardless of whether the F / N current or HE injection is performed.
It can be seen that the threshold values are different from each other. Utilizing this property, each word line WLi, WLi + 1, WLi + 2 can be simply verified by writing a program in the verify cell 4n and erasing a program from the verify cell 4n.
, Can verify the memory cell 2nk connected to.

First, program verification will be described.

First, the write operation is executed. That is,
The word line WLi is selected by the X decoder 10, a write selection voltage is applied to the word line WLi, and the bit line BLi of the memory cell 2nk to be written is selected.
, BLi + 1 ... And the selection transistors 8v, 8 connected to the bit line BLvi of the verify cell 4n.
n is selected by the Y decoder 12 and bit line B
A write voltage is applied to any one of Li, BLi + 1 ... And the bit line BLvi. In this way, data, for example, data "1" is written in the memory cell 2nk and the verify cell 4n to be written. In this write operation, the selection voltage and the write voltage are applied for a certain period of time, and the memory cell 2nk and the verify cell 4n are each given a threshold value in a predetermined range.

After this write operation, the verify operation is started. In the verify operation, the verify cell 4n of the word line WLi to which the programmed memory cell 2nk is connected is selected by the X decoder 10 and the verify voltage is applied. This verify voltage corresponds to the threshold voltage of the verify cell 4n programmed as described later. After that, the bit line BLvi
The selection transistor 8v connected to the Y decoder 12
Is selected. Therefore, the output from the programmed verify cell 4n is supplied to the sense amplifier 14. At the time of this verify operation, the reference cell 16 is also turned on, so that the reference output is supplied from the reference cell 16 to the sense amplifier 14. The sense amplifier 14 compares the reference output with the output from the verify cell 4n. Here, if the verify cell 4n is programmed correctly, for example, the level of the output from the verify cell 4n is larger than the level of the reference output, which means that the sense amplifier 14 has been programmed correctly. Output "1" is output. If the verify cell 4n is not properly programmed, for example, the level of the output from the verify cell 4n is smaller than the level of the reference output, which means that the sense amplifier 14 is not correctly programmed. Output "0" is output.

The erase verify is executed as described below in the same manner as the write verify. Here, the erase operation is executed for each common source and each common well. That is, the erase gate voltage is applied to the word lines WLi, WLi + 1, ... And the erase well voltage or the erase voltage is applied to the common well or the common source, or the erase well voltage and the erase well voltage are applied to the common well and the common source, respectively. An erase voltage is applied. In this way, the data in the memory cell 2nk and the verify cell 4n are erased. In this erasing operation, the selection voltage and the erasing voltage are applied for a certain period of time, and the memory cell 2nk and the verify cell 4n are respectively given a threshold value in a predetermined range.

After this erase operation, the verify operation is started. In the verify operation, verify cells 4n from which data has been erased are successively selected by the X decoder 10 and a verify voltage is applied. This verify voltage corresponds to the threshold voltage of the verify cell 4n at the time of erasing, as will be described later. When the selection transistor 8v connected to the bit line BLvi is selected by the Y decoder 12, the output from the erased verify cell 4n is supplied to the sense amplifier 14. In this verify operation, the reference output from the reference cell 16 which is turned on is compared with the output from the verify cell 4n by the sense amplifier 14. Here, when the verify cell 4n is properly erased, for example, the level of the output from the verify cell 4n is smaller than the level of the reference output, which means that the sense amplifier 14 has correctly erased. Output "0" is output. If the verify cell 4n is not erased, for example, the level of the output from the verify cell 4n is higher than the level of the reference output, and the sense amplifier 14 outputs an output indicating that the verify cell 4n has not been erased correctly. "1" is output. In this way, it is verified whether all the verify cells 4n have been erased.

As described above, by verifying the verify cell 4n, programming or erasing of the memory cell 2nk sharing the word line WLi with the verify cell 4n is verified. This is based on the following reasons.

FIG. 3A shows the distribution of the threshold values of a large number of cells, the horizontal axis shows the cell count corresponding to the number of cells, and the vertical axis shows the threshold voltage Vth.
Graphs A1 and B1 show the threshold distributions of the memory cell 2nk and the verify cell 4n at a certain time when electrons are injected into the floating gate 24. Also, graph A
2 and B2 indicate the threshold distributions of the memory cell 2nk and the verify cell 4n at a certain point in time when electrons are extracted from the floating gate 24.

As is clear from the graphs A1 and B1 in FIGS. 4A and 5A, when electrons are injected into the floating gate 24, if the threshold value of the verify cell 4n rises to a certain value, the couple ratio is increased. In the memory cell 2nk that is larger than the verify cell, the threshold change reaches a higher threshold level because the threshold change is faster than the verify cell 4n. Therefore, if it is checked whether the verify cell 4n conducts at the threshold value, the other memory cell 2nk is confirmed to be the verify cell 4n.
Since it has a predetermined threshold value having a threshold value larger than the threshold value of n 2, it is not necessary to check whether or not the memory cell 2nk corresponding to this verify cell 4n conducts at that threshold value.

Further, as is clear from the graphs A2 and B2 of FIGS. 4B and 5A, when electrons are extracted from the floating gate 24, if the threshold value of the verify cell falls to a certain value, the couple is An array cell having a ratio larger than that of the verify cell reaches a lower threshold level because the threshold change is faster than that of the verify cell. Therefore, if it is checked whether or not the verify cell 4n conducts at the threshold value, the other memory cell 2nk is confirmed to be the verify cell 4n.
Since it has a predetermined threshold value having a threshold value smaller than the threshold value, it is not necessary to check whether or not the memory cell 2nk corresponding to this verify cell 4n conducts at that threshold value. From this principle, the word line W
The verification of the memory cell 2nk is guaranteed only by checking one verify cell 4n for the bit sharing L.

Even when hot electrons are injected into the floating gate 4n, the graph A of FIG.
Since the distributions similar to those shown in 1 and B1 are shown, hot electrons are similarly injected and data is stored in the memory cell 2
Even when writing to nk or erasing,
The memory cell 2nk can be verified by simply verifying the verify cell 4n.

Here, when the reference cell 16 is formed in the same cell type as the array memory cell 2nk and the coupling ratio of the reference cell 16 is made equal to the coupling ratio of the array memory cell 2nk, the offset with respect to the verify cell 4n is set. It is necessary to check the sense ratio adjustment of the sense amplifier 14 for adjustment by the TEG process. If the reference cell 16 is also a cell of the same type as the verify cell 4n, its adjustment becomes easy.

From the above, the following applications are possible.

(1) Add a bit line consisting of a verify cell 4n having a larger coupling ratio than the array cell 2nk.

This verify cell 4n can be used for over-by-race and over-program check. That is, as shown in FIG.
And the threshold distribution of the array cell 2nk is different from that in FIG. That is, the relationship between the threshold values of the memory cell 2nk and the verify cell 4n at a certain point in time when electrons are injected into the floating gate 24 is that if the threshold value of the memory cell 2nk rises to a certain value as is clear from the graphs C1 and D1. The verify cell 4n having a larger couple ratio than the memory cell 2n reaches a higher threshold level because the threshold change is faster than that of the memory cell 4n. Further, the relationship between the thresholds of the memory cell 2nk and the verify cell 4n at a certain point in time when electrons are extracted from the floating gate 24, as is clear from the graphs C2 and D2, if the threshold of the memory cell 2nk falls to a certain value, The verify cell 4n having a larger couple ratio than the memory cell 2nk reaches a lower threshold level because the threshold change is faster than that of the memory cell 2nk.

Utilizing this property, the verify cell 4n shown in FIG. 1 is made to have a larger coupling ratio than the array cell 2nk, so that the verify cell 4n is replaced by the memory cell 2nk.
It can be used for over-the-race and over-program check.

(2) In the circuit shown in FIG. 1, the memory cells are classified into first and second memory cells having different thresholds, and the first and second memory cells have a smaller couple ratio than the first and second memory cells, respectively. A multilevel memory can be dealt with by adding two or more bit lines each including a second verify cell.

When a multilevel memory is manufactured by changing the voltage applied to the word line, the first level is verified by the first verify cell and the second level is verified by the second verify cell. At this time, the couple ratios of the first verify cell and the second verify cell do not necessarily have to be the same.

[0038]

Since the program verify and erase verify can be performed only by the verify cell or the verify bit line, the writing time and the erasing time of the highly integrated flash memory can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a non-volatile semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell shown in FIG.

3 is a cross-sectional view schematically showing the structure of the verify cell shown in FIG.

4A, 4B, and 4C are graphs showing electron injection characteristics, electron extraction characteristics, and hot electron injection characteristics of a memory cell and a verify cell, respectively.

5 (a), (b) and (c) are graphs showing threshold distributions for a large number of cells when the gate couple ratio is changed in the memory cell and the verify cell, respectively.

[Explanation of symbols]

 2nk ... Flash memory cell 4n ... Verify cell WLi, WLi + 1, WLi + 2, ... Word line BLi, BLi + 1, ... Bit line 8n, 8v ... Bit selection transistor SLvi ... Source line 16 ... Reference cell 20 ... Substrate 21 ... Source region 22 ... Drain region 23 ... Tunnel oxide film 24 ... Floating gate 26 ... Cap 28 ... Control gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/788 29/792 H01L 29/78 371

Claims (4)

[Claims] 1. A plurality of programmable flash memory cells arranged in a matrix, word lines and bit lines connecting the memory cells arranged in a matrix, and common bit lines arranged in parallel with the memory cells. A verify cell having the same structure as that of the memory cell and having a couple ratio different from that of the memory cell; and a verifying unit for verifying the verify cell. A non-volatile semiconductor device having a verify function characterized by the above. 2. The verifying means includes means for selecting a word line and read means for reading the output of the verify cell from the verify cell connected to the selected word line via the bit line. The non-volatile semiconductor device according to claim 1. 3. The non-volatile memory according to claim 2, wherein the read means includes a reference cell for generating a reference signal and a comparison circuit for comparing the reference signal from the reference cell with the output from the verify cell. Semiconductor device. 4. The non-volatile semiconductor device according to claim 1, wherein the verify cell includes first and second verify cell groups arranged in parallel with the memory cell.