JPH08179366A - Thin film transistor array - Google Patents

Abstract

(57) [Summary] [Purpose] To provide a TFT array that leaves a short ring so as to prevent corrosion when the wiring is exposed at the end face of the TFT array and to prevent the wiring from being exposed at the end face. To do. A thin film transistor 24 and a display electrode connected to one of a source electrode and a drain electrode of the thin film transistor 24 are provided at each intersection of a plurality of address lines 22 and a plurality of data lines 23 arranged to intersect each other. Two
5 are arranged in a matrix form, and the address wiring 22 is connected to the gate electrode of the thin film transistor 24, and the data wiring 23 is connected to the other of the source electrode and the drain electrode. Connection terminals 26 formed at the respective ends of 23 and outside the connection terminals 26,
A protective element 28 having a high resistance or a non-linear resistance characteristic, which is connected between metal wires exposed on the cut surface of the thin film transistor array, is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array used in a liquid crystal display device in which a plurality of display electrodes connected to thin film transistors are arranged in a matrix.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor (hereinafter referred to as a TFT
(Hereinafter referred to as)) and a display electrode are arranged in a matrix, and an active matrix type liquid crystal display element (hereinafter referred to as TFT-LCD) is used. As such a conventional TFT-LCD,
For example, a liquid crystal display element having an equivalent circuit of a TFT array as shown in FIG. 8 is known.

As shown in FIG. 8, a TFT array is arranged on an insulating transparent substrate 1 in a row direction and a column direction so that a plurality of address wirings 2 and data wirings 3 intersect each other at right angles. A plurality of TFTs 4 each having a gate electrode connected to the address wiring 2 and a drain electrode connected to the data wiring 3 are arranged at the intersection of the address wiring 2 and the data wiring 3, and connected to the source electrode of the TFT 4. A plurality of display electrodes 5 are arranged in a matrix.

A short ring 10 is formed on the outer peripheral portion of the insulating transparent substrate 1, and the address wiring 2 group and the data wiring 3 group are electrically connected to each other through the short ring 10. As a result, all the gate line groups and the drain line groups are kept at the same potential, so that the panel is protected from static electricity. In addition, 6 is an address wiring terminal, 7 is a data wiring terminal, 8 is an address wiring sub-terminal,
Reference numeral 9 is a data wiring sub-terminal.

The short ring 10 is cut and removed after the liquid crystal cell assembly process is completed. That is, the above-mentioned TFT
-Using an Al-based material as the wiring material of the LCD, the wiring is connected to the short ring 10 outside the panel for static electricity prevention and power supply at the time of gate anodic oxidation, and the connection with the short ring 10 is made at the time of scribing and breaking. A TFT array as shown in FIG. 10 is obtained by cutting along a cutting line B shown in FIG.

[0006]

However, the end surface of the TFT panel cut along the cutting line as described above is shown in FIG.
As shown in Fig. 3, since the Al-based wiring is exposed, when operating in a high temperature and high humidity environment, the driving voltage is
By applying a driving force between the system wirings or between the common electrode terminals to which the Al-based wirings serving as the gate wirings and the counter electrode (not shown) facing the pixel electrodes are connected,
There is a problem that the Al-based wiring is cathodically corroded from the end surface of the system wiring, and the corrosion reaches the connection terminal, resulting in poor contact or disconnection at the connection terminal.

That is, as for the corrosion of Al-based wiring, an electric bias is applied under high humidity (the presence of water), and an electrochemical reaction proceeds to cause cathodic corrosion, causing a failure such as disconnection. It is known. Therefore,
If the drive voltage cuts off the current leaking from the wiring exposed portion on the end face of the panel, the corrosion does not proceed even if the Al-based wiring is exposed on the end face.

As shown in FIG. 11, since the address wiring 2 is formed on the substrate 11 and the address wiring 2 is covered with the passivation film 12, no problem occurs. The present invention
In order to eliminate the above problems, when the wiring is exposed on the end face of the TFT array, it is possible to prevent the corrosion and to provide the TFT array with the short ring left so that the wiring is not exposed on the end face. The purpose is to do.

[0009]

In order to achieve the above-mentioned object, the present invention provides a thin film transistor and a source electrode of the thin film transistor at each intersection of a plurality of address wirings and a plurality of data wirings arranged to intersect each other. And a plurality of display electrodes connected to one of the drain electrodes are arranged in a matrix, and the address wiring is connected to the gate electrode of the thin film transistor, and the data wiring is connected to the other of the source electrode and the drain electrode. In the array, a high resistance or non-linearity connected between a connection terminal formed at each end of the address wiring and the data wiring and a metal wiring formed outside the connection terminal and exposed on a cut surface of the thin film transistor array. A protective element having a resistance characteristic is provided.

A thin film transistor and a display electrode connected to one of a source electrode and a drain electrode of the thin film transistor are provided at each intersection of a plurality of address wirings and a plurality of data wirings arranged to intersect each other. In a thin film transistor array arranged in a matrix, the address wiring is connected to the gate electrode of the thin film transistor, and the data wiring is connected to the other of the source electrode and the drain electrode, respectively. The connection terminal, the protection element having a high resistance or non-linear resistance characteristic connected to the outside of the connection terminal, and the short bar connected to the outside of the protection element are provided.

[0011]

According to the present invention, as described above, the connection terminals formed at the respective ends of the address wiring and the data wiring,
Since a protection element having a high resistance or a non-linear resistance characteristic, which is formed outside the connection terminal and is connected between the metal wires exposed on the cut surface of the thin film transistor array, is provided, an address wiring is formed on the cut surface of the thin film transistor array. Even when the cross section of the wiring extending from the data wiring is exposed, the electric circuit can be opened by the insertion of the protective element to prevent cathodic corrosion, and contact failure and disconnection due to cathodic corrosion of the connection terminal can be eliminated. .

Further, further, by inserting the protection element, even if the short bar is left, there is no hindrance to the operation of the normal thin film transistor array, and when static electricity of a high voltage is applied, the protection is performed. It is possible to take measures against static electricity by guiding static electricity to the short bar due to conduction of the element.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a schematic configuration diagram showing a TFT array before cutting according to a first embodiment of the present invention, FIG. 2 is a schematic configuration diagram showing the TFT array after cutting, and FIG.
FIG. 4 is a plan view showing an example of the protection element of the FT array.
FIG. 5 is a voltage-current characteristic diagram of the protective element of FIG.

As shown in FIG. 1, the TFT array according to the first embodiment of the present invention comprises a plurality of address wirings 22 and data wirings 2 on an insulating transparent substrate 21 in a row direction and a column direction, respectively.
3 are arranged so as to intersect each other at right angles, and a plurality of TFTs 24 are connected at the intersections of the address wirings 22 and the data wirings 23, each of which has a gate electrode connected to the address wiring 22 and a drain electrode connected to the data wiring 23. A plurality of display electrodes 25 are arranged in a matrix and connected to the source electrodes of the TFTs 24.

A connecting terminal 26 for the address wiring 22 is provided on the outer peripheral portion of the insulating transparent substrate 21.
A protection element 28 having a high resistance or a non-linear resistance characteristic is connected to the outside of 6, and a short ring 30 is formed on the outside thereof. Similarly, a connection terminal 27 of the data wiring 23 is provided on the outer peripheral portion of the insulating transparent substrate 21, a protection element 28 having a high resistance or a non-linear resistance characteristic is connected to the outside of the connection terminal 27, and a short circuit is provided outside the connection. Ring 3
0 is formed.

The short ring 30 is cut and removed after the liquid crystal cell assembly process is completed. That is, the above-mentioned TFT
Using an Al-based material as the wiring material of the LCD, the wiring is connected to the short ring 30 outside the panel to prevent static electricity and to supply power at the time of gate anodic oxidation, and the connection with the short ring 30 is made at the time of scribing and breaking. A TFT array having a cutting end face 29 as shown in FIG. 2 is obtained by cutting along a cutting line B shown in FIG.

In this way, the connection terminals 26 and 27 of the address wiring 22 and the data wiring 23 and the metal wirings 22a and 2 are formed.
A protective element 28 having a high resistance or a non-linear resistance characteristic is connected between the cut end surface 29 of 3a. The protection element 28 having the high resistance or the non-linear resistance characteristic has a characteristic that it is in an OFF state at a normal driving voltage and is turned on when a high voltage such as static electricity is applied.

That is, when a high voltage due to static electricity is applied in the process of rubbing or the like, the protection element 28 having a high resistance or a non-linear resistance characteristic is turned on and the electric charge is released to the short ring 30 to protect the panel. It After scribing and breaking, as shown in FIG. 2, each wiring is exposed at the cut end face 29, but the protective element 28 having a high resistance or a non-linear resistance characteristic is O in the drive voltage range.
Since it is FF and the current that promotes corrosion is cut off,
Corrosion is prevented.

Regarding the address wiring 22 on the gate side,
After supplying power for anodic oxidation, the connection between the wiring and the short ring 30 may be temporarily disconnected and reconnected with the protection element 28 having high resistance or non-linear resistance characteristics. Further, when the gate side address wiring is drawn out only on one side of the panel, power may be supplied from the side where there is no drawing to oxidize, and then the wiring may be separated.

Next, a method of manufacturing the above-mentioned protective element 28 will be described with reference to FIGS. 3 and 4. Here, as the protection element 28, the space charge limiting current (Spac
Two-terminal device (hereinafter, SCLC) whose voltage-current characteristics are specified by eCharge Limited Current
The element 50 will be described as an example. For example, the SCLC element 50 formed outside the connection terminal 26 and connected between the metal wirings 22a exposed on the cut end face 29 of the thin film transistor array is configured as shown in FIGS. 3 and 4.

That is, an island-shaped semiconductor film 32 made of amorphous silicon is formed on the gate insulating film 31 covering the address wiring 22 formed on the insulating transparent substrate 21, and the semiconductor film 32 has two electrodes. And a semiconductor protective layer 33 for protecting the semiconductor film 32 is formed. On both sides of the semiconductor film 32 sandwiching the semiconductor protective layer 33, ohmic junction layers 34 made of semiconductors doped with impurities are formed. The electrodes 35 and 37 are formed via the electrodes 36 and 36.

The one electrode 35 is the gate insulating film 3
1 is connected to the metal wiring 22a by a connecting conductor 39 through the contact hole 31a.
2 extends to the cut end face 29. The other electrode 37 is connected to the inner metal wiring 22a by a connection conductor 38. These SCLC element 50 regions are covered with the protective film 40.
Covered with.

As described above, the SCLC element 50 as the protection element can be manufactured without adding any special material or special step in the manufacturing process of the thin film transistor array. In this SCLC element 50, as the voltage applied between both electrodes 35 and 37 becomes higher, the excess electrons injected into the amorphous silicon of the island-shaped semiconductor film 32 are absorbed into the band gap of the amorphous silicon. Space charges are formed by being trapped in a localized level. As a result, the Fermi level is displaced to the conductor, so that the conduction electron density is increased, and the current is not proportional to the voltage but sharply increases.

Such a current is called a space charge limiting current, and a semiconductor having a localized level such as amorphous silicon exhibits a large non-linear voltage-current characteristic as shown in FIG. In FIG. 5, the horizontal axis represents voltage (V) and the vertical axis represents current (A). Further, a non-linear element as shown in FIG. 6 may be used instead of the protective element shown in FIGS.

That is, as shown in FIG.
6, the protection element 28 connected between the metal wirings 22a exposed on the cut end face 29 of the thin film transistor array has an island-shaped base electrode 41 on the insulating transparent substrate 21, as shown in FIG. Formed, this base electrode 41
The diodes D1 and D2 facing upward are formed. That is, the p-type semiconductor layer 42p, the i-type layer 42i, and the n-type semiconductor layer 42n are deposited from the lower layer on the base electrode 41, covered with the insulating film 43, and the insulating film 43 is contacted by photolithography. Connection conductor 45
Thereby, the n-type semiconductor layer 42n of the diode D1 is connected to the metal wiring 22a, and the metal wiring 22a is exposed to the cut end surface 29 of the panel.

The n-type semiconductor layer 42 of the diode D2 is also provided.
n is connected to the metal wiring 22a on the connection terminal 26 side by the connection conductor 44. Then, the surface of the protective element 60 is covered with the protective film 46. Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 7 is a schematic configuration diagram of a TFT array showing a second embodiment of the present invention.

As shown in FIG. 7, in the TFT array showing the second embodiment of the present invention, a plurality of address wirings 62 and data wirings 63 are provided on the insulating transparent substrate 61 in the row direction and the column direction, respectively. They are arranged so as to intersect each other at right angles, and at the intersections of these address wirings 62 and data wirings 63,
A plurality of TFTs 64 each having a gate electrode connected to the address wiring 62 and a drain electrode connected to the data wiring 63 are arrayed, and a plurality of display electrodes 65 connected to the source electrode of the TFT 64 are arrayed in a matrix.

A connection terminal 66 of the address wiring 62 is provided on the outer peripheral portion of the insulating transparent substrate 61, and a protection element 68 having a high resistance or a non-linear resistance characteristic is connected to the outside of the connection terminal 66 and the outside thereof. Short ring 70
Are formed. Similarly, a connection terminal 67 of the data wiring 63 is provided on the outer peripheral portion of the insulating transparent substrate 61, a protection element 68 having a high resistance or a non-linear resistance characteristic is connected to the outside of the connection terminal 67, and a short circuit is provided outside thereof. A ring 70 is formed.

The short ring 70 is not cut even after the liquid crystal cell assembling process and is left as it is.
Since the protection element 68 is OFF in the range of the normal drive voltage, each wiring is electrically independent and no driving problem occurs. Further, for the same reason, the protective element 6 which has a high resistance or a non-linear resistance characteristic also acts on the current for promoting cathodic corrosion.
Corrosion does not occur because it is blocked at 8.

On the other hand, when a high voltage such as static electricity is applied, the protection element 68 is turned on, so that the protection element is protected against static electricity. With this configuration, since the panel has a protection effect against static electricity even after scribing and breaking of the panel, it is possible to take sufficient measures against static electricity in the modularization process.

Therefore, it is possible to obtain a highly reliable TFT array in terms of both static electricity and electrolytic corrosion. It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0032]

As described in detail above, according to the present invention, the following effects can be obtained. (1) It is possible to take measures against static electricity and prevent electrolytic corrosion of the Al-based wiring metal exposed on the end surface of the panel.

(2) In the first embodiment, the countermeasures against static electricity can be taken up to the scribing and breaking steps of the panel. (3) In the second embodiment, the above-mentioned measures against static electricity can be taken after the scribing and breaking steps of the panel. (4) The protective element can be incorporated in the panel without adding a special material and a special process in the manufacturing process of the thin film transistor array.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a TFT array before being cut, showing a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram showing a TFT array after being cut according to the first embodiment of the present invention.

FIG. 3 is a plan view showing an example of a protective element of the TFT array showing the first embodiment of the present invention.

4 is a cross-sectional view taken along the line AA of FIG.

FIG. 5 is a voltage-current characteristic diagram of the protective element of the TFT array showing the first embodiment of the present invention.

FIG. 6 is a sectional view of another protection element of the TFT array showing the first embodiment of the present invention.

FIG. 7 is a schematic configuration diagram of a TFT array showing a second embodiment of the present invention.

FIG. 8 is a schematic configuration diagram of a conventional TFT array.

FIG. 9 is a schematic configuration diagram showing a conventional TFT array before being cut.

FIG. 10 is a schematic configuration diagram showing a conventional TFT array after being cut.

FIG. 11 is a perspective view showing a cut end surface of a conventional TFT array.

[Explanation of symbols]

 21, 61 Insulating transparent substrate 22, 62 Address wiring 22a, 23a Metal wiring 23, 63 Data wiring 24, 64 TFT 25, 65 Display electrode 26, 27, 66, 67 Connection terminal 28, 60, 68 Protective element 29 Cut end face 30, 70 Short ring 31 Gate insulating film 31a Contact hole 32 Island-shaped semiconductor film 33 Semiconductor protective layer 34, 36 Ohmic junction layer 35, 37 Electrode 38, 39, 44, 45 Connection conductor 40, 46 Protective film 41 Island-shaped Base electrode 42p p-type semiconductor layer 42i i-type layer 42n n-type semiconductor layer 43 insulating film 50 SCLC element D1, D2 diode

Claims (2)

[Claims] 1. A thin film transistor and a display electrode connected to one of a source electrode and a drain electrode of the thin film transistor are provided at each intersection of a plurality of address lines and a plurality of data lines arranged to intersect each other. In a thin film transistor array in which a plurality of thin film transistors are arranged in a matrix and the address wiring is connected to the gate electrode of the thin film transistor and the data wiring is connected to the other of the source electrode and the drain electrode, respectively, (a) ends of the address wiring and the data wiring And (b) a protective element having a high resistance or a non-linear resistance characteristic, which is formed outside the connection terminal and is connected between the metal wirings exposed on the cut surface of the thin film transistor array. A thin film transistor array characterized by the above. 2. A thin film transistor and a display electrode connected to one of a source electrode and a drain electrode of the thin film transistor are provided at each intersection of a plurality of address lines and a plurality of data lines arranged to intersect each other. In a thin film transistor array in which a plurality of thin film transistors are arranged in a matrix and the address wiring is connected to the gate electrode of the thin film transistor and the data wiring is connected to the other of the source electrode and the drain electrode, respectively, (a) ends of the address wiring and the data wiring A connection terminal formed on the connection part, (b) a protection element connected to the outside of the connection terminal and having high resistance or nonlinear resistance characteristics, and (c) a short bar connected to the outside of the protection element. A thin film transistor array characterized by the above.