JPH08179358A - Active matrix panel - Google Patents

Abstract

(57) [Abstract] [Purpose] Anodize the surface of the gate electrodes of all protection TFTs that make up the protection element to prevent dielectric breakdown and characteristic changes of the pixel part due to static electricity, etc. Have a pressure resistance. [Structure] Constituting protective elements 50a, 50b, 50c 2
The gate electrodes of the two protection TFTs 51 and 52 are connected to the short line 7 formed on the surplus portion 1B of the substrate 1 and the relay electrode (electrode for connecting the data line 5 to the short line 7) 8 The gate electrodes of the protection TFTs 51 and 52 are oxidized by anodization using the short line 7 as a power supply path.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix panel used for an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, an active matrix panel used for an active matrix liquid crystal display device has the following structure. Incidentally, the liquid crystal display element is generally
It is manufactured by a manufacturing method that assembles a plurality of liquid crystal display elements at a time.The active matrix panel used when manufacturing a liquid crystal display element by this manufacturing method is of a size capable of collecting panels for a plurality of liquid crystal display elements. ing.

FIG. 8 is a plan view of an equivalent circuit of a conventional active matrix panel used in a liquid crystal display device manufactured by the above manufacturing method, and FIG. 9 shows each wiring and electrode of the active matrix panel. FIG. 10 is a diagram showing what is formed on the substrate by a solid line, and what is formed on the insulating film provided on the substrate by a broken line.
FIG. 4 is a diagram showing, among the wirings and electrodes, those formed on the insulating film by solid lines and those formed on the substrate by broken lines.

This active matrix panel includes a plurality of transparent pixel electrodes 2 arranged in a matrix on a transparent substrate 1 made of glass or the like, and a plurality of thin film transistors (hereinafter, referred to as T) connected to the pixel electrodes 2, respectively.
FT) 3, a plurality of gate wirings 4 wired for each pixel electrode row to supply a gate signal to the TFTs 3 of each row, and a data signal supplied to the TFTs 3 of each column wired for each pixel electrode column. A plurality of data wirings 5 to be supplied and a plurality of capacitor wirings 6 which are wired for each pixel electrode row and which form a compensation capacitance (storage capacitor) Cs between each pixel electrode 2 are provided. There is.

The above-mentioned substrate 1 is a large-sized substrate capable of collecting an active matrix panel for a plurality of liquid crystal display elements, and the active matrix panel portion of each liquid crystal display element corresponds to the size of the liquid crystal display element. Area (hereinafter, referred to as element area) 1A, and this element area 1
A surplus portion 1B secured around A, and the pixel electrode 2, the TFT 3, the gate, the data wiring 4,
5 and capacitor wiring 6 are provided in the element region 1A.

FIG. 11 is a plan view showing a concrete structure of one pixel portion of the active matrix panel, and FIG.
FIG. 12 is an enlarged sectional view taken along line XII-XII in FIG. As shown in FIGS. 11 and 12, the gate wiring 4 and the capacitor wiring 6 are wired on the substrate 1, and
Reference numeral 3 denotes a gate electrode 31 formed integrally with the gate wiring 4 on the substrate 1 and Si N covering the gate electrode 31.
A gate insulating film 32 made of (silicon nitride) or the like, an i-type semiconductor film 33 made of a-Si (amorphous silicon) formed on the gate insulating film 32 so as to face the gate electrode 31, and this i A source electrode 35 and a drain electrode 3 formed on the type semiconductor film 33 via an n-type semiconductor film 34 made of a-Si doped with impurities.
6 and 6. Reference numeral 37 is a channel protective film made of SiN or the like provided on the channel region of the i-type semiconductor film 33.

The gate insulating film 32 is formed on almost the entire surface of the substrate 1 so as to cover the gate wiring 4 and the capacitor wiring 6, and the terminal portion 4a of the gate wiring 4 (see FIG. 8).
Are exposed by forming an opening in the gate insulating film 32.

The pixel electrode 2 has the gate insulating film 3
2, the pixel electrode 2 is connected to the source electrode 35 by forming one end of the pixel electrode 2 on the source electrode 35 of the TFT 3.

Further, the data wiring 5 is the gate insulating film 3 described above.
The data wiring 5 is wired on top of the TFT 2.
3 is formed on the drain electrode 36 and connected to the drain electrode 36.

Reference numeral 35a denotes an upper electrode formed on the source electrode 35 and made of the same metal film as that of the data line 5. The upper electrode 35a electrically connects the pixel electrode 2 and the source electrode 35. In order to ensure reliable connection, the metal film is formed by etching while leaving the metal film also on the source electrode 35.

On the other hand, the capacitor wiring 6 faces the edge portion of the pixel electrode 2 from below and has the compensation capacitance C.
s is composed of the capacitor wiring 6, the pixel electrode 2 and the gate insulating film between them. Each capacitor wiring 6 is commonly connected at one end as shown in FIG. 8, and a terminal portion 6a connected to the reference potential is formed at the common connection portion.

The surplus portion 1B of the substrate 1 is a portion that is finally removed (after the liquid crystal display element is assembled by joining the active matrix panel and the counter panel), and the surplus portion 1B is It is divided and removed along a dividing line k along the contour of the element region 1A, which is indicated by a chain double-dashed line in the figure.

An alignment film (not shown) made of polyimide or the like is formed on the active matrix panel.
The alignment film is subjected to an alignment treatment by rubbing the film surface in one direction. In that case, static electricity generated during rubbing of the alignment film may cause dielectric breakdown in the TFT 3 or cause damage to the TFT 3. The voltage-current characteristics may change.

Therefore, in the above active matrix panel, by short-circuiting all the gate wirings 4 and the data wirings 5 in the surplus portion 1B of the substrate 1,
This prevents dielectric breakdown and characteristic changes of the TFT 3 due to static electricity.

That is, in the surplus portion 1B of the substrate 1, FIG.
As shown in FIG. 3, short lines 7 for short-circuiting all the gate lines 4 and the data lines 5 are formed, and each gate line 4 and each data line 5 are connected to the short line 7. In addition, this short line 7
Are formed in a lattice shape on the substrate 1 so as to surround the entire circumference of the element region 1A, and both ends of the vertical and horizontal line portions are extended to the outer peripheral edge portion of the substrate 1.

The short line 7 is as shown in FIG.
Formed on the substrate 1, each gate wiring 4 is connected to the vertical line portion of the short line 7 via a wiring portion extended from the terminal portion 4a to the surplus portion 1B.

Further, on the element region 1A of the substrate 1, as shown in FIG. 9, each data wiring 5 is connected to the short line 7 in correspondence with the location where the terminal portion 5a of each data wiring 5 is formed. The relay electrode 8 for doing so is integrally formed with the horizontal line portion of the short line 7. The relay electrode 8 is exposed by forming an opening in the gate insulating film 32.

Each data wiring 5 has its terminal portion 5
By forming a on the relay electrode 8 as described above,
It is connected to the short line 7 via the relay electrode 8.

In this way, if all the gate wirings 4 and the data wirings 5 are short-circuited in the surplus portion 1B of the substrate 1 via the short line 7, the potentials of these wirings 4 and 5 become the same. It is possible to prevent dielectric breakdown and characteristic changes of the TFT 3 due to static electricity or the like.

However, since the surplus portion 1B of the substrate 1 is removed after the liquid crystal display element is assembled, it can be removed during the subsequent manufacturing process of the liquid crystal display element or when the manufactured liquid crystal display element is mounted on an electronic device. When an object having a high voltage such as static electricity touches or comes close to the liquid crystal display element, the voltage may cause dielectric breakdown of the TFT 3 or change in characteristics.

Therefore, in the active matrix panel, in order to prevent the dielectric breakdown and the characteristic change of the TFT 3 due to static electricity or the like even after the surplus portion 1B is removed (after the short line 7 is cut off). ,
A short ring 9 for preventing static electricity is formed in a portion (inside the element region 1A) inside a surplus portion disconnection portion (disconnection line k) of the substrate 1 so as to surround the arrangement region of the pixel electrodes 2 and the TFTs 3, and the gate wiring 4 and The data wiring 5 is connected to the protection element 10
It is connected to the short ring 9 via a and 10b.

As shown in FIGS. 9 and 10, the short ring 9 has two lateral wiring portions 9a wired in parallel with the gate wiring 4 on the substrate 1 and the gate insulating film 32.
And two vertical wiring portions 9b wired in parallel with the data wiring 5, and the end portions of the horizontal wiring portions 9a and the vertical wiring portions 9b are provided in the gate insulating film 32 at the contact holes. (Not shown) are connected.

In FIG. 13, the gate wiring 4 is connected to the short ring 9
14 is a cross-sectional view of the protection element 10a connected to the short circuit 9 and FIG. 14 is a cross-sectional view of the protection element 10b connecting the data line 5 to the short ring 9. These protection elements 10a and 10b are two protection thin film transistors (hereinafter It is described as a TFT) 11 and 12.

Since the protective TFTs 11 and 12 constituting the protective elements 10a and 10b have basically the same structure as the TFT 3 of the pixel portion shown in FIGS. 11 and 12, the description of the structure will be omitted. Are denoted by the same reference numerals and omitted.

Protective TFTs 11 and 12 constituting a protective element 10a for connecting the gate wiring 4 to the short ring 9.
Are arranged on both sides of the gate wiring 4 on the terminal portion 4a side as shown in FIGS. 8 and 13, and the protection element 10a includes the gate electrodes 31 of the two protection TFTs 11 and 12, respectively. The source electrode 35 of the protection TFT
, The source electrode 35 of one protection TFT 11 is connected to the gate wiring 4, the drain electrode 36 is connected to the short ring 9, and the source electrode 35 of the other protection TFT 12 is connected to the short ring 9 and the drain electrode 36.
Is connected to the gate wiring 4.

Gate wiring 4 of the protection TFTs 11 and 12
Electrode connected to, that is, the source electrode 35 of the one protection TFT 11 and the drain electrode 3 of the other protection TFT 12.
6 indicates the gate wiring 4 in the contact hole 39 formed in the gate insulating film 32 through the common gate wiring connecting film 38.
The drain electrode 36 of one protection TFT 11 and the source electrode 35 of the other protection TFT 12 are connected to
Is provided on the vertical wiring portion 9b of the short ring 9, and the short ring connection films 40 and 41 integrally formed on the vertical wiring portion 9b.
Connected through. The gate wiring connection film 38, the vertical wiring portion 9b of the short ring 9 and the short ring connection films 40 and 41 are formed of the same metal film as the data wiring 5.

The gate electrode 31 of the one protection TFT 11 is formed integrally with the gate wiring 4, and is electrically connected to the source electrode 35 of the protection TFT 11 via the gate wiring 4 and the gate wiring connection film 38. The gate electrode 31 of the other protection TFT 12 is connected to the gate electrode 31 in the contact hole (not shown) in which the vertical wiring portion 9b of the short ring 9 is provided in the gate insulating film 32.
It is electrically connected to the source electrode 35 of the protective TFT 12 through the short ring 9 and the short ring connection film 41 by connecting to the lead portion derived from.

Further, the protective TFTs 11 and 1 constituting the protective element 10b for connecting the data wiring 5 to the short ring 9 are provided.
As shown in FIGS. 8 and 14, 2 is arranged on both sides of the data wiring 5 on the side of the terminal portion 5a, and the protection element 10b includes the gate electrodes 31 of the two protection TFTs 11 and 12. Source electrode 3 of each protection TFT
5 electrically connected to one of the protection TFTs 11
Source electrode 35 to data line 5 and drain electrode 36
Is connected to the short ring 9, the source electrode 35 of the other protective TFT 12 is connected to the short ring 9, and the drain electrode 3 is connected.
6 is connected to the data wiring 5.

Data wiring 5 of the protection TFTs 11 and 12
Electrode connected to, that is, the source electrode 35 of the one protection TFT 11 and the drain electrode 3 of the other protection TFT 12.
6 is connected to the data wiring 5 via a data wiring connection film 42 formed integrally with the data wiring 5, and the drain electrode 36 of one protection TFT 11 and the source electrode 35 of the other protection TFT 12 are connected to each other. , And is connected to the lateral wiring portion 9a of the short ring 9 through the short ring connection films 43 and 44 made of the same metal film as the data wiring 5. Since the lateral wiring portion 9a of the short ring 9 is wired on the substrate 1, the short ring connection film 4 is formed.
3, 44 are connected to the lateral wiring portion 9a through contact holes (not shown) provided in the gate insulating film 32.

Further, the gate electrode 31 of the one protection TFT 11 is formed so as to extend below the data line 5 to which the source electrode 35 of the protection TFT 11 is connected. The gate electrode 31 of the one protection TFT 11 is Contact hole 45 in which the data wiring 5 is provided in the gate insulating film 32
By connecting to the extension of the gate electrode 31 in, the source electrode 35 of the protective TFT 11 is electrically connected via the data line 5.

The gate electrode 31 of the other protective TFT 12 is formed integrally with the lateral wiring portion 9a of the short ring 9, and the protective TFT 12 is provided via the short ring 9.
Is electrically connected to the source electrode 35.

In the protection elements 10a and 10b, when a high voltage such as static electricity is applied to the gate wiring 4 or the data wiring 5, one of the two protection TFTs 11 and 12 is turned on and the gate wiring 4 and the data wiring 5 are turned on. 5 and 5 are electrically connected via the short ring 9. For example, when a high voltage is applied to the gate wiring 4, the protection element 1 on the gate wiring 4 side is provided.
One of the protection TFTs 11a of 0a is turned on to electrically connect the gate wiring 4 and the short ring 9 to each other, and a voltage applied from the gate wiring 4 to the short ring 9 causes the other protection TFT 12 of the protection element 10a on the data wiring 5 side. In the ON state, the data line 5 and the short ring 9 are electrically connected, the potentials of the gate line 4 and the data line 5 become the same, and the dielectric breakdown and the characteristic change of the TFT 3 of the pixel portion due to static electricity or the like are prevented. .

The liquid crystal display element is driven by sequentially supplying a gate signal to each gate wiring 4 and supplying a data signal to each data wiring 5 in synchronization with the gate signal, but the protection elements 10a and 10b are driven. , The gate electrodes 31 of both protection TFTs 11 and 12 are respectively the source electrodes 3 of the protection TFTs.
Since these are connected to 5, the protection TFT 11,
12 does not turn on at about the voltage of the gate signal and the data signal, and therefore the gate wiring 4 and the data wiring 5 are shorted by the short ring 9 via the protection elements 10a and 10b.
Connection to the liquid crystal display element does not affect the display drive of the liquid crystal display element.

The active matrix panel is manufactured by the following manufacturing method. First, a metal film made of an Al (aluminum) -based alloy or the like is formed on the substrate 1, and the metal film is patterned to form the gate line 4 and the gate electrode 31 of the TFT 3 in the pixel portion shown by the solid line in FIG. , Capacitor wiring 6, short line 7, relay electrode 8 for connecting data wiring 5 to short line 7, lateral wiring portion 9a of short ring 9, protective TFT 1
Gate electrodes 31 of 1 and 12 are simultaneously formed.

Next, the gate wiring 4 and T of the pixel portion
The gate electrode 31 of FT3 is anodized to form an oxide film on its surface. In FIG. 12, a is an oxide film generated by the anodizing process, and this oxide film a
Are formed to supplement the withstand voltage of the gate insulating film 32 thereabove.

In the anodic oxidation treatment, the substrate 1 is immersed in an electrolytic solution, and the film to be oxidized (the gate wiring 4 and the gate electrode 31 of the TFT 3 in the pixel portion) on the substrate 1 is made to face the cathode in the electrolytic solution. In this state, a positive voltage with respect to the potential of the counter electrode is applied to the film to be oxidized.

The voltage is applied to the film to be oxidized in the anodic oxidation process by using the short line 7 as a power supply path. A voltage is supplied to the gate electrode 31 of the TFT 3 of each pixel portion, and these oxidized films cause a chemical conversion reaction in the electrolytic solution to anodize the surface thereof.

In this case, of the protection elements 10a and 10b, one protection T of the protection element 10a on the gate wiring 4 side is provided.
Since the gate electrode 31 of the FT 11 is formed integrally with the gate wiring 4, the gate electrode 31 of the protection TFT 11 is
Is also anodized at the same time, and the oxide film a (FIG.
).

Further, the common connection portion of each capacitor wiring 6 is formed in a pattern in which the end portion is connected to the short line 7. Therefore, the surface of each capacitor wiring 6 is also anodized at the same time by the anodizing treatment. It

The short line 7 has a relay electrode 8 for connecting the data line 5 to the short line 7.
However, if the relay electrode 8 is covered with a resist, the surface thereof will not be anodized, and the terminal portion 4a of the gate wiring 4 and the terminal portion 6a of the capacitor wiring 6 will not be resisted. If they are covered with, the surfaces of these terminal portions 4a and 6a will not be anodized.

After the above-mentioned anodizing treatment, the substrate 1
A gate insulating film 32, an i-type semiconductor film 33, and a channel protective film 37 are sequentially formed on the above, and the channel protective film 37 is formed.
Is patterned into a shape that covers the channel region of the i-type semiconductor film 33 of the TFT 3 of the pixel portion and the protective TFTs 11 and 12.

Next, an n-type semiconductor film 34 is formed, a metal film made of Cr (chromium) or the like is formed on the n-type semiconductor film 34, and then the metal film is patterned to form the TFT 3 in the pixel portion and each protective TFT 11, 12 source electrode 35 and drain electrode 36 are formed, and then the n-type semiconductor film 34 is patterned into the same shape as the source and drain electrodes 35 and 36 to form the TFT 3 in the pixel portion and the protective TFTs 10a and 10a.
Complete b.

Next, a transparent conductive film made of ITO or the like is formed, and the transparent conductive film is patterned to form each pixel electrode 2. After that, the gate wiring 4 and the capacitor wiring 6 are formed on the gate insulating film 32. Of the terminal portions 4a, 6a and the relay electrode 8 and the contact holes 3 described above.
9 and 45 are formed.

After that, a metal film made of an Al-based alloy or the like is formed, and this metal film is patterned to form the data wiring 5 and the gate wiring connection film 3 of each protection element 10a, 10b.
8, the short ring connection films 40, 41, 43, 44 and the data wiring connection film 42 are formed to complete the active matrix panel.

[0045]

However, in the above-mentioned conventional active matrix panel, since the short ring 9 must be provided in the element region 1A, in order to prevent dielectric breakdown or characteristic change of the TFT in the pixel portion due to static electricity or the like. However, there is a problem that the wiring structure that constitutes the protection circuit becomes complicated.

In the manufacturing process of the conventional active matrix panel, the gate electrode 31 of the gate wiring 4 and the TFT 3 of the pixel portion and the gate electrode 31 of the one protection TFT 11 of the protection element 10a on the gate wiring 4 side are formed. The surface can be anodized, but the gate electrode 3 of the other protective TFT 12 of the protective element 10a on the side of the gate wiring 4
1 and both protection T of the protection element 10b on the data wiring 5 side
There is a problem that the gate electrodes 31 of the FTs 11 and 12 cannot be anodized.

This is the protection element 10a on the gate wiring 4 side.
Since the gate electrode 31 of the other protection TFT 12 and the gate electrodes 31 of both protection TFTs 11 and 12 of the protection element 10b on the data wiring 5 side are individually formed as shown by the solid line in FIG. This is because a voltage for anodizing cannot be supplied to these gate electrodes 31.

Therefore, in the above-mentioned conventional active matrix panel, the protective TFT 12 on the other side of the protective element 10a on the gate wiring 4 side and the protective element 10 on the data wiring 5 side are provided.
It was not possible to provide both the protection TFTs 11 and 12 of b with a sufficient withstand voltage.

The present invention is directed to the TF of the pixel portion due to static electricity or the like.
The purpose of the present invention is to obtain an active matrix panel in which a protective circuit for preventing the dielectric breakdown of T and a change in characteristics is formed by a simple structure, and a plurality of protective TFTs constituting a protective element of the protective circuit. It is an object of the present invention to provide a highly reliable active matrix panel in which the surface of a gate electrode is anodized so that these protective TFTs have a sufficient withstand voltage.

[0050]

An active matrix panel according to the present invention includes a plurality of pixel electrodes, a plurality of TFTs respectively connected to the pixel electrodes, and a plurality of the plurality of pixel electrodes on a substrate on which a liquid crystal display element is formed. A plurality of gate wirings for supplying a gate signal to the TFT and a plurality of data wirings for supplying a data signal to the plurality of TFTs are provided,
The gate wiring and the data wiring, which are adjacent to each other of the gate wiring and the data wiring, and the gate wiring and the data wiring at each group end of the gate wiring group including the plurality of gate wirings and the data wiring group including the plurality of data wirings, Each of them is characterized in that the gate electrode and the source electrode are connected via a protective element in which two protective TFTs electrically connected to each other are connected in series.

Further, in the active matrix panel of the present invention, a plurality of element regions are formed on the substrate having a surplus portion which is removed after the liquid crystal display device is assembled around the element region corresponding to the size of the liquid crystal display device. A pixel electrode and a plurality of TFTs respectively connected to these pixel electrodes,
A plurality of gate wirings for supplying a gate signal to the plurality of TFTs and a plurality of data wirings for supplying a data signal to the plurality of TFTs are provided, and the gate wirings and the data wirings adjacent to each other, The gate wiring and the data wiring at the end of each of the gate wiring group including the plurality of gate wirings and the data wiring group including the plurality of data wirings are electrically connected to the gate electrode and the source electrode, respectively. The two protection TFTs are connected via a protection element, and the protection element connects the drain electrodes of the two protection TFTs to each other, and connects the source electrode of one protection TFT to one wiring, The source electrode of the other protection TFT is connected to the other wiring, and all the data distribution is on the surplus portion of the substrate. And a short line for short-circuiting the data lines are formed, on the element region of the substrate relay electrode for connecting the data lines to the short line is formed integrally with the short lines,
The gate wiring is formed on the substrate and connected to the short line at an end thereof, and the data wiring is formed on an insulating film provided on the substrate and connected to the relay electrode. The gate electrode of the TFT connected to the pixel electrode is formed integrally with the gate wiring, and the gate electrodes of the two protective TFTs forming the protection element are integrated with either the gate electrode or the relay electrode. It is characterized in that the electrode surface is oxidized by anodic oxidation treatment using the short line as a power feeding path.

[0052]

That is, in the active matrix panel of the present invention, the adjacent gate wirings and data wirings, and the gate wirings and data wirings at the end of each of the gate wiring group and the data wiring group are connected to the gate electrodes. Since the source electrode is directly connected by the protective element formed by the series connection of the two protective TFTs electrically connected to each other, these protective TFs are protected when static electricity is applied.
Since T is conductive and the potential of the gate line and the data line is substantially the same, it is not necessary to provide a short ring as in the conventional case.
This simplifies the configuration of the protection circuit for preventing the dielectric breakdown and characteristic changes of the.

Further, in the active matrix panel of the present invention, the protective element is constructed as described above, and the gate electrodes of the two protective TFTs constituting this protective element are connected to the short line formed on the surplus portion of the substrate. The gate electrode of the protective TFT is oxidized by anodization treatment using the short line as a power feeding path by integrally forming the gate wiring and the relay electrode connected to each other. According to the panel, since the surfaces of the gate electrodes of all the protection TFTs constituting the protection element are anodized, these protection TFTs can have a sufficient withstand voltage.

[0054]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.
Will be described with reference to. FIG. 1 is an equivalent circuit plan view of the active matrix panel of this embodiment, and FIG.
Of the respective wirings and electrodes of the active matrix panel, those formed on the substrate are shown by solid lines, and those formed on the insulating film provided on the substrate are shown by broken lines. Of the respective wirings and electrodes, those formed on the insulating film are shown by solid lines, and those formed on the substrate are shown by broken lines.

8 to 10 in FIGS. 1 to 3.
The components provided in the conventional active matrix panel shown in (1) are assigned the same reference numerals in the drawings, and detailed description thereof will be omitted.

In the active matrix panel of this embodiment, the element region 1A of the substrate 1 has a surplus portion 1B which is removed around the element region 1A corresponding to the size of the liquid crystal display element after the liquid crystal display element is assembled. A plurality of pixel electrodes 2, a plurality of TFTs 3 connected to each of the pixel electrodes 2, a gate wiring 4 for supplying a gate signal to the TFT 3, and a data wiring 5 for supplying a data signal to the TFT 3 are provided. In addition, the gate wiring 4 and the data wiring 5 which are adjacent to each other, and the gate wiring 4 and the data wiring 5 at the end of each of the gate wiring group and the data wiring group (the uppermost gate wiring and the left end in FIG. 1). Data wiring) and protective elements 50a, 50b, 50c having non-linear voltage-current characteristics such as diodes, respectively.
And the protection elements 50a, 5
0b and 50c have the following configurations.

FIG. 4 is a sectional view of the protective element 50a connecting the adjacent gate wirings 4 to each other, FIG. 5 is a sectional view of the protective element 50b connecting the adjacent data wirings 5 to each other, and FIG. 6 is a gate wiring at the end of the wiring group. 4 is a cross-sectional view of a protective element 50c that connects the data wiring 5 and the data wiring 5, and FIG.
b and 50c are two protection TFTs 51 and 52, respectively.
It is composed of

The protective TFTs 51 and 52 constituting these protective elements 50a, 50b and 50c are the same as those shown in FIGS.
It has the same structure as the TFT 3 of the pixel portion shown in FIG. 1, and has a gate electrode 31 formed on the substrate 1, a gate insulating film 32 covering the gate electrode 31, and a gate insulating film 32 on the gate insulating film 32. An i-type semiconductor film 33 formed facing the gate electrode 31, a channel protection film 37 provided on a channel region of the i-type semiconductor film 33,
The source electrode 35 and the drain electrode 36 are formed on the i-type semiconductor film 33 with the n-type semiconductor film 34 interposed therebetween.

As shown in FIGS. 1 and 4, the protective TFTs 51 and 52 which form the protective element 50a for connecting the gate wirings 4 to each other are arranged between the terminal portions 4a of two adjacent gate wirings 4, respectively. This protection element 50a
Electrically connects the gate electrodes 31 of the two protection TFTs 51 and 52 to the source electrodes 35 of the protection TFTs, respectively, and connects the drain electrodes 36 of the protection TFTs 51 and 52 to each other, and the source electrode of one of the protection TFTs 51. 35 is connected to one gate wiring 4 and the other protection T
The source electrode 35 of the FT 52 is connected to the other gate wiring 4.

The drain electrodes 36 of the protection TFTs 51 and 52 are connected by the drain electrode connection film 53, and the source electrodes 35 of the protection TFTs 51 and 52 are respectively connected via the gate wiring connection film 54 to the gate insulating film 32.
It is connected to the gate wiring 4 in the contact hole 55 provided in the. The drain electrode connection film 53 and the gate wiring connection film 54 are formed of the same metal film as the data wiring 5.

The gate electrode 31 of the one protection TFT 51 is formed integrally with the one gate wiring 4 and is electrically connected to the source electrode 35 of the protection TFT 11 through the gate wiring 4 and the gate wiring connection film 54. The gate electrode 31 of the other protective TFT 52 is integrally formed with the other gate wiring 4 and electrically connected to the source electrode 35 of this protective TFT 52 through the gate wiring 4 and the gate wiring connection film 54. Connected to each other.

Further, as shown in FIGS. 1 and 5, the protective TFTs 51 and 52, which form the protective element 50b for connecting the data wirings 5 to each other, are located between the terminal portions 5a of two adjacent data wirings 5, as shown in FIGS. It is arranged and this protection element 50b
Electrically connects the gate electrodes 31 of the two protection TFTs 51 and 52 to the source electrodes 35 of the protection TFTs, respectively, and connects the drain electrodes 36 of the protection TFTs 51 and 52 to each other, and the source electrode of one of the protection TFTs 51. 35 is connected to one data wiring 5 and the other protection T
The source electrode 35 of the FT 52 is connected to the other data line 5.

The drain electrodes 36 of the protection TFTs 51 and 52 are connected to each other by the drain electrode connection film 53 made of the same metal film as the data wiring 5, and both the protection TFTs 5 are protected.
The source electrodes 35 of 1, 52 are respectively connected to the data wiring 5 through a data wiring connection film 56 formed integrally with the data wiring 5.

The gate electrodes 31 of both the protection TFTs 51 and 52 are lead portions 8 derived from the relay electrodes 8 for connecting the data lines 5 to the short lines 7, respectively.
The gate electrodes 31 of the protection TFTs 51 and 52 are integrally formed on the gate wiring a, and the gate electrodes 31 of the protection TFTs 51 and 52 connect the data wiring 5 to the gate insulating film 3
2 in the contact hole 57 provided in
By connecting to the relay electrode 8 and the data wiring 5
Is electrically connected to the source electrodes 35 of the respective protection TFTs 51 and 52 via.

Further, the protective TFT 5 which constitutes the protective element 50c for connecting the gate wiring 4 and the data wiring 5 at the end of the wiring group
As shown in FIGS. 1 and 6, the reference numerals 1 and 52 are arranged between the gate wiring 4 and the data wiring 5 on the side of the terminal portions 4a and 5a, and the protection element 50c includes two protection TFTs.
The gate electrodes 31 of 51 and 52 are respectively provided as protection TFTs thereof.
Of the protective TFTs 51 and 52, the drain electrodes 36 of the protective TFTs 51 and 52 are connected to each other, the source electrode 35 of one protective TFT 51 is connected to the gate wiring 4, and the source electrode of the other protective TFT 52 is connected. 35 is connected to the data wiring 5.

In this protection element 50c, the side connected to the gate wiring 4 has the same structure as the right side portion of the protection element 50a shown in FIG. 4, and the side connected to the data wiring 5 is shown in FIG. Since it has the same configuration as the left side portion of the protection element 50b, duplicate description will be omitted by giving the same reference numerals to the drawings.

Further, each of the protection elements 50a, 50b, 5
Gate electrodes 31 of all protection TFTs 51 and 52 of 0c
Is subjected to anodic oxidation using the short line 7 formed in the surplus portion 1B of the substrate 1 as a power supply path, and the electrode surface is removed along with the gate wiring 4 and the gate electrode 31 (see FIG. 12) of the TFT 3 in the pixel portion and the capacitor wiring 6. Anodized.

The anodizing process is performed by the data wiring 5
Is also applied to the lead portion 8a which is led out from the relay electrode 8 for connecting the gate line 4 to the short line 7 and is connected to the gate electrode 31 of the protective TFTs 51 and 52. The lead portion 8a of the relay electrode 8 is anodized except for the connection portion of the wiring connection film 54 (the portion corresponding to the contact hole 55), and the lead portion 8a of the relay electrode 8 is the connection portion of the data wiring 5 (the portion corresponding to the contact hole 57). Except anodized.

In FIGS. 4 to 6, a is an oxide film formed by the anodizing process, and the part where the oxide film a is formed is slightly smaller than the non-oxidized part due to the increase in volume due to the oxidation of the metal film. It's excited.

The protection elements 50a, 50b and 50c are
When a high potential difference such as an electrostatic voltage is generated between the two wirings connected via this protection element, the two protection TFTs 51 and 52 are turned on to electrically connect the two wirings. And, for example, all gate wiring 4
When a high voltage such as static electricity is applied to the gate wiring 4, the gate wiring 4 and the data wiring 5 at the end of the wiring group are electrically connected via the protection element 50c, and the wirings 4 and 5 have the same potential. The potential change of the gate wiring 4 and the data wiring 5 at the end of the wiring group causes the gate wiring 4 and the data wiring 5 to change.
A potential difference is generated between the gate wiring 4 and the next data wiring 5 and the data wiring 5, and the gate wirings 4 and 4 and the data wirings 5 and 5 are electrically connected via the protection elements 50a and 50b. The gate wiring 4 and the data wiring 5 are sequentially brought into conduction, and all the potentials of the gate wiring 4 and the data wiring 5 become the same.

This is the same when a high voltage is applied to a part of the gate wiring 4 or the data wiring 5, and in this case, the wiring to which the high voltage is applied and the next wiring are electrically connected,
By repeating this, all the gate wirings 4 and the data wirings 5 are sequentially conducted, and the potentials of all the gate wirings 4 and the data wirings 5 become the same.

Therefore, the gate wiring 4 and the data wiring 5 which are adjacent to each other, and the gate wiring 4 and the data wiring 5 at the end of each of the gate wiring group and the data wiring group are connected to the protection elements 50a, 50b and 50c. If the connection is made via T, even after the surplus portion 1B of the substrate 1 is removed (after the short line 7 is cut off), the T
It is possible to prevent dielectric breakdown and characteristic changes of FT3.

Then, according to the present embodiment, the gate wiring 4
And between the adjacent wirings of the data wirings 5 and between the gate wirings 4 and the data wirings 5 at the end of each of the gate wiring group and the data wiring group.
Two protective TFTs 51 and 52 electrically connected to
Protective elements 50a, 50 configured by serial connection of
Since they are directly connected by b and 50c, when static electricity is applied, these protection TFTs 51 and 52 become conductive and the gate wiring 4 and the data wiring 5 are substantially at the same potential. Unlike the panel, it is not necessary to provide a short ring, and therefore, the structure of the protection circuit for preventing the dielectric breakdown or the characteristic change of the TFT 3 in the pixel portion due to static electricity or the like becomes simple.

The protective elements 50a, 50b, 50
In c, both of the protection TFTs 51 and 52 are obtained by connecting the gate electrode 31 to the source electrode 35 of the protection TFT, so that the protection TFTs 51 and 52 do not turn on at about the voltage of the gate signal and the data signal. , The gate wiring 4 and the data wiring 5 are the protection elements 5
Even if they are connected via 0a, 50b, and 50c, they do not affect the display drive of the liquid crystal display element.

The active matrix panel is manufactured by the following manufacturing method. First, a metal film made of an Al-based alloy or the like is formed on the substrate 1, and the metal film is patterned to form the gate wiring 4 and the gate electrode 31 of the TFT 3 in the pixel portion and the capacitor wiring shown by the solid line in FIG. 6,
Short line 7, relay electrode 8 for connecting data line 5 to short line 7 and lead portion 8a thereof, and protective TFT 5 of all protective elements 50a, 50b, 50c
1, 52 gate electrodes 31 are simultaneously formed.

In this step, the gate wiring 4, the capacitor wiring 6, and the relay electrode 8 are all formed integrally with the short line 7, and the gate electrode 31 of the TFT 3 in the pixel portion is formed.
And the gate electrodes 31 of both protection TFTs 51 and 52 of the protection element 50a and the gate electrode 31 of the other protection TFT 52 of the protection element 50c are formed integrally with the gate wiring 4, and the protection TFT 51 of one protection TFT 51 of the protection element 50c. Gate electrode 3
1 and the gate electrodes 31 of both protective TFTs 51 and 52 of the protective element 50b are formed integrally with the lead portion 8a of the relay electrode 8.

Next, the gate wiring 4 and the T of the pixel portion are
The gate electrode 31 of FT3 and all the protection TFTs 51 and 5
2 of the gate electrode 31, the lead portion 8a of the relay electrode 8,
The capacitor wiring 6 and the capacitor wiring 6 are simultaneously anodized to form an oxide film a on their surfaces.

This anodic oxidation treatment is performed by connecting the terminal portion 4a of the gate wiring 4 and the connecting portion of the gate wiring connecting film 54, the data wiring connecting portion of the relay electrode 8 and its lead portion 8a, and the terminal portion of the capacitor wiring 6. 6a and 6 are masked with a resist,
The substrate 1 is immersed in an electrolytic solution, and the film to be oxidized (the gate wiring 4, the capacitor wiring 6, the gate electrode 31, etc.) on the substrate 1 is made to face the cathode in the electrolytic solution, and the short line 7 is used as a power feeding path. This is performed by applying a positive voltage to the oxide film with respect to the potential of the counter electrode.

As described above, when the voltage is supplied to the short line 7, the voltage is supplied to the gate line 4, the capacitor line 6, and the relay electrode 8 connected to the short line 7, and the gate line is connected. 4 and the TFT 3 and the protection TFT 5 of the pixel portion formed integrally
1, 52 and the gate electrode 31 of the protective TFTs 51, 52 integrally formed with the relay electrode 8.
Is applied with the above voltage, and the film to be oxidized undergoes a chemical conversion reaction in the electrolytic solution to anodize the surface thereof.

After the above anodizing treatment, the substrate 1
A gate insulating film 32, an i-type semiconductor film 33, and a channel protective film 37 are sequentially formed on the above, and the channel protective film 37 is formed.
Is patterned into a shape that covers the channel region of the i-type semiconductor film 33 of the TFT 3 of the pixel portion and the protective TFTs 51 and 52.

Next, an n-type semiconductor film 34 is formed, a metal film made of Cr or the like is formed on the n-type semiconductor film 34, and then the metal film is patterned to form the TFT 3 and each protective TFT 5 in the pixel portion.
1, 52, the source electrode 35 and the drain electrode 36 are formed, and then the n-type semiconductor film 34 is patterned into the same shape as the source and drain electrodes 35, 36 to form the TFT 3 and the protective TFTs 50a, 50b, 50c in the pixel portion. Complete.

Next, a transparent conductive film made of ITO or the like is formed, and the transparent conductive film is patterned to form each pixel electrode 2, and then the gate wiring 4 and the capacitor wiring 6 are formed on the gate insulating film 32. Of the terminal portions 4a, 6a and the relay electrode 8 and the contact holes 5 described above.
5 and 57 are formed.

After that, a metal film made of an Al-based alloy or the like is formed, and the metal film is patterned to connect the data wiring 5, the drain electrode connection film 53 of each protection element 50a, 50b, 50c, and the gate wiring connection. The film 54 and the data wiring connection film 56 are simultaneously formed to complete the active matrix panel.

That is, in the above active matrix panel, the protective elements 50a, 50b and 50c are constructed as described above, and the two protective TFTs constituting this protective element are arranged.
By forming the gate electrodes 31 of 51 and 52 integrally with either the gate wiring 4 or the relay electrode 8 connected to the short line 7 formed on the surplus portion 1B of the substrate 1, the short line 7 is formed. The gate electrodes 31 of the protection TFTs 51 and 52 are processed by anodizing to form a power supply path.
According to this active matrix panel, the protective elements 50a, 50b,
Since the surfaces of the gate electrodes 31 of all the protection TFTs 51 and 52 constituting the 50c are anodized, these protection T
Since the FTs 51 and 52 can have sufficient withstand voltage, the reliability of the active matrix panel can be improved.

In the above embodiment, the gate wiring (uppermost gate wiring in FIG. 1) 4 at one group end of the gate wiring group and the data wiring (left end in FIG. 1) at one group end of the data wiring group. The data wiring 5) is connected via the protective element 50c, but the gate wiring 4 and the data wiring 5 connect the wirings 4 and 5 at the other end of the wiring group to the protective element 50c. You may connect through.

FIG. 7 is an equivalent circuit plan view of an active matrix panel showing a second embodiment of the present invention. In this embodiment, the gate wirings 4 at both ends of the gate wiring group and the data wirings are shown. The data wirings 5 at both ends of the group are connected to each other via the protective element 50c.

In this embodiment, of the group end gate wiring 4 and the data wiring 5, the protection element 50 for connecting the lowermost gate wiring 4 and the rightmost data wiring 5 in the figure.
In c, the one protection TFT 51 is arranged near the terminal portion 4a side of the gate wiring 4, the other protection TFT 52 is arranged near the terminal portion 5a side of the data wiring 5, and the protection TFTs 51 and 52 are arranged. The drain electrodes are connected to each other by a drain electrode connection film 53 'which is formed in a wiring shape and circumscribes the outside of the pixel array region (display region).

In the protection element 50c, the distance between the protection TFTs 51 and 52 of the protection element 50c shown in FIG. 6 is increased and the drain electrode connection film 53 is lengthened to bypass the outside of the pixel array region. Since it is formed in a wiring shape and is substantially the same as the protection element 50c shown in FIG. 6, the description of the configuration is omitted.

The active matrix panel of this embodiment is the same as that of the first embodiment shown in FIGS. 1 to 6 except that the gate wiring 4 and the data 5 at the other end of the gate wiring group and the data wiring group. Since the protection element 50c for connecting to and is added and the other structure is the same as that of the first embodiment, the duplicated description will be omitted by giving the same reference numerals to the drawings.

Further, in the above-mentioned embodiment, the gate wirings 4 and the data wirings 5 adjacent to each other, and the gate wirings 4 at the end of each of the gate wiring group and the data wiring group.
And a data line 5 are connected to the protective element 50a,
50b and 50c are provided on the side of the terminals 4a and 5a of the gate wiring 4 and the data wiring 5, respectively.
0a, 50b, 50c may be provided on the opposite side of the terminal portions 4a, 5a of the gate wiring 4 and the data wiring 5, or may be provided on both ends of the gate wiring 4 and the data wiring 5.

Further, in the above embodiment, the data line 5, the drain electrode connection film 53 of each protection element 50a, 50b, 50c, the gate line connection film 54, and the data line connection film 56.
Are formed on the gate insulating film 32, and these are formed by forming an interlayer insulating film on the gate insulating film 32 and forming a contact hole on the interlayer insulating film. Source of the TFT and protection TFTs 51 and 52 of
It may be connected to the drain electrodes 35 and 36 and the data wiring 5.

[0092]

According to the active matrix panel of the present invention, the adjacent gate wirings and data wirings, and the gate wirings and data wirings at the end of each of the gate wiring group and the data wiring group are used as the gate electrodes. Since the protection element constituted by the series connection of the two protection TFTs electrically connected to the source electrode is directly connected, when the static electricity is applied, these protection TFTs are electrically connected and substantially gate Since the wiring and the data wiring have the same potential, it is not necessary to provide a short ring as in the conventional case. Therefore, the structure of the protection circuit for preventing the dielectric breakdown and the characteristic change of the TFT in the pixel portion due to static electricity is simplified. Become.

Further, in the active matrix panel of the present invention, the protective element for preventing the dielectric breakdown and the characteristic change of the pixel portion due to static electricity and the like, the gate electrodes of the two protective TFTs are electrically connected to the source electrodes of the protective TFTs. And the drain electrodes of these protective TFTs are connected to each other, the source electrode of one protective TFT is connected to one wiring, and the source electrode of the other protective TFT is connected to the other wiring. By forming the gate electrodes of the two protective TFTs forming the element integrally with either the gate wiring connected to the short line formed on the surplus portion of the substrate or the relay electrode, the short line is connected to the feed line. The protection T by the anodizing treatment
The surface of the gate electrode of the FT is oxidized. According to this active matrix panel, the surface of the gate electrode of all the protection TFTs constituting the protection element is anodized. Withstand voltage can be increased.

[Brief description of drawings]

FIG. 1 is an equivalent circuit plan view of an active matrix panel showing a first embodiment of the present invention.

FIG. 2 is a diagram in which, among wirings and electrodes of the active matrix panel, those formed on a substrate are shown by solid lines, and those formed on an insulating film provided on the substrate are shown by broken lines. .

FIG. 3 is a diagram in which, of the respective wirings and electrodes of the active matrix panel, those formed on an insulating film are shown by solid lines, and those formed on a substrate are shown by broken lines.

FIG. 4 is a cross-sectional view of a protection element that connects gate wirings.

FIG. 5 is a cross-sectional view of a protection element that connects data lines to each other.

FIG. 6 is a cross-sectional view of a protection element that connects a gate wiring and a data wiring.

FIG. 7 is an equivalent circuit plan view of an active matrix panel showing a second embodiment of the present invention.

FIG. 8 is a plan view of an equivalent circuit of a conventional active matrix panel.

FIG. 9 shows wiring lines and electrodes of a conventional active matrix panel which are formed on a substrate by a solid line and those which are formed on an insulating film provided on the substrate by a broken line. Fig.

FIG. 10 is a diagram in which, among wirings and electrodes of a conventional active matrix panel, those formed on the insulating film are shown by solid lines, and those formed on the substrate are shown by broken lines.

FIG. 11 is a plan view showing a specific configuration of one pixel portion of the active matrix panel.

12 is an enlarged cross-sectional view taken along line XII-XII in FIG.

FIG. 13 is a cross-sectional view of a protection element that connects a gate wiring to a short ring in a conventional active matrix panel.

FIG. 14 is a cross-sectional view of a protection element that connects a data line to a short ring in a conventional active matrix panel.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 1A ... Element area 1B ... Surplus part 2 ... Pixel electrode 3 ... Pixel part TFT 4 ... Gate wiring 5 ... Data wiring 6 ... Capacitor wiring 7 ... Short line 8 ... Relay electrodes 50a, 50b, 50c ... Protective element 51 , 52 ... Protect TFT 31 ... Gate electrode a ... Oxide film 35 ... Source electrode 36 ... Drain electrode

Claims (2)

[Claims] 1. A plurality of pixel electrodes, a plurality of thin film transistors respectively connected to the pixel electrodes, and a plurality of gate wirings for supplying a gate signal to the plurality of thin film transistors on a substrate on which a liquid crystal display element is formed. A plurality of data wirings for supplying a data signal to the plurality of thin film transistors, adjacent wirings of the gate wirings and the data wirings, a gate wiring group including the plurality of gate wirings, and the plurality of data wirings. The data wiring group and the gate wiring and the data wiring at the end of each group are connected via a protective element in which two protective thin film transistors in which a gate electrode and a source electrode are electrically connected are connected in series. Active matrix panel characterized by. 2. A plurality of pixel electrodes are provided in the element region of the substrate having a surplus portion removed after assembling the liquid crystal display element around the element region corresponding to the size of the liquid crystal display element.
A plurality of thin film transistors respectively connected to these pixel electrodes, a plurality of gate wirings for supplying a gate signal to the plurality of thin film transistors, and a plurality of data wirings for supplying a data signal to the plurality of thin film transistors are provided, The gate wiring and the data wiring, which are adjacent to each other of the gate wiring and the data wiring, and the gate wiring and the data wiring at each group end of the gate wiring group including the plurality of gate wirings and the data wiring group including the plurality of data wirings, Each of the gate electrodes and the source electrodes are connected via a protective element composed of two protective thin film transistors electrically connected, and the protective element connects the drain electrodes of the two protective thin film transistors, Connect the source electrode of one protective thin film transistor to one wiring. And the source electrode of the other protective thin film transistor is connected to the other wiring, and all the data wirings and short lines for shorting the data wirings are formed on the surplus portion of the substrate. A relay electrode for connecting the data line to the short line is formed integrally with the short line on the element region of the substrate, and the gate line is formed on the substrate at the end portion thereof. The data line is connected to the short line, the data line is formed on an insulating film provided on the substrate and is connected to the relay electrode, and the gate electrode of the thin film transistor connected to the pixel electrode is the gate line. The gate electrodes of the two protective thin film transistors that are integrally formed in the
An active matrix panel, characterized in that it is formed integrally with one of the gate electrode and the relay electrode, and the electrode surface is oxidized by anodizing treatment using the short line as a power supply path.