JPH0817864A - Semiconductor package - Google Patents

Abstract

PURPOSE:To obtain a semiconductor package which is even thin but small in an area rate to a semiconductor chip by a method wherein a semiconductor package is composed of a semiconductor chip provided with a bump electrode and an insulating film fitted with a foil lead art its one side and an inter lead bonding hole. CONSTITUTION:A semiconductor package is composed of a semiconductor chip 1 provided with a bump electrode 2 and an insulating film 3 fitted with a foil lead 5 which comprises an inner lead 6 and an outer lead 7 on its one side and an inner lead bonding hole 4. The semiconductor chip 1 is placed on the other side of the insulating film 3, and the bump electrode 2 is bonded to the corresponding inner lead 6 through the intermediary of the hole 4. A part of the insulating film 3 including the outer lead 7 is so formed as to rise along the side edge of the semiconductor chip 1 making nearly right angles with the surface of the semiconductor chip 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device, and more particularly to a structure of a miniaturized package of semiconductor elements.

[0002]

2. Description of the Related Art A container and a semiconductor package that house a semiconductor chip, protect it from the external environment, and have a function of facilitating connection with an external circuit as a semiconductor element, are highly integrated ICs, There is a strong demand for high-density packaging to meet this demand, and miniaturization is progressing. The types of packages are roughly classified into a board insertion type and a surface mounting type in terms of shape, but at present, the latter surface mounting type, which has a great advantage of thinning, is becoming the mainstream.

Conventionally, SOP (Small O
utline Package), SSOP (Shri
nkSmall Outlook Package),
TCP (Tape Carrier Package)
Etc. Among the above, SOP and SSOP are resin mold type packages and have the following configurations.

3A and 3B are explanatory views showing the structure of the SOP package of the above-described type. FIG. 3A is a perspective view showing the outer shape of the package, and FIG. 3B is a sectional view of the side surface thereof. is there. In these figures, 1 is a semiconductor chip, 6 is an inner lead, 7 is an outer lead, 8 is a tab, and 9 is a metal wire 12 is a resin. Hereinafter, the same reference numerals in the drawings indicate the same or corresponding ones. In this type of package, a lead frame is generally used as a component that constitutes a lead portion and a semiconductor chip mounting tab, and is manufactured as follows.

First, the semiconductor chip 1 is fixed to the tab 8 of the lead frame, each electrode of the chip is connected to each inner lead 6 by the metal wire 9, and then molded with the resin 12, and the tie bar of the lead frame, The unnecessary portion of the lead is cut and removed, and the outer lead 7 is formed into a predetermined shape to complete the manufacture of the package.

The relationship between the semiconductor chip size and the semiconductor package size in a package of this type will be exemplified. FIG. 5 is a diagram for explaining these sizes. In FIG. 5, X1 and Y1 represent a semiconductor chip size, and X2 and Y2 represent a semiconductor package size.

To give an example of a particularly miniaturized package, the SOP type has X1 = 2.7 (unit: mm, hereinafter omitted), Y1 = 2.7, X2 = 6.8, Y2.
= 5.0, so the area ratio of the semiconductor package to the semiconductor chip (X2 · Y2) / (X1 · Y1) is about 4.
7, SSOP type, X1 = 2.2, Y1 = 2.1, X
2 = 6.4, Y2 = 3.5, and the same as above, with an area ratio of about 4.8.

The TCP type package is a so-called T-type package.
AB (Tape automated Bondin
g) A package made using the
Since it can be thinned, it is increasingly used as a package for highly integrated LSI. 4A and 4B are structural explanatory views of the TCP type package, FIG. 4A is a plan view thereof, and FIG. 4B is a sectional view in which a central portion of FIG. In the figure, 1 is a semiconductor chip, 2 is a bump electrode, and 5
Is a lead portion, 6 is an inner lead, 7 is an outer lead, 10 is a film carrier tape, and 11 is a test tape.
The pad, 12 is a resin.

To make a package of this type, first,
A bump electrode 2 made of a metal protrusion is formed on each electrode of the semiconductor chip 1, while a wiring pattern of the lead portion 5 including the above 6, 7 and 11 is formed on a long heat-resistant insulating film. A film carrier tape 10 (made by etching from a tape obtained by adhering a copper foil to an insulating film in which a semiconductor chip accommodating portion and outer lead corresponding portion are preliminarily perforated) is prepared, and the above semiconductor chip is provided thereon And each bump electrode 2 is connected to each inner lead.

Next, the semiconductor chip portion is sealed with resin 12, a test is performed using the test pad 11, after which the unnecessary portion is cut off and the outer lead portion is molded as required to complete the fabrication. To do. Also in this case, the area ratio of the semiconductor package to the semiconductor chip is about the same as that of the SOP type and SSOP type.

In order to reduce the area ratio, a PLCC (Plastic Leaded Chip) having a structure in which outer leads are folded into the back side of the mold package is a kind of resin mold type package.
There is a package called Carrier.

As a mounting method for maximally increasing the mounting density, a method called a flip chip method in which a semiconductor chip provided with bump electrodes is turned upside down and placed on a substrate, and the bump electrodes are directly bonded to a wiring pattern on the substrate. There is.

[0013]

In the above-mentioned conventional packages, in the SOP type, SSOP type and TCP type packages, the area ratio of the semiconductor package to the semiconductor chip is several times to several tens of times. The limit is about double.

Further, the area ratio P can be made smaller than the above.
In the case of the LCC type, it is not possible to make it as thin as the above, and when mounting, the outer leads folded into the back side of the package are bonded to the board side, so it is difficult to confirm soldering, etc. There is.

Further, the flip-chip method can maximize the mounting density, but requires a special bonder (flip-chip bonder) for assembly, and the substrate and the semiconductor are relieved in order to reduce the stress between the substrate and the semiconductor chip. Since it is necessary to pour the resin into the gap between the chip and the chip, the process becomes complicated.

It is an object of the present invention to provide a semiconductor package having a new structure that solves the above problems.

[0017]

In order to solve the above problems, the present invention has a semiconductor package having the following structure.

That is, it is composed of a semiconductor chip provided with bump electrodes, and an insulator film having a foil-shaped lead portion including an inner lead and an outer lead on one surface thereof and a hole for inner lead bonding. The semiconductor chip is mounted on the opposite surface of the one surface of the insulator film, and each bump electrode and each inner lead corresponding to the bump electrode are bonded to each other through the hole. A portion including the outer lead of the film was formed in a shape which is along the side surface of the semiconductor chip and stands substantially perpendicular to the semiconductor chip surface.

As one of the embodiments, in the semiconductor package, the height of the vertically folded portion of the insulating film is made higher than the height of the semiconductor chip, and the height of the portion and the semiconductor chip are made higher. A resin was filled in the concave portion formed in.

[0020]

1 is an explanatory view of an embodiment of a semiconductor package of the present invention, (a) is a perspective view and (b) is a sectional view. Further, FIG. 2 shows an explanatory view showing a state of an intermediate step of manufacturing the package. In the figure, 1 is a semiconductor chip, 2 is a bump electrode, 3 is an insulator film, and 4 is a hole for inner lead bonding. A lead portion 5 made of copper foil includes an inner lead 6, an outer lead 7 and a test pad 11. Reference numeral 12 represents a resin.

The semiconductor package of the present invention is manufactured as follows. First, for each electrode of each semiconductor chip 1, in the state of the wafer before finishing the wafer processing into chips,
Bumps such as gold or high-temperature solder are formed to form the bump electrodes 2 (the height of the bumps is made high enough to allow bonding through holes in an insulating film described later), and then the individual chips are diced. .

As the insulator film 3, for example, a film of polyimide resin having a thickness of 75 μm, which is used in the TAB method, is used. First, an opening 4 for inner lead bonding having a diameter slightly larger than that of the electrode is formed in each portion of the same film which should face the bump electrode 2 during packaging.
A 5 μm copper foil is attached with an adhesive (for example, a thickness of about 15 μm).

Next, unnecessary portions are removed from the copper foil by etching to form lead portions 5. Figure 2 (a)
Shows this state (the one-dot chain line shows the portion corresponding to the semiconductor chip 1). The lead portion 5 includes portions to be inner leads, outer leads and a test pad 11, which are plated with metal such as tin or gold.

Next, the semiconductor chip with the bump electrode is placed on the surface of the insulating film opposite to the lead portion 5 for alignment, and each inner lead corresponding to each bump electrode 2 through the hole 4. 6 and 6 are bonded by thermocompression bonding.

Next, after performing a test using the test pad 11, the pad is cut and removed together with the insulating film, and the outer shape of the insulating film is cut into a shape required for the next step (folding).・ Mold. FIG. 2B shows this state.

Next, as shown in FIG. 1, the peripheral portion of the insulating film provided with the outer leads is heat-molded into a shape in which it is vertically folded along the side surface of the semiconductor chip 1. The height of the insulator film on the side surface formed by this folding is set to be about 100 to 200 μm higher than the upper surface of the semiconductor chip by the dimensioning of the cutting.

Finally, as shown in FIG. 1 (b), epoxy resin 12 is potted in the above-mentioned raised portion and the recess formed by the semiconductor chip to complete the assembly of the semiconductor package according to the present invention.

In the semiconductor package of the present invention, the insulating film plays a role of insulating / protecting the semiconductor chip.
The resin 12 serves to reinforce the molding of the folded portion as well as to further protect the semiconductor chip.

As described above, the semiconductor package of the present invention can be manufactured in an extremely small size because the main container is the extremely thin insulator film and the outer lead portions are erected perpendicularly to the semiconductor chip surface. . Therefore, the SSOP semiconductor chip (chip size: X1 = 2.2, Y1 = 2.1) given as the above-mentioned conventional example is an insulator film, copper foil, etc. having the thickness illustrated in the above-mentioned embodiment of the present invention. When the package of this system is formed by using the above material, the package size becomes approximately X2 = 2.45 and Y2 = 2.35, and therefore the area ratio of the semiconductor package to the semiconductor chip becomes approximately 2.2. Area ratio about 4.
It is smaller than half of 8).

To mount the semiconductor package of the present invention on a circuit board, the package is placed on a predetermined portion of a wiring pattern coated with solder, and the solder is reflowed to be mounted. In this case, the solder wets the lower part of the outer lead, which is perpendicular to the board surface, and accumulates in the corners formed by the wiring of the board so that the soldering adhesion state can be easily checked by visual inspection. It

In the description of the above embodiment, the inner leads,
Although the case where a circular hole is provided for each electrode as the bonding hole 4 is shown, the shape is not limited to the circular shape, and as long as the insulation by the insulating film is not hindered,
It is also possible to use the one having slit-shaped holes corresponding to a plurality of electrodes.

As an example, the case where the folded portion of the insulating film is raised and the resin is potted in the recessed portion formed with the semiconductor chip has been described. By covering the diffusion surface and the side surface, and by constructing the outer lead in the shape of standing up along the side surface, the main effect thereof is produced, and it is not limited to the configuration of the above-mentioned embodiment, Further, it is not limited to the manufacturing method.

[0033]

As described above, in the semiconductor package of the present invention, the extremely thin insulator film is used as the main container, and the outer lead portions are erected along the side surface of the semiconductor chip and substantially perpendicular to the semiconductor surface. From that,
It is possible to realize a semiconductor package which is thin and has a much smaller area ratio of package size to a semiconductor chip than a conventional semiconductor package.

Also, since the outer leads are provided vertically along the side surface of the chip, when mounted on a circuit board,
The corners made with the wiring pattern can be used for bonding. Therefore, unlike the conventional PLCC type or flip chip type, there is no problem that it is difficult to confirm the bonding state of soldering.

Further, there is no need for a special bonder as in the case of the flip chip system, and there is no need for pouring resin into the gap between the substrate and the semiconductor chip.

As described above, the semiconductor package of the present invention facilitates ultra-miniaturization, but at the same time, its structure is simple, so that the production can be fully automated.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a semiconductor package of the present invention.

FIG. 2 is an explanatory view showing a state in an intermediate step of the semiconductor package of the present invention.

FIG. 3 is an explanatory diagram of an example of a conventional semiconductor package.

FIG. 4 is an explanatory diagram of another example of a conventional semiconductor package.

FIG. 5 is a diagram for explaining an area ratio between a semiconductor package and a semiconductor chip.

[Explanation of symbols]

1: semiconductor chip, 2: bump electrode, 3: insulator film, 4: hole, 5: lead part, 6: inner lead, 7:
Outer leads, 8: tab, 9: metal wire, 10: film carrier tape, 11: test pad, 1
2: Resin.

Claims (2)

[Claims] 1. A semiconductor chip provided with bump electrodes, and an insulator film having a foil-shaped lead portion including an inner lead and an outer lead on one surface thereof and having a hole for inner lead bonding. The semiconductor chip is mounted on the opposite surface of the one surface of the insulator film, and each bump electrode and each inner lead corresponding to the bump electrode are bonded to each other through the hole. A semiconductor package, wherein a portion including an outer lead of the film is formed in a shape that stands along a side surface of the semiconductor chip and is substantially perpendicular to the semiconductor chip surface. 2. The semiconductor package according to claim 1, wherein
The height of a portion of the insulator film which stands vertically is made higher than the height of the semiconductor chip, and a recess formed by the raised portion and the semiconductor chip is filled with resin. package.