JPH0817319B2 - 3-state circuit and output circuit using the same - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and in particular, it operates with one signal without using a complementary signal as an enable signal.
The present invention relates to a (tri) state circuit and an output circuit using the same.

[Conventional technology]

A bipolar CMOS composite technology is being developed with the aim of realizing an LSI that combines the bipolar transistor and COMS in a basic circuit and combines the low power consumption and high integration of CMOS with the high speed of a bipolar transistor. This bipolar CMOS composite technology has been applied to memories, gate arrays, etc., and products have already been announced by each company. The output circuit used for the gart array by the bipolar CMOS composite technology is disclosed in, for example, Nikkei Electronics (85.8.12.P196). This circuit diagram is shown in FIG. The basic operation is as follows. The output signal of the internal circuit is input to the 201 CMOS inverter. This inverter is an amplifier circuit for fully swinging the signal of the internal circuit to the power supply voltage. The output of the inverter 201 is 202PM
The OS transistor and 203,204 are fed to an NMOS transistor, each MOS transistor driving a 205,206 bipolar transistor. For example, when "H" is input to the input terminal 207, the input is inverted by the inverter 201 and "L"
Becomes Therefore, the PMOS of 202 is turned on, the NMOSs of 203 and 204 are turned off, the NPN transistor of 205 is turned on, the NPN transistor of 206 is turned off, and eventually the output of 208 becomes "H". Conversely, when “L” is input to the input 207, the input is inverted by the inverter 201 and becomes “H”. Therefore 202 PMOS
Is turned off, the NMOSs 203 and 204 are turned on, the NPN transistor of 205 is turned off, the NPN transistor of 206 is turned on, and eventually the output of 208 becomes "L". As described above, in the conventional output circuit, the internal signal is received by the CMOS and the complementary operation is performed by driving the bipolar by the CMOS to achieve the low power consumption.

[Problems to be solved by the invention]

In the above-mentioned conventional technique, since the input portion has the CMOS configuration, when the tri-state circuit is configured, two contradictory control signals are required, which causes a problem of increasing the number of elements. This will be described in detail with reference to FIG. FIG. 3 shows a tri-state circuit as the output circuit described with reference to FIG. The elements added in addition to those in FIG. 2 are a PMOS 303, and NMOS 304, 305, 306. These four MOSs are the elements necessary to form a tristate circuit. Further, 301 and 302 are enable terminals. 301 and 302 input contradictory control signals. The operation will be briefly described below. When “L” is input to 301 and “H” is input to 302, 303 turns on, 305 and 306 turn off, and 304 turns on. In this case, the circuit operates normally according to the input signal of 207 and outputs the output signal. For example, when “L” is input to 207, the input is inverted by the inverter 201, 202 is turned off, and 203 and 204 are turned on. Therefore, 205 is off, 206 is on, and the output is "L". On the other hand, input "207" is "H"
When is input, the input is inverted by 201 and becomes “L”.
Is on, 203,204 is on, so 205 is on, 206
Turns off and the output goes high. In this way, when "L" is input to 301 and "H" is input to 302, normal operation is performed. However, if "L" is input to 301, "L" is input to 302, 303 is off, 305 and 306 are on, 304 is on, so both 205 and 206 are off at the same time, and the output is in a high impedance state. In this way, by inputting contradictory control signals to 301 and 302, this conventional circuit outputs “H” and “L” output signals to 208 according to the input signal of 207, or outputs high signals. Impedance state. However, in this conventional circuit, 303, 304,
Four new MOSs, 305 and 306, have been newly added.
In order to control the MOS, it is necessary to input two contradictory control signals.

An object of the present invention is to provide a circuit which does not need to add a new element even when configuring a tri-state circuit, and which requires only one enable signal for controlling the tri-state circuit.

[Means for solving problems]

The means for achieving the above-mentioned object will be described below roughly divided into two. The first is to use it in a differential circuit where the outputs simultaneously go to "H". The second is a single channel MO for the output of the first differential circuit.
It is input to the gate of S. First, the first differential circuit will be described with reference to FIG. 101,102 is N
It is a PN transistor, and its emitters are connected to each other and have a common potential. The base of 102 is fixed to a certain reference potential V _BB, and the base 103 of 101 serves as an input terminal. 101 and 102
Emitter 104 is the enable terminal and collector of 101
The collector 105 of 106 and 102 is the output terminal. The circuit operation will be described below. First, consider a case where the enable terminal 104 has a high impedance. At this time, when a voltage “H” higher than V _BB is input to input 103, 101 turns on and 102 turns off.
105 “H” and 106 become “L”. Conversely, when a voltage lower than V _BB is input to input 103, 101 turns off, 102 turns on, and 105
Is "L" and 106 is "H". This series of operations is the same as a normal differential circuit.

On the other hand, consider the case where "H" is input to the enable terminal 104. At this time, the common emitter of 101 and 102 is clamped to “H” input to 104. Therefore, when either “H” or “L” is input to the input terminal 103, both 101 and 102 are turned off at the same time. Therefore, both outputs 105 and 106 become "H" at the same time. The above operation is summarized in Table 1.

Next, the latter half of the means will be described with reference to FIG.
(B) shows that the outputs 105 and 106 of the circuit (a) are connected to an inverter composed of a single channel MOS. Since the differential circuit has been described in detail above, the operation of the subsequent stage will be described below. 107 and 108 are PMOS, and 109 and 110 are NPN transistors. When 105 is “L” and 106 is “H”,
107 is on, 108 is off, so 109 is on, 110 is off, and the output 111 is "H". Conversely, when 105 is “H” and 106 is “L”, 107 is off, 108 is on, 109 is off, 110 is on, and the output 111 is “L”. If both 105 and 106 are "H", 107,1
08 is turned off and both 109 and 110 are also turned off. Thank you
The output 111 is in a high impedance state. This operation is summarized as follows.

Therefore, it can be seen that FIG. 1 (b) constitutes a tri-state inverter. As is clear from the above description, the circuit of FIG. 1 (b) can be made into a tri-state circuit only by providing the terminal 104, so that the number of elements is not increased.

[Action]

The following description will be given with reference to FIG. First, FIG. 1 (a)
Is a differential circuit whose outputs simultaneously become "H" as shown in Table 1 above. That is, when the enable terminal 104 is high impedance, if 103 is “H”, 105 is “H”,
106 becomes “L”, and if 103 is “L”, 105 becomes “L”, 106
Becomes "H". On the other hand, when the enable terminal 104 is "H", both 101 and 102 are turned off and 105 and 106 are simultaneously "H" regardless of whether "103" is "H" or "L". Connect the inverter composed of single channel No.5 to the differential circuit that performs the above operation. This circuit is shown in FIG. 1 (b). That is, by inputting the complementary signals output to the outputs 105 and 106 of the differential circuit to the gate of the single channel MOS, the single channel MOS performs the complementary operation. For example, 105 is “H”, 10
When 6 is “L”, 107 is off. Since 108 is on, 109 is off, and 110 is on, the output 111 is "L". Conversely, 10
When 5 is "L" and 106 is "H", 107 is on, 108 is off, 109 is on and 110 is off, so the output 111 is "H". On the other hand, if both 105 and 106 are “H” at the same time,
Both 107 and 108 are off, 109 and 110 are also off at the same time, and output 11
1 becomes high impedance state. As described above, the tri-state inverter can be constructed without increasing the number of elements by using the differential circuit whose outputs become "H" at the same time and the inverter composed of the single channel MOS.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. The output circuit according to the present embodiment outputs the signal of the internal circuit operating between the second power source −5.2V and GND as a TTL level signal between the first power source + 5V and GND.
Based on the above, the circuit configuration and circuit operation will be described below. The circuit is roughly divided into an input unit 407, a level shift unit 408, and an output unit 409. Input power supply terminal 405
Is connected to GND, and the power supply terminal 406 is connected to the second power supply (−5.2
V). A signal from the internal circuit is input to the input terminal 401. Low level V _IL of internal circuit signal is -5.2
V and high level V _IH are signals with a swing of OV or close to OV. The input unit 407 converts the input signal into a signal with a swing of about 0.8V. About 0.8V after conversion to the output 103 of the input section
A swing signal appears. In this way, the reason why the internal circuit signal having a swing of about 5 V is converted to a swing of about 0.8 V at the output 103 of the input section is to minimize the reverse bias applied between the base and the emitter of the NPN transistor 101. Because of that. Next, the power supply terminal 404 of the level shift unit is connected to the first power supply (+ 5V), and the power supply terminal 406 is connected to the second power supply (−5.2V). In the level shift unit 408, the signal of the output 103 of the input unit is level-shifted and widened, and a complementary signal is produced. A signal of 103 having a potential lower than GND and a swing of about 0.8V is converted to a swing of positive potential having a swing of about 5V at 105 and 106. The signals 105 and 106 are inverted from each other. Finally, the power supply terminal 404 of the output unit 409 is connected to the first power supply (+ 5V), and the power supply terminal 405 is connected to GND. The output unit 409 is a buffer circuit and outputs the complementary signals of 105 and 106 as a single end. TTL for output terminal 111
The level signal is output. The functions of the PMOSs 403 and 407 will be described later. The circuit configuration is as described above, and the circuit operation will be described below. In the following description, the “H” level “L” level of the input signal, the “H” level “L” of the output 103 of the input unit 407 and the “H” level “L” level of the outputs 105 and 106 of the level shift units are described. The "H" level and "L" level of the output signal are different, but for simplicity, all "H" levels are described as "H" and each "L" level is described as "L".
When “H” is input to the input terminal 401, 103 becomes “L”. Therefore, 101 is turned off, 102 is turned on, 106 is “H”, and 105 is “L”. 107 is on, so 109 is on, 407,108
Is turned off, so 110 is turned off, and therefore "H" is output to the output terminal 111. Further, when “L” is input to the input terminal 401, 103 becomes “H”, 101 is on and 102 is off. Therefore, 105 becomes "H" and 106 becomes "L". Since 107 is turned off, 109 is turned off, and 407 and 108 are turned on, so 110 is turned on. Therefore, “L” is output to the output terminal 111. From this operation, this embodiment constitutes a through circuit. It is easily possible to change the present embodiment to an inverter circuit. That is, connect 105 to the collector of 101 and 106 to 102
Connect to the collector. In such a configuration, a signal that is the inverse of the circuit operation described above is output, so that an inverter circuit is obtained. Further, when it is desired to configure multi-input logic, the logic can be configured by the CMOS unit of the input unit 407. Further, the feature of the circuit of this embodiment is that a PMOS 403 is added to form a tri-state circuit. When “H” is input to the enable terminal 402, the PMOS 403 turns off and the circuit operates normally. On the other hand, when “L” is input to 402, the PMOS 403 is turned on, the emitters of 101 and 102 are clamped to the high level, and both 101 and 102 are turned off.
Therefore, 105 and 106 are all "H", and 107,108 and 407
All PMOS are turned off. That is, both 109 and 110 are turned off, and the output 111 becomes high impedance. Finally, the 407 PMOS is the 110 base supply MOS. When 106 is “L”, 407 keeps supplying base current to 110,
110 remains on. Therefore, the output 111 connected to the TTL circuit can sufficiently handle the sink current I _OL from the TTL, and the output “L” is maintained.

Further, although the single channel MOS is composed of the PMOS in this embodiment, it may be composed of the NMOS.

〔The invention's effect〕

According to the present invention, it is possible to configure a differential circuit in which outputs simultaneously become “H”. A tristate circuit can be constructed by using the differential circuit of the present invention and a single channel MOS. The tri-state circuit can be constructed with almost no additional elements. First of all, a differential circuit whose outputs simultaneously become "H" is realized by clamping the common emitter of the transistors forming a differential pair to "H". This corresponds to inputting "H" to the terminal 104 shown in FIG. On the other hand, in order for the differential circuit to operate normally, 104 may be in a high impedance state. The gate of a single channel MOS is connected to the output of this differential circuit. For example, it is as shown in FIG. Since complementary signals are output from the outputs 105 and 106 of the differential circuit, the single channel MOSs 107 and 108 perform complementary operations. An inverter circuit can be configured by this operation. Also output 10
If 5,106 simultaneously become “H”, single channel MOS
Both 107 and 108 are off. Yotsute NPN transistor 10
Both 9,110 are also turned off, and eventually the output 111 becomes a high impedance state. As described above, the common emitter of the differential circuit
By adding a control signal to 104, a trastate circuit can be constructed without adding any element.

[Brief description of drawings]

1 and 4 are circuit diagrams of an embodiment of the present invention, FIG. 2 and FIG.
The figure is a circuit diagram of a conventional embodiment. 101,102 ... NPN transistor, 103 ... Input terminal, 104 ...
… Enable terminal, 105,106 …… Output terminal, 107,108 ……
PMOS, 109,110 …… NPN transistor, 111 …… Output terminal, 202 …… PMOS, 203,204 …… NMOS, 205,206 …… NPN transistor, 301,302 …… Enable terminal, 303 …… PMO
S, 304, 305, 306 ... NMOS, 401 ... Input terminal, 402 ... Enable terminal, 403 ... PMOS, 407 ... Input section, 408 ...
Level shift section, 409 ... Output section.

Claims (9)

[Claims] 1. A first bipolar transistor in which an input signal is input to a base and a collector is connected to a first power supply potential via an impedance element, and a reference potential is applied to the base, and a collector is connected via an impedance element. A second bipolar transistor whose emitter is connected to the first bipolar transistor and whose collector is connected to the emitters of the first and second bipolar transistors, and whose collector is connected to the first power supply potential. An enable signal is inputted and at least a third bipolar transistor whose emitter is connected to the second power supply potential is provided, and first and second signals are output from the collectors of the first and second bipolar transistors, respectively. And a first differential circuit section that performs on / off operation by receiving the first signal at the gate
Field effect transistor, a second field effect transistor of the same conductivity type as the first field effect transistor which is turned on and off by receiving the second signal at the gate, and the first field effect transistor.
And a logic circuit section having at least a bipolar transistor which is turned on / off according to on / off of the second field effect transistor, and a high level signal based on the high level or low level of the input signal and the enable signal. , A low-level signal and a high-impedance state signal are output. 2. The bipolar transistor of the logic circuit section according to claim 1, wherein the collector is connected to a third power supply potential, and the emitter is connected to the output section. Is connected to the output section, and a fifth bipolar transistor whose emitter is connected to a fourth power supply potential. In the first field effect transistor, one of a source and a drain thereof is a third The second field effect transistor is connected to the power supply potential, the other is connected to the base of the first bipolar transistor, and one of the source and the drain of the second field effect transistor is connected to the output section, and the other is connected to the second section. A three-state circuit characterized by being connected to the base of the bipolar transistor of. 3. The method according to claim 2, wherein between the base of the fourth bipolar transistor of the logic circuit section and the output section or between the base of the fifth bipolar transistor and the fourth power supply potential. 3 is characterized by being connected with an impedance element between
State circuit. 4. The first and second electric fields according to claim 2, wherein the fourth bipolar transistor and the fifth bipolar transistor of the logic circuit section are NPN type. The effect transistor is a P-type 3-state circuit. 5. The method according to claim 2, 3, or 4, wherein the first power source potential and the third power source potential are substantially the same potential, and the second power source potential and the third power source potential are the same. A three-state circuit characterized in that the power supply potentials of 4 are almost the same. 6. A first field effect transistor, which operates between a first power supply potential and a second power supply potential and receives an input signal at each gate, and a first conductivity type transistor different from the first field effect transistor. At least a complementary field effect transistor pair including two field effect transistors, and a third field effect transistor that receives an enable signal at its gate and receives a potential from the first power supply potential at either its source or drain. And an input section for receiving a signal from the complementary field effect transistor pair and converting it into a signal of a predetermined amplitude, and a signal of a predetermined amplitude converted by the input section is input to the base, and the collector is an impedance element. A first bipolar transistor connected to a third power supply potential via
A reference potential is applied to the base, a collector is connected to the third power supply potential through an impedance element, an emitter is connected to the first bipolar transistor, and a collector is the first and second bipolar transistors. The third power source potential is input to the collector of the second bipolar transistor through the third field effect transistor that is turned on / off according to the enable signal and is connected to the emitter of the second bipolar transistor, and the emitter becomes the second power source potential. At least a third bipolar transistor connected, and operating with a power supply potential difference between the third and second,
A level shifter for outputting first and second signals from the collectors of the first and second bipolar transistors, and a fourth on / off operation for receiving the first signal at the gate
And a fifth field effect transistor of the same conductivity type as the fourth field effect transistor which is turned on and off by receiving the second signal at the gate, and the fourth and fifth field effect transistors. A bipolar transistor which is turned on / off in response to turning on / off, and an output section which operates between the third power supply potential and the fourth power supply potential, and the input signal and the enable signal. An output circuit, which outputs a high-level signal, a low-level signal, and a high-impedance state signal based on the above. 7. The bipolar transistor of the output section according to claim 6, wherein a collector is connected to a third power supply potential, a fourth bipolar transistor which outputs a signal from an emitter, and a collector is the third bipolar transistor. Four
A fifth bipolar transistor connected to the emitter of the bipolar transistor, the emitter of which is connected to the fourth power supply potential, and the first field-effect transistor is configured such that one of the source and the drain thereof is the third. Of the second bipolar field effect transistor, the other of which is connected to the base of the first bipolar transistor and the other of which is connected to the emitter of the fourth bipolar transistor. The output circuit is characterized in that the other is connected to the base of the second bipolar transistor. 8. A device according to claim 7, wherein the gate receives the first signal from the level shift unit, and the source / drain current path is connected to the base of the fifth bipolar transistor of the output unit and the base of the fifth bipolar transistor. An output circuit having a sixth field effect transistor formed between the third power supply potential and the third power supply potential. 9. The claim 7 or claim 8, wherein the fourth bipolar transistor and the fifth bipolar transistor of the output section are NPN type, and the first and second electric field effects are provided. An output circuit characterized in that the transistor is a P-type.