JPH08167919A - Digital demodulator - Google Patents

Abstract

PURPOSE: To reduce the scale of the hardware by simultaneously absorbing influence of Doppler effect in a buffer of an error correction section adopting the successive decoding system. CONSTITUTION: The demodulator is provided with a 1st buffer 1 storing a reception signal 10 synchronously with a reception clock 11 and a 2nd buffer 2 storing decoded data 15 outputted from a sequential decoding processing section 3 and includes an error correction section synchronizing reading of data from the 2nd buffer 2 to an external circuit with a ground system clock 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital demodulation device, and more particularly to a digital demodulation device for satellite communication including an error correction section.

[0002]

2. Description of the Related Art A digital demodulation device for satellite communication comprises a demodulation section and an error correction section. In the digital demodulation device currently used for satellite communication, the demodulation unit is QP
In SK, Viterbi decoding is mainly used for the error correction unit. Further, in the error correction unit, sequential decoding, which has a larger coding gain than Viterbi decoding, is often used.

Sequential decoding is one of the decoding methods for convolutional codes. That is, in order to detect and correct a transmission error of data, the data is divided into several information symbols, and the information symbols are convolutionally coded by an error correction encoder into code symbols, and the transmitted code symbols are error-coded. Decoding is performed using the Fano algorithm in the correction decoder.

The error correction encoder has a state holding circuit and a function generating circuit. The state holding circuit is composed of, for example, a shift register, holds an internal state, and changes the internal state by inputting an information symbol. The function generator generates code symbols based on the internal state. The code symbol is sent to the receiving station via the satellite line.

The received signal (hard decision) received by the decoder of the receiving station corresponding to one code symbol does not always match the code symbol sent due to a transmission error. The decoder has a circuit having the same function as the corresponding error correction encoder (hereinafter referred to as “encoder duplication”), and encodes all possible information symbols each time a received signal corresponding to one code symbol is received. Each of the code symbols output by the encoder replica when input to the replica is compared with the received signal received, and the information symbol that gives the code symbol closest to the received signal is estimated to be the transmitted information symbol.

In this case, a likelihood called Fano likelihood is used as a measure of the closeness. In the Huano algorithm, basically, the information symbol string having the largest cumulative likelihood of the Fano likelihood is determined to be the sent information symbol string.

However, if many transmission errors occur, it is possible that the wrong information symbol is determined to be the sent information symbol.

Once an erroneous decision is made, the internal state of the encoder copy after that is inconsistent with the internal state of the error correction encoder, and even if an attempt is made to find an information symbol having a large fano likelihood, it will not be found. It can be detected that the judgment is made.

When it is detected that an erroneous decision is made, the internal state of the encoder copy is returned to the past state, and the information symbol having the second largest fano likelihood is sent after the information symbol selected in the past. Then, the decoding is redone.

In this case, if an attempt is made to find an information symbol having the next largest fano likelihood and it cannot be found because it has already been searched, another previous state is returned to and the same operation is performed.

In such a demodulator, decoding may be performed by repeating trial and error, and the once completed decoding result may be changed later. Therefore, the decoder needs a buffer for the input received signal and a buffer for the decoding result.

The above-described Huano algorithm was devised by American Fano (RM Fano).
EE Transactions on Information Theory, IT-
9 (1963) (US), pp. 64-74.
Further, the error correction encoder and decoder as described above are disclosed, for example, in US Pat. No. 3,66, George David Forney, Jr.
It can be realized by the circuit described in 5,396.

On the other hand, in satellite communication, the phase of the clock of the received data (hereinafter referred to as "receive clock") gradually changes as the drift of the satellite changes. This is called the satellite Doppler effect.

When the receive clock phase changes,
The output data from the digital demodulator cannot be correctly read by the terrestrial clock operating in the terrestrial system connected to the demodulator.

In order to eliminate this influence, a digital demodulator is generally equipped with a Doppler buffer. That is, the received data is written to the Doppler buffer in synchronization with the received clock, the data is accumulated in the Doppler buffer to some extent, and then the received data is read at the terrestrial clock.

FIG. 3 is a diagram for explaining how a conventional Doppler buffer memory is used, based on a ring-shaped buffer.

Referring to FIG. 3, A indicates a pointer (referred to as "write pointer") for writing the reception data to the memory buffer in synchronization with the reception clock, and indicates a circle representing the memory buffer (capacity N bits). , Write the received data in synchronization with the received clock while rotating clockwise. B indicates a pointer for reading the decoded data from the memory buffer in synchronization with the terrestrial clock (referred to as "read pointer"), and at the same time, the data is read in synchronization with the terrestrial clock while rotating clockwise. It should be noted that the pointers A and B start to operate at positions separated by N / 2 bits from each other.

FIG. 3 (a) shows a case where the frequencies of the reception clock and the terrestrial clock match. Since the write pointer A and the read pointer B have the same traveling speed on the circumference of the buffer memory, the positional relationship in the initial state is maintained.

FIG. 3B shows a case where the reception clock has a higher frequency than the terrestrial clock. Since the write pointer A has a relatively faster moving speed than the read pointer B, the read pointer B is catching up with the write pointer A (the memory buffer is overflowing with data to be read).

FIG. 3C shows a case where the frequency of the reception clock is lower than that of the ground clock. Since the write pointer A has a relatively slower moving speed than the read pointer B, the read pointer B is catching up with the write pointer A (the memory buffer has a small amount of data to be read).

The size N of the buffer memory is shown in FIG.
, The read pointer B becomes the write pointer A,
Further, in FIG. 3C, it is necessary to determine such that the write pointer A cannot catch up with the read pointer B.

[0022]

As described above, in the conventional digital demodulation device, the error correction unit and the Doppler buffer are independently configured. Therefore, there is a limit in reducing the circuit scale of the digital demodulator.

The present invention has been made in view of the above problems, and in a buffer of an error correction unit of a sequential decoding system, the influence of the Doppler effect is absorbed at the same time, and thereby the digital demodulation for reducing hardware is achieved. To provide a device.

[0024]

In order to achieve the above object, a digital demodulation device according to the present invention stores first reception means for storing a reception signal in synchronization with a reception clock and a signal subjected to sequential decoding processing. A digital demodulation device is provided which further comprises an error correction unit for performing reading from the second storage unit to an external circuit in synchronization with a terrestrial clock.

[0025]

According to the present invention, the buffer in the error correction unit of the digital demodulator also has the Doppler buffer function, and therefore the amount of hardware can be reduced as compared with the conventional example.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the error correction unit of the present invention.

The data 10 (received signal) sent from the demodulator is the clock 11 sent from the demodulator.
And is stored in the buffer 1 in synchronization with.

The successive decoding processing unit 3 instructs the buffer 1 via the control signal 13 to input the received signal. In response to this instruction, the buffer 1 receives the designated received signal 1
4 is sent to the sequential decoding processing unit 3.

The successive decoding processing unit 3 performs successive decoding by the Fano algorithm in synchronization with the clock 12 supplied from the oscillator 4 which outputs a frequency several times to several tens of times of the reception clock 11.

The decoded data 15 is stored in an appropriate position in the buffer 2 under the control of the control signal 16.

The buffer 2 outputs the stored decoded data 18 in synchronization with the terrestrial clock 17 sent from the connected terrestrial device.

The above is the case where the received data has relatively few errors and the decoding proceeds smoothly. However, when the received data contains many errors, the decoding process is redone.

That is, if the received data contains a relatively large number of errors, the sequential decoding operation will not proceed. Then, the sequential decoding processing unit 3 determines that the error is due to an error in past decoding, and performs the decoding again.

Under the control of the control signal 16, the successive decoding processing unit 3 instructs the successive decoding processing unit 3 to return the decoded data 15 stored in the buffer 2 as if the decoding was once completed.

Further, the successive decoding processing unit 3 instructs the buffer 1 via the control signal 13 to input the received data read when decoding the decoded data to the successive decoding processing unit 3 again. In this way, the past decoding is redone until the decoding work can proceed.

Assuming that the required buffer capacity in the case of normal sequential decoding is M bits and the required buffer capacity of the Doppler buffer is N bits, the buffer 1 in this embodiment,
The capacity of 2 is N + M bits.

FIG. 2 is a diagram for explaining how to use the memory of the error correction unit in this embodiment. Referring to FIG. 2, A
Indicates a pointer for writing the reception data in synchronization with the reception clock while rotating in the clockwise direction on the circumference representing the memory buffer (capacity (N + M) bits). Similarly, B indicates a pointer for reading the decoded data in synchronization with the terrestrial clock while rotating clockwise. Further, C indicates a pointer for decoding the data while advancing the data section written on the memory. It should be noted that the positions A and B start the operation at positions separated from each other by N / 2 bits.

FIG. 2 (a) shows the case where the frequencies of the reception clock and the terrestrial clock are the same. Since the write pointer A and the read pointer B have the same traveling speed on the circumference of the buffer memory, the positional relationship in the initial state is maintained.

FIG. 2B shows a case where the reception clock has a higher frequency than the terrestrial clock. Since the write pointer A has a relatively faster moving speed than the read pointer B, the read pointer B is catching up with the write pointer A (the memory buffer is overflowing with the decoded data to be read).

FIG. 2C shows a case where the frequency of the reception clock is lower than that of the ground clock. Since the write pointer A has a relatively slower moving speed than the read pointer B, the read pointer B is catching up with the write pointer A (the data to be read is running out in the memory buffer). However, since the capacity of the Doppler buffer is N bits, the read pointer B cannot catch up with the write pointer A at worst. That is, the section between the write pointer A and the read pointer B always has M bits or more. In this embodiment, the capacities of the buffers 1 and 2 are determined so that the M-bit buffer capacity can be secured for the decoding process even in such a worst case.

As described above, according to this embodiment, the buffer in the error correction section of the digital demodulator also has the Doppler buffer function, and the amount of hardware can be reduced as compared with the conventional example.

[0042]

As described above, according to the present invention, the error correction unit of the digital demodulator also has the Doppler buffer function, and has the effect of reducing the amount of hardware as compared with the conventional example.

According to the present invention, when the frequency of the received clock is lower than that of the terrestrial clock, the decoding process buffer capacity for the decoding process is secured even in the worst state.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an error correction unit of a digital demodulation device according to the present invention.

FIG. 2 is a diagram illustrating how a memory of an error correction unit according to the present invention is used.

FIG. 3 is a diagram illustrating how a memory of a conventional Doppler buffer is used.

[Explanation of symbols]

1, 2 Buffer circuit 3 Sequential decoding processing unit 4 Clock generator A Pointer for writing received data to the memory buffer in synchronization with the received clock. B Pointer that reads the decoded data from the memory buffer in synchronization with the terrestrial clock. C A pointer for decoding the stored received data.

Claims (2)

[Claims] 1. A first storage means for storing a reception signal in synchronization with a reception clock, and a second storage means for storing a signal subjected to sequential decoding processing. A digital demodulation device including an error correction unit for performing reading to an external circuit in synchronization with a terrestrial clock. 2. An error correction section, comprising: first storage means for storing a reception signal in synchronization with a reception clock; and a decoding processing section for receiving the reception signal from the first storage means and performing a sequential decoding process. A second storage unit for storing the decoded data output from the decoding processing unit and reading the decoded data in synchronization with a ground clock, the total capacity of the first and second storage units. Is a value obtained by adding at least the capacity required for the decoding process and the capacity required for the Doppler buffer to the digital demodulator.