JPH08163108A - Resynchronization device for error correction code decoder - Google Patents

Abstract

PURPOSE: To quickly correct the synchronous error of an error correction code decoder of Hagelborger code, etc., in a simple circuit constitution. CONSTITUTION: A syndrome calculation part 5 includes the shift registers R1 to R15 and calculates syndromes S0 to S7 for the series which are shifted from each other every bit of inputs Y1 to Y8. A comparison/decision part 6 decides the synchronous series based on the syndromes S0 to S7. Then the part 6 switches a switch SW and shifts the input by an extent equal to the number of shifted bits between the synchronous series and the original data Y1 to Y8 to recover the synchronization.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction code decoder used in the field of data communication, and more specifically,
The present invention relates to an apparatus for reestablishing synchronization of an error correction code decoder.

[0002]

2. Description of the Related Art As a forward error correction method, an error correction code capable of correcting data errors by itself is known. Various codes have been proposed for these error correction codes. For example, Hamming code, BCH code, RS (Reed-Solomon) code is used as the block code, and Iwadare code, Hagelbarge is used as the convolutional code.
R-codes and the like have been proposed.

Generally, redundant bits are added to the error correction code. For example, a 1-bit redundant bit (of course, the redundant bit is not limited to 1 bit) is added to n-1 bit data to obtain an n-bit error correction code. On the decoding side, the n-bit data is decoded and the original n-
Reproduce 1-bit data.

[0004]

As described above, data must be input to the error correction code decoder in units of n bits. However, if the synchronization is deviated and the delimiter every n bits of the data is deviated. Has a problem that it cannot be decrypted.

Whether or not decoding is correctly performed can be known by monitoring the syndrome in time series. That is, if decoding can be performed correctly, 0 will appear consecutively in the syndrome, but if decoding cannot be performed correctly, 1 will be added to it. If it cannot be decoded correctly, more 1 will occur.

[0006] In the simplest case, it is conceivable to shift the data series so that the syndrome becomes continuous to zero. However, since the syndrome changes by shifting the data sequence by one, it takes time for the syndrome to stabilize after shifting by 1 bit, and it also takes time before it can be determined whether or not the synchronization is really restored. . This is because the register used for syndrome calculation and the register used for error correction are shared, and the previous correction result affects the syndrome.

As another method, n error correction code decoders are used and a data series shifted by 1 bit is input. Then, of the syndromes of each error correction code decoder, the decoded output of the error correction code decoder with the smallest occurrence of 1 is selected and used. In this method, although the synchronization error can be corrected instantaneously, there is a problem that the number of error correction code decoders is required and the circuit scale becomes large.

The present invention has been made in view of the above,
It is an object of the present invention to provide a resynchronization device for an error correction code decoder that can quickly resynchronize with a relatively simple configuration.

[0009]

In order to solve the above-mentioned problems, a resynchronization device of an error correction code decoder according to the invention of claim 1 is a decoding means for decoding an error correction code of a reception sequence, and a reception sequence. , A storage unit having a plurality of storage sequences for storing the data by shifting them by a predetermined bit, a syndrome calculation unit for calculating the syndrome based on the data stored in the storage unit, and a bit shift of the reception sequence based on the calculation result of the syndrome calculation unit. And a bit shift means for causing the shift.

According to a second aspect of the present invention, in the resynchronization device of the error correction code decoder according to the first aspect, the decoding means decodes an n-bit error correction code and the storage means stores 2n-. The syndrome calculation means has one series of memory sequences, and the syndrome calculating means calculates n series of syndromes with respect to a reception sequence that is shifted by 1 bit from the 2n−1 memory series, and a sequence with the least error from these n series of syndromes. To decide.

Further, the invention of claim 3 is the resynchronization device of the error correction code decoder according to claim 2, wherein the bit shift means is a sequence which is determined by the syndrome calculation means to have the smallest error, and The received sequence is bit-shifted by the number of bit deviations from the received sequence.

[0012]

According to the first aspect of the present invention, a syndrome is created for each of the sequences that are deviated by a predetermined bit from the original reception sequence, and it is determined which sequence is synchronized. From the bit shift between the synchronized sequence and the original received sequence, it is immediately known how many bits the original received sequence should be shifted to achieve the synchronization. Then, the bits of the original reception sequence can be shifted by that number of bits, and resynchronization can be immediately achieved. Since only the syndrome needs to be calculated, the circuit scale can be reduced as compared with the case where n decoders are used.

A second aspect of the present invention more specifically represents the memory series and the syndrome calculating means. When an n-bit error correction code is used, it is necessary to calculate n syndromes for a sequence shifted by 1 bit in order to determine whether or not synchronization is established and resynchronize. However, when calculating only the syndrome,
In the calculation of one syndrome and the calculation of the next syndrome, n-1 memory series can be shared. Therefore, n × n storage sequences are not necessary to calculate n syndromes, and 2n−1 storage sequences are enough.

According to a third aspect of the present invention, when it is determined that the error of this sequence is the smallest, the bit shift means changes the original received sequence to m (or m (or 0≤m <n)). (n−m) Shift bits and resynchronize.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. In this embodiment, the present invention is applied to the Iwadare code having a coding rate of 7/8. The coding rate of 7/8 means converting original data of 7 bits into an 8-bit code. Therefore, n = 8, and at the time of decoding, 8-bit data is decoded into 7-bit data.

Generally, when the code sequence W of the convolutional code of the check matrix H is transmitted with the code rate k / n, the error sequences E, E = (E1 (D), ..., En ( D)) is added and a reception sequence Y, Y = (Y1 (D), ..., Yn (D)) is received (D represents a delay operator).

[0017] In this case, S = (S1 (D) , ·····, Sn-k (D)) = YH T to become n-k-dimensional vector sequence S is called syndrome. The code sequence W satisfies WH ^T = 0 and S = (W +
E) H ^T, since the EH ^T, the syndrome S, the transmission sequence is determined by the error sequence regardless of what the was. If there is no error, the syndrome will always be zero.

In actual communication, an error may occur due to noise, jitter, etc. on the channel, and the syndrome may become 1. In such a case, the syndrome temporarily becomes 1. However, when the synchronism is out of sync, 1 is continuously generated in the syndrome, and in the time series, the state in which 1 is generated with a probability of 50% continues.

FIG. 1 shows the circuit configuration of the error correction code decoder and its resynchronization device according to the embodiment. The reception sequence is the serial / parallel (S
/ P) is input to the converter 2. The serial / parallel converter 2 converts the reception sequence into 8-bit parallel data Y1 to Y.
8 and outputs to the Iwadare code decoder 3. The Iwadare code decoder 3 decodes the 8-bit Iwadare code Y1 to Y8 into 7-bit data W1 to W7. Note that S is the syndrome of the decoder 3. Details of the decoder 3 will be described later. The parallel / serial (P / S) converter 3 converts the 7-bit parallel data W1 to W7 into serial data and outputs it.

In the syndrome calculation section 5, R1 to R15 include shift register (hereinafter simply referred to as register) columns. Each register train has the number of stages (42 stages in this embodiment) necessary for calculating the syndromes S0 to S7. The registers R1 to R8 store the data Y of the reception series.
1 to Y8 are input as they are. In the registers R2 to R9, the data Y2 to Y8 and Y1 '("'" which are shifted by one bit are stored.
Indicates the data of the next block). Registers R3 to R10 store data Y3 which is further shifted by 1 bit.
~ Y8, Y1 'to Y2' are input. In this way, the register groups R4 to R11, R5 to R12, R6 to R13,
R7 to R14 and R8 to R15 sequentially store data shifted by 1 bit.

The syndrome calculation section 5 includes registers R1 to R1.
Syndrome S0 based on the data stored in R8
Is calculated. Then, the obtained syndromes S0 are sequentially stored in the syndrome register SR0. Similarly,
The syndrome calculation unit 5 includes registers R2 to R9 and R3 to
R10, R4-R11, R5-R12, R6-R13,
Based on the data stored in R7 to R14 and R8 to R15, the syndromes S1, S2, S3, S4, respectively.
S5, S6 and S7 are calculated and the syndrome registers SR1, SR2, SR3, SR4, SR5 and SR are respectively calculated.
6, stored in SR7.

Each syndrome S0, S1, S2, ..., S
7 is 0, 1, respectively, with respect to the original data Y1 to Y8.
2, ..., Represents a syndrome for a sequence shifted by 7 bits. Syndrome registers SR0, SR1, S
R2, ... Each SR7 has the number of stages necessary for determining the synchronization. Although the number of stages is 32 in this embodiment, the number of stages is not limited to this.

Each syndrome register SR0, SR1,
SR2, ..., SR7 are weight counting means C0, C, respectively.
, C2, ..., C7. Weight counting means C
0, C1, C2, ..., C7 are the syndrome registers S
The number of 1's in R0, SR1, SR2, ..., SR7 is counted and output to the comparison / determination unit 6.

The comparison / determination unit 6 includes weight counting circuits C0, C.
The smallest one is selected from the counting results of 1, C2, ..., C7, and the contact of the switch SW is switched so that the data of the reception series is displaced by the number of bit deviations corresponding thereto. For example, when the reception sequence is shifted by 1 bit, the comparison / determination unit 6
Switches SW to the b side and inputs the previous data Y8 to the serial / parallel converter 2 again. Then, the comparison and determination unit 6
Switches the switch SW to the a side, and the subsequent data Y
Input 1 ′ to Y7 ′ to the serial / parallel converter 2. The serial / parallel converter 2 uses the data Y8, Y
1 ′ to Y7 ′ are converted into parallel data and output to the decoder 3. By repeating this operation, it is possible to shift the arbitrary bit data and resynchronize the decoder 3.

The syndrome calculation unit 5 obtains the syndrome by the same calculation as the decoder 3. Here, the decoder 3
Will be described in detail with reference to FIG. 11 is a 35-stage register, 12 is a 28-stage register, 13 is a 22-stage register, 14 is a 17-stage register, 15 is a 13-stage register, 1
6 is a 10-stage register and 17 is an 8-stage register. Registers 11, 12, 13, 14, 15, 16, 17 have
Receiving sequence data Y1, Y2, Y3, Y4, Y
5, Y6 and Y7 are input.

Reference numeral 19 is a 7-stage register, 20 is a 6-stage register, 21 is a 5-stage register, 22 is a 4-stage register, 23 is a 3-stage register, 24 is a 2-stage register, and 25 is a 1-stage register. The registers 19 to 25 are the registers 11 to 1
It receives the output of 7. Registers 33, 34, 35, 3
Reference numerals 6, 37, 38 and 39 are single-stage registers.

26 is a (10000001) pattern detector, 27 is a (1000001) pattern detector, 28 is a (100001) pattern detector, and 29 is a (1000
1) pattern detector, 30 is a (1001) pattern detector, 31 is a (101) pattern detector, and 32 is a (11)
It is a pattern detector.

40 is an 8-stage register, 41 is a 15-stage register, 42 is a 21-stage register, 43 is a 26-stage register, 4
Reference numeral 4 is a 30-stage register, and 45 is a 33-stage register. The outputs of the registers 40, 41, 42, 43, 44, 45 are the decoded data W2, W3, W4, W5, W6, W7.

(10000001) Pattern detector 2
6, (1000001) pattern detector 27, (100
(001) pattern detector 28, (10001) pattern detector 29, (1001) pattern detector 30, (10
1) pattern detector 31, (11) pattern detector 32
Is a bit pattern detector for detecting an error in Y1 to Y7 of one group of parallel inputs Y1 to Y8.

(11) The pattern detector 32 receives the syndrome S and the output of the one-stage shift register 33, and outputs "1" when both are "1". This output is added by the adder to the Y7 series, that is, the output of the 8-stage register 17. Then, it is delayed by the 33-stage register to obtain the decoded output W7.

On the other hand, (11) the output of the pattern detector 32 is added to the input of the one-stage register 33 through the adder. Then, the input of the one-stage register 33 is set to “0”, and the input of the one-stage register 34 is set to “0” by the adder on the input side of the one-stage register 34 to change “11” of the syndrome series to “00”. To

(101) The pattern detector 31 receives the syndrome S and the output of the one-stage register 34, and outputs "1" when the output of the syndrome S is "1" and the output of the one-stage register 34 is "1". Is output. Originally, it is necessary to detect even when the output of the 1-stage register 33 is "0".
When the output of the stage shift register 33 is 1, (1
1) It is not necessary because the error is corrected by the pattern detector 32. (101) Pattern detector 31
Is added to the output of the 10-stage register 16 by the adder. Then, the decoded output W6 is obtained after being delayed by the 30-stage register 44.

Similarly, the (1001) pattern detector 3
The 0, ..., (10000001) pattern detector 26 corrects the errors in the series Y5 ,. And
Decoded outputs W5 to W1 are obtained through the 26-stage register 43, ..., 8-stage register, and the adder 46.

The syndrome calculation unit 5 also calculates the syndromes S0 to S7, like the decoder 3. However, the syndrome calculation unit 5 does not need to correct the data stored in the registers R1 to R15.

In the above embodiment, the shift register is used as hardware, but the present invention can be implemented by high-speed software processing using a digital signal processor (DSP). In this case, a random access memory (RAM) will be used as the storage means.

Further, in the above embodiment, the case where the present invention is applied to the decoding of the Iwadare code having the coding rate of 7/8 is explained, but the kind of the error correction code is not limited to the Iwadare code. It is applicable to resynchronization of various error correction code decoders using the syndrome pattern decoding method such as BCH code and RS code.

[0037]

As described above, the resynchronization device of the error correction code decoder according to the present invention comprises a decoding means for decoding the error correction code of the reception sequence and a plurality of storage units which shift the reception sequence by a predetermined bit. A storage means having a storage sequence of, a syndrome calculation means for calculating a syndrome based on the data stored in the storage means, and a bit shift means for bit-shifting the reception sequence based on the calculation result of the syndrome calculation means. Therefore, there is an advantage that the synchronization of the decoder can be quickly recovered with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an Iwadare code decoder including a resynchronization device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a circuit configuration of a decoder applied to the Iwadare code decoder.

[Explanation of symbols]

2 ... Serial / parallel converter, 3 ... Iwadare code decoder, 4 ... Parallel / serial converter, 5 ...
Syndrome calculation unit, 6 ... Comparison determination unit, R1 to 1
5 ... Shift register, SR0-7 ... Syndrome register, C0-7 ... Weight counting circuit

Claims (3)

[Claims] 1. A decoding means for decoding an error correction code of a reception sequence, a storage means having a plurality of storage sequences for storing the reception sequence by shifting by a predetermined bit, and a syndrome calculation based on the data stored in the storage means. A resynchronization device for an error correction code decoder, comprising: a syndrome calculation means for performing the above; and a bit shift means for bit-shifting the reception sequence based on the calculation result of the syndrome calculation means. 2. The decoding means decodes an n-bit error correction code, the storage means has a storage series of 2n-1 series, and the syndrome calculation means uses 1n from the storage series of 2n-1. N for received sequences that are shifted bit by bit
2. The resynchronization device for an error correction code decoder according to claim 1, wherein the syndromes of the sequences are calculated, and the sequence in which the number of 1 is smaller than the syndromes of the n sequences is determined. 3. The error according to claim 2, wherein the bit shift means bit-shifts the reception sequence by the number of bit deviations between the sequence determined to be the smallest by 1 in the syndrome calculation means and the original reception sequence. Correction code decoder resynchronization device.