JPH08163053A - Identification recovery circuit - Google Patents

Abstract

PURPOSE: To keep an optimum identification phase condition automatically by eliminating the need for individual adjustment of an identification phase. CONSTITUTION: A clock signal extract circuit 33 extracts a clock signal from an input data signal and the clock signal is given to a voltage controlled phase shifter 35, in which the phase of the clock signal is adjusted by a voltage control signal and the input data signal in a flip-flop 32 is synchronized with the clock signal whose phase is adjusted to obtain a data identification recovery output. The input data signal to the flip-flop 32 is given to two delay elements 361, 362, in which the signal is delayed by delay times D1, D2 which differ from each other and exclusive OR gates 363, 364 take excltusive OR to the output of the flip-flop 32 and the delayed signals respectively, the result is smoothed by smoothing circuits 365, 366 and the outputs are differentially amplified by a differential amplifier 367 to generate a voltage control signal to the voltage controlled phase shifter 35.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discriminating and reproducing circuit used in an optical receiving device of an optical repeater, and more particularly to a circuit technique for automatically controlling a discriminating clock phase.

[0002]

2. Description of the Related Art A conventional identification / reproduction circuit used in an optical receiver is generally constructed as shown in FIG. In FIG. 6, the received pulse signal photoelectrically converted by the light receiving element 1 by the photodiode (PD) is amplified by the equalization amplifier 2 and supplied to the identification reproduction circuit 3.

In the discriminating / reproducing circuit 3, the received pulse signal a from the equalizing amplifier 2 is supplied to a slice amplifying circuit 31, where the amplitude is discriminated based on a threshold voltage Vref1. The pulse signal b whose amplitude has been identified is subjected to time identification and waveform shaping based on a clock signal c described later by the D flip-flop 32, whereby an identification reproduction output d of NRZ data is obtained.

On the other hand, the input reception pulse signal a is supplied to the clock extraction circuit 33. In this clock extraction circuit 33, the input reception pulse signal a is differentiated by the non-linear extraction circuit (Δ) 331 by the differentiation circuit, and the frequency equal to the code rate f0 of the input data is obtained by the narrow band bandpass filter (BPF) 332 having the center frequency f0. The clock signal is reproduced by extracting the clock component of the above and further amplifying it by a limiter amplifier (LIM) 333 so as to have a constant amplitude.

The clock signal obtained here is phase-adjusted by the phase adjuster 34 so that its rising edge coincides with the center of the input data eye pattern of the D-type flip-flop 32, and then the clock signal is sent to the D-type flip-flop 32. It is supplied and used for NRZ data identification and reproduction, and also becomes a clock reproduction output c.

Here, the phase adjuster 34 normally adjusts by the following method. First, using an oscilloscope,
The waveforms of the input data signal b of the D flip-flop 32 and the input clock signal c are observed, and the phase relationship between them is measured. Next, the phase adjuster 3 is adjusted so that the rising edge of the clock signal c is at the center of the eye pattern of the input data b.
Set a delay time of 4.

Another method is to set the delay time of the phase adjuster 34 so as to minimize the error rate while measuring the code error rate of the reproduced output data d obtained from the D flip-flop 32. is there.

Whichever method is used, since the input / output phase of the narrow bandpass filter 332 varies, a phase adjusting step is required at the manufacturing stage of the optical receiver. Since this leads to an increase in cost, no adjustment is desired. Further, even if it is completely adjusted once, the input / output phase may change during long-term use due to the secular change of the narrowband bandpass filter 332, and the optimum phase condition may not be maintained, resulting in characteristic deterioration. .

[0009]

As described above, in the identification / regeneration circuit used in the conventional optical receiving apparatus or the like, due to the variation in the input / output phase of the narrow band pass filter,
The identification phase was adjusted individually, which led to an increase in cost. Also, due to the secular change of the narrow band bandpass filter, the input / output phase may change during long-term use, and the optimum phase condition may not be maintained, which may cause characteristic deterioration.

The present invention has been made to solve the above problems, and it is not necessary to individually adjust the identification phase, and the input / output phase of the narrow bandpass filter changes during long-term use. Even if it is, it is an object of the present invention to provide an identification reproduction circuit that can automatically maintain the optimum identification phase condition.

[0011]

In order to achieve the above object, an identification and reproduction circuit according to the present invention comprises a clock signal extraction circuit for extracting a clock signal from an input data signal, and a clock extracted by the clock signal extraction circuit. A voltage control phase shifter for adjusting the phase of the signal according to the voltage control signal, and a flip-flop for synchronizing the input data signal based on the clock signal phase-adjusted by the voltage control phase shifter to obtain a data identification reproduction output. A first delay element for delaying and outputting the input data signal of the flip-flop by a first delay time, and a delay output of the input data signal for the flip-flop by a second delay time different from the first delay time. A first exclusive theory for calculating the exclusive OR of the second delay element, the output of the first delay element, and the output of the flip-flop And OR gate, and a second exclusive OR gate for calculating the exclusive OR of the outputs of said flip-flop of said second delay element, said first, second
To the voltage control phase shifter by amplifying the difference voltage between the outputs of the first and second smoothing circuits for smoothing the outputs of the exclusive OR gates of The first characteristic is that the differential amplifier for generating a voltage control signal is provided and configured.

A clock generating means for generating a clock signal having a frequency corresponding to the control voltage signal and a flip-flop for synchronizing the input data signal based on the clock signal generated by the clock generating means to obtain a data identification reproduction output. A first delay element that delays and outputs the input data signal of the flip-flop by a first delay time,
A second delay output for delaying the input data signal of the flip-flop by a second delay time different from the first delay time.
Delay element, a first exclusive OR gate for calculating the exclusive OR of the output of the first delay element and the output of the flip-flop, the output of the second delay element and the flip-flop A second exclusive-OR gate for calculating an exclusive-OR with the output of the first and second smoothing circuits for smoothing the outputs of the first and second exclusive-OR gates, respectively. A second feature is that the differential circuit is provided with a differential amplifier that amplifies the difference voltage between the outputs of the first and second smoothing circuits to generate a voltage control signal for the clock generating means.

A third feature is that an offset correction circuit for applying an offset voltage to one input of the differential amplifier is added to any one of the first and second features.

[0014]

In the discriminating and reproducing circuit having the first characteristic configuration, the clock signal is extracted from the input data signal by the clock signal extracting circuit, and the phase of the clock signal is adjusted by the voltage control phase shifter according to the voltage control signal. And supplies it to a flip-flop, which synchronizes an input data signal based on a clock signal to obtain a data identification reproduction output. The input data signal of the flip-flop is fed by the first and second delay elements. They are delayed by first and second delay times different from each other, and an exclusive OR with the output of the flip-flop is calculated for each delayed output by the first and second exclusive OR gates, and each output is calculated. The voltage-controlled phase shifter is smoothed by the first and second smoothing circuits, and each smoothed output is differentially amplified by the differential amplifier. And so as to generate a voltage control signal against.

In the identification and reproduction circuit having the second characteristic, the clock generating means generates a clock signal having a frequency corresponding to the control voltage signal and supplies the clock signal to the flip-flop, and the flip-flop receives the input data signal. A data identification reproduction output is obtained by synchronizing based on a clock signal, and an input data signal of a flip-flop is delayed by first and second delay times which are different from each other by first and second delay elements, respectively. With respect to the delayed output, the exclusive OR with the output of the flip-flop is calculated by the first and second exclusive OR gates, and each calculated output is smoothed by the first and second smoothing circuits, and each smoothed output is obtained. Is differentially amplified by a differential amplifier to generate a voltage control signal for the clock generating means.

In either case, the optimum discriminating phase condition is always maintained by detecting the phase shift of the discriminating clock and performing the closed-loop control of the voltage control phase shifter or the clock generating means. It is automatically corrected to realize no adjustment of the identification clock phase.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described in detail below with reference to FIGS. FIG. 1 shows a configuration in which the identification / reproduction circuit according to the present invention is applied to an optical receiving device. However, in FIG. 1, the same parts as those in FIG. 6 are denoted by the same reference numerals, and different parts will be mainly described here.

In FIG. 1, the clock extraction circuit 33.
The clock signal obtained in (1) is phase-adjusted by the voltage-controlled phase shifter 35, then supplied to the D-type flip-flop 32, and at the same time becomes a clock reproduction output.

The voltage control phase shifter 35 is specifically constructed as shown in FIG. 2, and includes a directional coupler 351, voltage variable capacitance diodes 352 and 353, and resistors 354 and 3.
Using the phase shift circuit of 55, the voltage control signal CON
By controlling the capacitances of the voltage variable capacitance diodes 352 and 353 according to T, the input / output phase can be variably adjusted.

On the other hand, both the input data signal b and the output pulse signal d of the D flip-flop 32 are supplied to the automatic discrimination phase control circuit 36. This circuit 36 includes a delay element 3
61, 362, exclusive OR gates 363, 364, low-pass filters 365, 366, and differential amplifier 367. An offset correction circuit 37 is connected to the (−) side input of the differential amplifier 367 as necessary. It

In the automatic discrimination phase control circuit 36,
The data signal b output from the DC reproduction circuit 31 is supplied to the delay elements 361 and 362. These delay elements 36
1, 362 have mutually different delay times, the delay time D1 of one delay element 361 is set to (T / 2) −Δt, and the delay time D2 of the other delay element 362 is set to (T / 2) + Δt. The data signals e and g delayed by the delay elements 361 and 362 are exclusive OR gates 363 and 364, respectively.
And the exclusive OR operation with the output data signal d of the D-type flip-flop 32.

The high-frequency components of the calculation outputs f and h are removed by the low-pass filters 365 and 366, respectively, and the DC voltage Δ
After being converted into V1 and ΔV2, they are supplied to the (+) input terminal and the (−) input terminal of the differential amplifier 367. An offset correction voltage is applied to the (−) input terminal of the differential amplifier 367 as needed. The differential amplifier 367 amplifies a difference voltage between both inputs ΔV1 and ΔV2 with a predetermined gain G. The voltage signal G (ΔV1−ΔV obtained in this way
2) is supplied to the voltage control phase shifter 35 as the voltage control signal CONT.

The processing operation of the automatic discrimination phase control circuit will be described with reference to FIG. Here, in order to simplify the explanation, it is considered that the D-type flip-flop 32 has no internal delay time.

FIG. 3 shows changes in the waveforms of the signals indicated by a to h in the figure, where a is an input pulse signal, b is an input data signal of the D-type flip-flop 32, c is a clock signal, and d is a D-type flip-flop. Output data signal of the group 32, e is an output signal of the delay element 361, and f is an exclusive OR gate 363.
Is an output signal of the delay element 362, and h is an output signal of the exclusive OR gate 364.

At the output of the D-type flip-flop 32, a change point coincides with the rising edge of the clock signal c, and a waveform d obtained by delaying the input data signal b by about T / 2 is obtained. Here, the input data signal b of the D flip-flop 32 is delayed by a delay time D1 different from T / 2 by a minute time Δt.
= T / 2−Δt, D2 = T / 2 + Δt, the delay waveforms e and g and the output Q waveform d are input to the exclusive OR gates 363 and 364, and then delayed. Gives a pulse train denoted by f and h. This pulse train is used as a low pass filter 365, 3
When smoothed by 66, DC voltages ΔV1 and ΔV2 proportional to the phase shift are obtained.

FIG. 4 shows the relationship between the phases of the two input waveforms e and g input to the exclusive OR gates 363 and 364 and the smoothed output voltages ΔV1 and ΔV2. here,
Since the values of the two delay elements 361 and 362 are shifted by ± Δt, the two exclusive OR gates 363 and 364
From, the average output voltages of ΔV1 and ΔV2 are obtained, respectively.

Assuming that the rising phase difference between the input data signal b and the output data signal d of the D-type flip-flop 32 is τ, the pulse width of f becomes equal to the pulse width of h when τ = T / 2, so ΔV1 = ΔV2 , Τ> T / 2, the pulse width of f becomes narrower and the pulse width of h becomes wider, so ΔV1 <
ΔV2, and conversely, when τ <T / 2, ΔV1> ΔV2.

The DC voltage ΔV1, thus obtained,
ΔV2 is changed to ΔV by a differential amplifier 367 having an appropriate gain G.
By amplifying the difference between 1 and ΔV2 and controlling the voltage control phase shifter with this output voltage, the phase of the clock signal c is automatically adjusted so as to be in the center of the eye pattern of the data signal b. , The optimum phase condition can always be maintained.

By connecting the offset correction circuit 37, it is possible to control so that ΔV1 and ΔV2 are different voltages. According to this, the delay elements 361, 36
Even if the setting accuracy of 2 is poor, the optimum discrimination phase can be maintained.

Another embodiment of the present invention is shown in FIG. Figure 5
In FIG. 1, the same parts as those in FIG.
The details are omitted. In FIG. 5, the identification reproduction circuit 3 of FIG.
Instead of the voltage controlled phase shifter 35 used in the above, a voltage controlled oscillator 38 whose oscillation frequency can be controlled by voltage is used. This configuration is a so-called phase locked loop (PLL), and the phase of the identification clock can be indirectly controlled by controlling the oscillation frequency of the voltage controlled oscillator 38 by the output voltage of the automatic identification phase control circuit 36. The same effect as the first embodiment can be obtained.

As described above in detail, according to each of the above embodiments, the phase shift of the identification clock is detected, and the voltage controlled phase shifter or the voltage controlled oscillator is closed-loop controlled to always maintain the optimum discrimination phase condition. Therefore, it is possible to eliminate the adjustment of the identification phase by automatically correcting the variation of the identification phase caused by the variation of the input / output phase of the narrow band bandpass filter, which has been a problem in the conventional identification reproduction circuit. it can.

Further, even if the input / output phase of the narrow band bandpass filter changes due to aging, the phase control circuit of the present invention automatically corrects the phase shift, so that the characteristics may deteriorate even if it is used for many years. It is possible to realize a highly reliable optical receiving device.

In the above embodiment, the case where the present invention is applied to the identification / reproduction circuit of the optical receiving device has been described, but it goes without saying that it can also be applied to other data communication devices. Other than the above, the present invention can be implemented in various ways without departing from the scope of the invention.

[0034]

As described above, according to the present invention, it is not necessary to individually adjust the identification phase, and even if the input / output phase of the narrow band pass filter changes during long-term use, It is possible to provide an identification reproduction circuit capable of automatically holding the optimum identification phase condition.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration when applied to an optical receiver as an embodiment of an identification / reproduction circuit according to the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of the voltage controlled phase shifter of the above embodiment.

FIG. 3 is a timing chart for explaining the operation of the automatic discrimination phase control circuit of the above embodiment.

FIG. 4 is a characteristic diagram showing input / output characteristics of the automatic discrimination phase control circuit of the above embodiment.

FIG. 5 is a block circuit diagram showing the configuration of another embodiment of the identification / reproduction circuit according to the present invention.

FIG. 6 is a block circuit diagram showing a configuration example of an optical receiving device using a conventional identification and reproduction circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Light receiving element, 2 ... Equalization amplifier, 3 ... Identification reproduction circuit, 3
1 ... Slice amplifier circuit, 32 ... D-type flip-flop (DFF), 33 ... Clock extraction circuit, 331 ... Non-linear extraction circuit, 332 ... Narrow band bandpass filter, 333
... Limiter amplifier, 34 ... Phase adjuster, 35 ... Voltage control phase shifter, 351 ... Directional coupler, 352, 353 ... Voltage variable capacitance diode, 354, 355 ... Resistor, 36 ... Automatic identification phase control circuit, 361. 362 ... Delay element, 36
3,364 ... Exclusive-OR (EX-OR) gate, 36
5,366 ... Low-pass filter, 367 ... Differential amplifier,
37 ... Offset correction circuit, 38 ... Voltage controlled oscillator.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H04B 10/04 10/06 H03L 7/00 A H04L 7/027 // H03K 5/00 H03K 5 / 00 U

Claims (3)

[Claims] 1. A clock signal extraction circuit for extracting a clock signal from an input data signal, a voltage control phase shifter for adjusting the phase of the clock signal extracted by the clock signal extraction circuit according to a voltage control signal, and the input. A flip-flop that synchronizes a data signal based on a clock signal whose phase has been adjusted by the voltage-controlled phase shifter to obtain a data identification reproduction output; and a first delay output of an input data signal of the flip-flop by a first delay time. And a second delay element for delaying and outputting the input data signal of the flip-flop by a second delay time different from the first delay time.
Delay element, a first exclusive OR gate for calculating an exclusive OR of the output of the first delay element and the output of the flip-flop, the output of the second delay element and the flip-flop A second exclusive-OR gate for calculating an exclusive-OR with the output, and first and second smoothing circuits for smoothing the outputs of the first and second exclusive-OR gates, respectively. And a differential amplifier that generates a voltage control signal for the voltage control phase shifter by amplifying a difference voltage between outputs of the first and second smoothing circuits. 2. A clock generating means for generating a clock signal having a frequency corresponding to a control voltage signal, and a flip-flop for synchronizing the input data signal based on the clock signal generated by the clock generating means to obtain a data identification reproduction output. A first delay element that delays and outputs the input data signal of the flip-flop by a first delay time, and an input data signal of the flip-flop by a second delay time different from the first delay time. Delayed output second
Delay element, a first exclusive OR gate for calculating an exclusive OR of the output of the first delay element and the output of the flip-flop, the output of the second delay element and the flip-flop A second exclusive-OR gate for calculating an exclusive-OR with the output, and first and second smoothing circuits for smoothing the outputs of the first and second exclusive-OR gates, respectively. And a differential amplifier that amplifies a difference voltage between outputs of the first and second smoothing circuits to generate a voltage control signal for the clock generating means. 3. The identification reproduction circuit according to claim 1, further comprising an offset correction circuit that applies an offset voltage to one input of the differential amplifier.