JPH08162615A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To provide a semiconductor integrated circuit wherein test data can be inputted without installing an input terminal of the test data. CONSTITUTION: A data input terminal DIN is connected with an internal circuit block 2, via a buffer 1. The output terminal of the internal circuit block 2 is connected with an internal circuit block 3, in which a register for setting test data is included. The data input terminal DIN serves as an input terminal of the data for test. The test data are supplied in the form wherein the 'H' level (VDD) of an ordinary data signal is multiplexed by the amplitude of (1/2) VDD. In order to separate the test data from the amplitude modulated signal, a threshold gate 4 which sets (3/4) VDD as the circuit threshold value and executes binary discrimination is installed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit (eg, LSI), and a test facilitation LSI for inputting predetermined test data to perform a logical operation test.
Regarding

[0002]

2. Description of the Related Art In general, a test facilitation LSI is provided with a terminal for inputting test data in addition to a normal data input terminal and the like. The input test data is set in, for example, the register of the internal circuit, and the operation of the circuit set by the test data is checked to test whether the internal circuit performs the intended logical operation. Is done.

[0003]

If a special terminal is required for inputting test data, the LSI package becomes large and the cost of the LSI increases. The present invention has been made in view of the above points, and provides a semiconductor integrated circuit in which test data can be input without providing a special test data input terminal, thereby reducing the size of the package and reducing the cost. The purpose is to do.

[0004]

The present invention is a semiconductor integrated circuit in which a predetermined external signal input terminal is shared as a normal data input terminal and a test data input terminal, and a signal input to the external signal input terminal is provided. Is characterized in that the normal data is a signal whose amplitude is modulated with the test data, and a threshold circuit for separating the test data from the input signal is incorporated. In the present invention, preferably, the amplitude-modulated signal has an amplitude (1/2) of a VDD "H" level signal as normal data.
It is assumed that the test data of VDD is multiplexed, and the threshold circuit performs binary determination of this amplitude-modulated signal with (3/4) VDD as the circuit threshold.

[0005]

According to the present invention, the test data can be input by using the normal data input terminal, the initial clear terminal, etc. in the form of being superimposed on the "H" level signal input to these terminals. Therefore, miniaturization of the LSI package and cost reduction can be achieved.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an equivalent circuit of an LSI according to an embodiment of the present invention. The data input terminal DIN is connected to the first internal circuit block 2 via the buffer 1, and the output terminal of this circuit block 2 is connected to the second internal circuit block 3. The second circuit block 3 includes a register (not shown) for setting test data.

The data input terminal DIN also serves as a test data input terminal. As will be described later, the test data has a form in which it is multiplexed with the "H" level (VDD) of a normal data signal, specifically, the "H" level signal has an amplitude (1/2).
It is supplied as an amplitude-modulated signal that is amplitude-modulated with VDD test data. In order to separate the test data from the amplitude modulation signal, a threshold circuit 4 for making a binary decision using (3/4) VDD as a circuit threshold value is provided.

The output of the threshold circuit 4 is A in order to selectively supply the separated test data to the internal circuit.
An ND gate 5 is provided. One input terminal of the AND gate 5 is led to the outside as a test mode setting terminal TEST. That is, the test mode setting terminal TEST
"H" level signal is input to the data input terminal DIN
When the input data is amplitude-modulated with the test data, the test data is separated by the threshold circuit 4,
It is supplied to the second internal circuit block 3 through the D gate 5.

FIG. 2 shows a configuration example of the threshold circuit 4. As shown in the figure, a first-stage CMOS inverter composed of a PMOS transistor QP1 and an NMOS transistor QN1, and a PM
It is composed of a second stage CMOS inverter composed of an OS transistor QP2 and an NMOS transistor QN2.
In the first-stage inverter, by designing the ratio W / L of the gate width W and the gate length L of the PMOS transistor QP1 to about twice the W / L of the NMOS transistor QN1,
A circuit threshold of about (3/4) VDD is obtained. The circuit threshold of the second-stage inverter is arbitrary, for example (1 /
2) Set to VDD.

In order to generate a signal in which the test data is multiplexed with the normal data, a multiplexing circuit 7 is required outside the LSI 8 as shown in FIG. In the multiplexing circuit 7, as shown in FIG. 4, the test data is superposed at the timing of the "H" level of the normal data to form an amplitude-modulated signal.

The operation of inputting test data in this embodiment will be described with reference to FIG. As shown in FIG. 4, the data input terminal DIN has a data signal of "H", as described in FIG.
"H" at the timing when the level (VDD) is input
A signal in which test data of amplitude (1/2) VDD is multiplexed to the level is supplied. If the test data is "1" at "H" level and "0" at "L" level, the normal data at "H" level is VDD level at the portion where "1" data is superposed, and "0" level. "The area where the data is superimposed is about (1
/ 2) It becomes VDD.

The threshold value circuit 4 makes a binary decision on the amplitude modulated signal with a threshold value (3/4) VDD, and the test data B is taken out. If the circuit threshold of the buffer 1 is set to a value slightly lower than (1/2) VDD, the buffer 1 separates the normal data A. The extracted test data B is selected by a mode setting signal input to the test mode setting terminal TEST in synchronization with the test data, and is supplied to the second internal circuit block 3.

FIG. 6 shows an LSI equivalent circuit of another embodiment of the present invention. In this embodiment, the initial clear terminal IC for initializing the internal circuit 6 is shared as a test data input terminal. Therefore, the threshold circuit 4 is provided in the initial clear terminal IC as in the previous embodiment, and the AND gate 5 that supplies the output thereof to the internal circuit 6 is provided.
Is provided.

Also in the case of this embodiment, as shown in FIG.
The test data is multiplexed with the initial clear signal which becomes "H" level at a predetermined timing t0. However, in the case of this embodiment, in order to ensure the initial clear, the test data is multiplexed with the initial clear signal at the timing t1 slightly delayed from the input timing t0 of the initial clear signal. Assuming that the level of multiplexing is the same as in the previous embodiment, the test data C is separated and taken out by the threshold value circuit 4 in which the circuit threshold value is set to (3/4) VDD. You can

[0015]

As described above, according to the present invention, a normal data input terminal, an initial clear terminal or the like can be used without providing a special test data input terminal.
The test data can be input in the form of being superimposed on the "H" level signals entering these terminals.
The package can be downsized and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is an equivalent circuit of an LSI according to an embodiment of the present invention.

FIG. 2 is a configuration example of a threshold circuit of the same embodiment.

FIG. 3 shows an external multiplexing circuit of the same embodiment.

FIG. 4 is a diagram for explaining a multiplexing operation of the embodiment.

FIG. 5 is an operation timing chart of the embodiment.

FIG. 6 is an equivalent circuit of an LSI according to another embodiment of the present invention.

FIG. 7 is an operation timing chart of the embodiment.

[Explanation of symbols]

1 ... buffer, 2 ... first internal circuit block, 3 ... second
Internal circuit block, 4 ... Threshold circuit, 5 ... AND gate, 6 ... Internal circuit, 7 ... Multiplexing circuit.

Claims (2)

[Claims] 1. A semiconductor integrated circuit that shares a predetermined external signal input terminal as a normal data input terminal and a test data input terminal, wherein the signal input to the external signal input terminal is normal data. Assuming that the signal is amplitude-modulated by
A semiconductor integrated circuit having a built-in threshold circuit for separating the test data from the input signal. 2. The amplitude-modulated signal has an amplitude (1/2) VDD as an "H" level signal of VDD as normal data.
Of the test data is multiplexed, and the threshold value circuit performs binary determination of the amplitude-modulated signal using (3/4) VDD as a circuit threshold value. The semiconductor integrated circuit according to claim 1.