JPH08162474A - Bipolar transistor manufacturing method - Google Patents

Abstract

PURPOSE: To obtain a bipolar transistor of an SICOS structure, which can reduce the area of an emitter by a method wherein an external base region on the projected sidewall parts of an epitaxial layer and after a sidewall is formed on a projected top surface, a diffusion is performed for forming an emitter region. CONSTITUTION: A N-type epitaxial layer 3 is grown on a semiconductor substrate, a thermal diffusion is performed and an oxide film 16 and a nitride film 17 are formed in order. Then, the films 17 and 16 are etched away excluding emitter and base regions, the layer 3 is subjected to anisotropic etching using both of these films 16 and 17 as masks, and projected side walls are formed. Then, the surface of a polysilicon film 22 is oxidized; impurities being contained in this film 22 are made to diffuse in the layer 3 of the projected sidewalls; and an external base region 12 is formed. The exposed film 17 is etched; the film 16 is made to expose; an oxide film 25 is formed on the whole surface; and a sidewall 25 is formed on the projected top surface 22 and the end surfaces of an oxide film 24 by anisotropic etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar transistor, and more particularly to an S electrode having electrodes drawn out from the side wall of the device.
The present invention relates to a method for manufacturing a bipolar transistor having an ICOS (sidewall base contact structure) structure.

[0002]

2. Description of the Related Art A bipolar transistor having a SICOS structure has been proposed for the purpose of lowering power consumption and speed of a bipolar transistor. A method of manufacturing a conventional bipolar transistor having a SICOS structure will be described below by taking an NPN bipolar transistor as an example. First, P
Impurity diffusion for forming the N type buried layer 2 is performed on the type silicon semiconductor substrate 1, and then the N type epitaxial layer 3 is grown on the silicon semiconductor substrate 1. A P-type isolation layer 4 for element isolation and a collector wall 5 connected to the N-type buried layer 2 previously formed to form a collector region are formed in the N-type epitaxial layer 3. An insulating film other than an oxide film, for example, a nitride film 6 is formed on the entire surface of the N-type epitaxial layer 3, and then the nitride film 6 other than the regions where the emitter and the base are to be formed is removed by etching. Remaining nitride film 6
Is used as a mask to etch the epitaxial layer 3 to leave the epitaxial layer 3 in the regions where the emitter and base are to be formed in a convex shape. At this time, the epitaxial layer is made to enter inside the end portion of the nitride film by etching. afterwards,
An oxide film 7 is formed on the exposed epitaxial layer surface by thermal oxidation, and another mask film, for example, a metal film 8 is deposited. At this time, a portion where the oxide film 7 is exposed without being covered with the metal film 8 is left on the convex side wall portion below the nitride film (FIG. 9).

Using the metal film 8 as a mask, the epitaxial layer 3
The oxide film 7 exposed on the side wall of the convex shape is removed by etching, and the epitaxial layer 3 is exposed only on the side wall of the convex shape. After that, the metal film 8 is removed, and a polysilicon film 9 to be a base extraction electrode is formed on the entire surface. The polysilicon film 9 can be formed by diffusing P-type impurities into a doped silicon film or a non-doped polysilicon film. After that, patterning is performed to form an oxide film 10 serving as an interlayer insulating film on the entire surface (FIG. 10).

The oxide film 10, the polysilicon film 9 and the nitride film 6 are removed by etching only on the convex upper surfaces of the emitter and base formation regions to expose the epitaxial layer 3. P-type impurities are diffused to form the base region 11 on the exposed surface of the epitaxial layer 3 (FIG. 11). Next, thermal oxidation is performed to oxidize the exposed end portion of the polysilicon film 9. By this heat treatment, at the same time, the P-type impurity is diffused from the polysilicon film 9 to the convex side wall portion, and the external base region 12 connected to the previously formed base region 11 is formed.

To form the emitter 13, N-type impurities are diffused into the base region 11 (FIG. 12). Then, contact holes (not shown) in the collector region and the base region are opened to form a collector electrode 15 and an emitter electrode 14,
A bipolar transistor of SICOS structure is obtained (Fig. 1
3).

[0006]

The conventional bipolar transistor formed as described above has a reduced parasitic capacitance and is capable of high-speed operation. However, in the case of further speeding up, the emitter area is smaller than that of the nitride film 6. Depends on the forming accuracy, and because the formation of the emitter region is not self-aligned,
There was a limit to the reduction. Therefore, there is a problem that there is a limit to the speedup of the transistor.

[0007]

In order to solve the above problems, the present invention forms a reverse conductivity type buried layer forming a part of a collector region on a semiconductor substrate of one conductivity type, and the buried layer is formed. In the method of manufacturing a bipolar transistor, a reverse conductivity type epitaxial layer is grown on a layer, element isolation is performed, and a reverse conductivity type collector region, a one conductivity type base region, and a reverse conductivity type emitter region are formed. A step of forming a first insulating film on the surface of the layer, a step of removing the first insulating film except for the emitter and base formation planned regions,
A step of etching the epitaxial layer with the first insulating film as a mask to form a convex shape, and forming a second insulating film on the entire surface, and forming a second insulating film on the convex side wall portion to form a sidewall. And a step of forming a third insulating film on the surface of the epitaxial layer by using the sidewall as a mask, a part of the second insulating film is removed, and only the side wall of the convex shape is formed. Exposing the epitaxial layer, forming a base electrode metal in contact with the exposed epitaxial layer on the entire surface, forming a flattening film on the base electrode, flattening, and etching back the first electrode. A step of exposing the insulating film, and a fourth step on the surface of the base electrode.
Forming an insulating film, forming an external base region on the convex side wall portion, removing the first insulating film, forming a fifth insulating film on the entire surface, and forming the fifth insulating film. Forming a sidewall on the base electrode on the convex top surface and the end of the fourth insulating film with a film; and forming a base region on the epitaxial layer surface on the convex top surface in contact with the external base region. The method is characterized by including a step of forming, an step of forming an emitter area on the base area, and a step of forming a collector area in contact with the buried layer.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below by taking an NPN bipolar transistor as an example. N forming a part of the collector region on the P-type silicon semiconductor substrate 1
Impurity diffusion for forming the buried type layer 2 is performed, and then the N type epitaxial layer 3 is grown on the silicon semiconductor substrate 1 by about 1 micron. When element isolation is performed by impurity diffusion, a P-type buried layer can be formed in the same manner as the N-type buried layer. Thermal diffusion is performed to form the N-type buried layer. After that, the oxide film 16 is formed to 200 angstroms on the N-type epitaxial layer 3 and the nitride film 17 is formed to 30 Å thereon.
00 angstroms are formed. Here, although the oxide film 16 is not always necessary, it is preferably formed thin in consideration of the difference in the coefficient of thermal expansion between the silicon semiconductor substrate 1 and the nitride film 17. Except for the emitter and base formation planned area,
The nitride film 17 and the oxide film 16 are removed by etching. Then, using the nitride film 17 and the oxide film 16 as a mask, the N-type epitaxial layer 3 is anisotropically etched to a height of about 500.
A convex shape of 0 angstrom is formed. The height of this convex shape may be set to a height such that the contact resistance of the external base region formed in a later step becomes sufficiently small, and is appropriately set. Further, when the convex shape is formed by anisotropic etching, the side wall becomes a substantially vertical columnar shape, but it is also possible to perform isotropic etching and make the side wall inclined. After that, the exposed epitaxial layer 3
An oxide film 18 of 200 angstrom is formed on the surface (FIG. 1).

A nitride film 19 of 3000 angstrom is formed on the entire surface (FIG. 2), and the nitride film 19 in the LOCOS oxide film formation planned region is removed by etching for element isolation. A LOCOS oxide film is formed by the recess method (FIG. 3). In FIG. 3, 20 is a LOCOS oxide film, and 21 is a channel stopper. Here, the previously formed oxide film 18 is L
It is necessary as a mask for performing OCOS oxidation, and is used when another element isolation method is adopted or in another process.
When forming the S oxide film, the oxide film 18 is not always necessary. As an element isolation method, a method of diffusing impurities is possible in addition to the method of using an oxide film.

The nitride film 19 is anisotropically etched to form sidewalls made of the nitride film 19 on the convex side wall portions. After that, thermal oxidation is performed to increase the thickness of the oxide film 18 in the portion which is not masked by the sidewall made of the nitride film 19 in the oxide film 18 formed earlier. Next, in order to form a collector wall that constitutes the collector region, a part of the oxide film 18 in the region where the collector wall is to be formed is etched using a photoresist as a mask, and phosphorus is implanted into the epitaxial layer 3 using this photoresist as a mask. Ion implantation is performed at a dose of 1E15 / cm2 and an acceleration voltage of 30 KeV. After removing the photoresist, 3 at 1150 ° C
Thermal diffusion is performed for 0 minutes to form the collector wall 5 that is in contact with the previously formed N-type buried layer 2 (FIG. 4).

The nitride film 19 is etched by hot phosphoric acid or isotropic etching. At this time, the nitride film 19 is left in the vicinity of the convex bottom surface. This nitride film 1
By leaving 9 as the impurity, the impurities forming the external base region are diffused only from the convex side wall portion, and it is possible to prevent the formation of an unnecessary external base. Further, the nitride film 17 remains because it is sufficiently thick. Then, the exposed oxide film 18 is etched to expose the epitaxial layer 3 on the side wall of the convex shape. Non-doped polysilicon 22 is formed on the entire surface by the CVD method, and boron, which is a P-type impurity, is immediately injected at an injection amount of 1E14 to 1E15 / cm2 and an acceleration voltage of 20 Ke.
Inject with V. At this time, in order to reduce the resistance, polysilicon may be silicided with Ti or the like, or WSi may be formed on the polysilicon. However, when silicidation or silicide is formed on the surface, an oxide film is formed on the surface of the polysilicon film in a later step, so that it is necessary to further form the polysilicon film by the CVD method to about 1000 angstroms. It is also possible to use a doped silicon film instead of the non-doped silicon film. In this case, it is not necessary to implant impurities into the polysilicon film. Next, a photoresist 23 as a flattening film is applied thickly on the polysilicon film 22, and after flattening, etching back is performed under the condition that the etching rate of the photoresist is equal to that of the polysilicon film (different to the dotted line portion shown in FIG. 5). Then, the polysilicon film 22 on the nitride film 17 is etched.
Is etched to expose the nitride film 17 (FIG. 5).

After removing the photoresist 23 remaining on the polysilicon film 22, the polysilicon film 22 in the region where the collector electrode is to be formed is etched and the surface of the polysilicon film 22 is oxidized to form an oxide film 24. At the same time, the thermal oxidation diffuses the impurities contained in the polysilicon film 22 into the epitaxial layer 3 having the convex side wall to form the external base region 12 (FIG. 6).

The exposed nitride film 17 is etched with hot phosphoric acid to expose the oxide film 16. Then CVD on the entire surface
By forming the oxide film 25 on the entire surface by anisotropic etching and etching the oxide film 25 by anisotropic etching to form sidewalls made of the oxide film 25 on the end faces of the polysilicon film 22 and the oxide film 24 on the convex top surface. (Fig. 7). By forming the side wall, the emitter area can be reduced. At this time, similar sidewalls are formed also in the region where the collector electrode is to be formed, but since they are not necessary for the present invention, description thereof will be omitted. The lateral dimension of the sidewall formed on the convex top surface is preferably the same as or slightly wider than the lateral diffusion dimension of the external base 22 previously formed. However, the invention is not necessarily limited to this, and a base region formed later and the external base region 12 formed earlier can be easily joined and the area of the emitter region can be reduced. It is possible to appropriately select the dimensions that are possible.

After the oxide film 16 is removed by etching using the oxide film 25 as a mask, a polysilicon film serving as an emitter electrode and a collector electrode is formed on the entire surface, and a P-type impurity is added in the polysilicon film to form a base region. A certain boron is injected with an injection amount of 3E15 / cm2 and an acceleration voltage of 50 KeV.
Then, heat treatment is performed at 1020 ° C. for 15 seconds by a lamp annealing method to diffuse impurities in the epitaxial layer 3 to form the base region 11 connected to the external base region previously formed. Here, the oxide film 16 can be removed after the nitride film 17 is removed by etching before the oxide film 25 is formed. Next, in order to form an emitter region, arsenic, which is an N-type impurity, is implanted with an amount of 1E16.
Ion implantation is performed with a cm 2 acceleration voltage of 80 KeV to form an emitter region 13. The polysilicon film is patterned to form the emitter electrode 14 and the collector electrode 15 (FIG. 8). Hereinafter, a bipolar transistor having a SICOS structure is obtained according to a usual method for manufacturing a bipolar transistor.

[0015]

As described above, according to the manufacturing method of the present invention, in addition to high-speed circuit operation and high integration, which are the advantages of the bipolar transistor of the conventional SICOS structure, the base, The emitter can be self-aligned, and the side wall is formed to reduce the emitter area. Therefore, the circuit operation can be further speeded up. Further, when the external base is formed, the nitride film 19 and the oxide film 18 are partially left in the vicinity of the convex bottom portion, so that the external base region is formed only on the convex side wall portion, and the base attributed to the external base region is formed. There is an effect that the capacitance between the collectors can be suppressed to be small and the device characteristics can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram illustrating a method for manufacturing a bipolar transistor of the present invention.

FIG. 2 is an explanatory diagram illustrating a method for manufacturing a bipolar transistor of the present invention.

FIG. 3 is an explanatory diagram illustrating a method for manufacturing a bipolar transistor of the present invention.

FIG. 4 is an explanatory diagram illustrating a method for manufacturing a bipolar transistor of the present invention.

FIG. 5 is an explanatory view illustrating a method for manufacturing a bipolar transistor of the present invention.

FIG. 6 is an explanatory diagram illustrating a method for manufacturing a bipolar transistor of the present invention.

FIG. 7 is an explanatory diagram illustrating a method for manufacturing a bipolar transistor of the present invention.

FIG. 8 is an explanatory diagram illustrating a method for manufacturing a bipolar transistor of the present invention.

FIG. 9 is an explanatory diagram illustrating a conventional method for manufacturing a bipolar transistor.

FIG. 10 is an explanatory diagram illustrating a conventional method for manufacturing a bipolar transistor.

FIG. 11 is an explanatory diagram illustrating a conventional method for manufacturing a bipolar transistor.

FIG. 12 is an explanatory diagram illustrating a conventional method for manufacturing a bipolar transistor.

FIG. 13 is an explanatory diagram illustrating a conventional method for manufacturing a bipolar transistor.

[Explanation of symbols]

 1 Silicon Semiconductor Substrate 2 Buried Layer 3 Epitaxial Layer 4 Separation Layer 5 Collector Wall 6 Nitride Film 7 Oxide Film 8 Metal Film 9 Polysilicon Film 10 Oxide Film 11 Base Region 12 External Base Region 13 Emitter Region 14 Emitter Electrode 15 Collector Electrode 16 Oxide film 17 Nitride film 18 Oxide film 19 Nitride film 20 LOCOS oxide film 21 Channel stopper 22 Polysilicon film 23 Photoresist 24 Oxide film 25 Oxide film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/761

Claims (1)

[Claims] 1. A reverse conductivity type buried layer forming a part of a collector region is formed on a single conductivity type semiconductor substrate, and a reverse conductivity type epitaxial layer is grown on the buried layer to form a device. A method of manufacturing a bipolar transistor, which comprises separating and forming a collector region of opposite conductivity type, a base region of one conductivity type, and an emitter region of opposite conductivity type, a step of forming a first insulating film on a surface of the epitaxial layer, A step of removing the first insulating film except for an emitter and a base formation planned region; a step of etching the epitaxial layer by using the first insulating film as a mask to form a convex shape; Forming a film, forming a sidewall on the convex side wall portion with the second insulating film, and forming a third insulating film on the surface of the epitaxial layer using the sidewall as a mask, Removing a part of the second insulating film to expose the epitaxial layer only on the convex side wall portion; forming a base electrode metal in contact with the exposed epitaxial layer on the entire surface; Forming a flattening film on the electrode metal, flattening, and etching back to expose the first insulating film; forming a fourth insulating film on the surface of the base electrode; A step of forming an external base region on the base, removing the first insulating film, forming a fifth insulating film on the entire surface, and forming the fifth insulating film on the base electrode and the convex top surface of the fifth insulating film. Forming a side wall at the end of the fourth insulating film; forming a base region in contact with the external base region on the surface of the convex top epitaxial layer; and forming an emitter region on the base region. Forming And a step of forming a collector region connected to the buried layer, the method of manufacturing a bipolar transistor.