JPH08160409A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
- Publication number
- JPH08160409A JPH08160409A JP30655594A JP30655594A JPH08160409A JP H08160409 A JPH08160409 A JP H08160409A JP 30655594 A JP30655594 A JP 30655594A JP 30655594 A JP30655594 A JP 30655594A JP H08160409 A JPH08160409 A JP H08160409A
- Authority
- JP
- Japan
- Prior art keywords
- shielding layer
- liquid crystal
- light shielding
- light
- display device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000010408 film Substances 0.000 claims description 26
- 238000010438 heat treatment Methods 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910000846 In alloy Inorganic materials 0.000 claims description 2
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 claims 2
- 230000000007 visual effect Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 77
- 229910021417 amorphous silicon Inorganic materials 0.000 description 12
- 229910019923 CrOx Inorganic materials 0.000 description 11
- 239000011159 matrix material Substances 0.000 description 11
- 238000004544 sputter deposition Methods 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- AYTAKQFHWFYBMA-UHFFFAOYSA-N chromium dioxide Chemical compound O=[Cr]=O AYTAKQFHWFYBMA-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133512—Light shielding layers, e.g. black matrix
Landscapes
- Liquid Crystal (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は液晶表示装置に関し、特
に、良好な視認を妨げる反射光を抑えた液晶表示装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device which suppresses reflected light which hinders good visual recognition.
【0002】[0002]
【従来の技術】液晶表示装置は薄型、軽量、低消費電力
などの特徴があり、OA機器、AV機器などの分野で実
用化が進んでいる。特に、スイッチング素子として、薄
膜トランジスタ(以下、TFTと略す)を用いたアクテ
ィブマトリクス型は、原理的にデューティ比100%の
スタティック駆動をマルチプレクス的に行うことがで
き、大画面、高精細な動画ディスプレイに使用されてい
る。2. Description of the Related Art Liquid crystal display devices are characterized by thinness, light weight and low power consumption, and are being put to practical use in the fields of OA equipment, AV equipment and the like. In particular, the active matrix type using a thin film transistor (hereinafter abbreviated as TFT) as a switching element can perform static driving with a duty ratio of 100% in a multiplexed manner in principle, and has a large screen and a high-definition moving image display. Is used for.
【0003】アクティブマトリクス型液晶表示装置は、
一対の透明な基板間で対向配置された透明電極間に、液
晶が装填されてなる画素容量へ所望の電圧が印加可能に
構成された表示画素が、マトリクス状に配列されてな
る。透明電極はそれぞれ透明基板により支持されてお
り、一方はマトリクス状に形成された画素電極であり、
他方は全面的に形成された共通電極である。各画素電極
にはそれぞれ薄膜トランジスタ(TFT:Thin Film Tr
ansistor)が接続され、入力信号電圧が選択される。各
TFTは線順次走査により選択されて、同一行について
一斉にONされ、これに同期したデータ信号電圧が各画
素電極に印加される。共通電極も所定の電圧に設定さ
れ、各画素容量に印加された電圧はTFTのOFF抵抗
により次フィールドで書き換えられるまで保持され液晶
層に一定の電界が形成される。液晶は静電的に反応して
光学的状態が変化し、透過光が変調される。このよう
に、画素ごとに変調された透過光は合成して視認され、
表示画像として観察される。The active matrix type liquid crystal display device is
Display pixels configured so that a desired voltage can be applied to a pixel capacitance in which liquid crystal is loaded are arranged in a matrix between transparent electrodes that are arranged to face each other between a pair of transparent substrates. The transparent electrodes are each supported by a transparent substrate, one of which is a pixel electrode formed in a matrix,
The other is a common electrode formed over the entire surface. Each pixel electrode has a thin film transistor (TFT).
ansistor) is connected and the input signal voltage is selected. Each TFT is selected by line-sequential scanning and turned on simultaneously for the same row, and a data signal voltage synchronized with this is applied to each pixel electrode. The common electrode is also set to a predetermined voltage, the voltage applied to each pixel capacitance is held by the OFF resistance of the TFT until it is rewritten in the next field, and a constant electric field is formed in the liquid crystal layer. The liquid crystal reacts electrostatically to change its optical state and modulate the transmitted light. In this way, the transmitted light modulated for each pixel is synthesized and visually recognized,
Observed as a display image.
【0004】以下、TFTとして、ゲートを半導体層よ
りも上層に配した正スタガー型を用いた液晶表示装置に
ついて、従来例を説明する。図5は、単位画素部分の平
面図であり、図6は図5のB−B線に沿った断面図であ
る。ガラスなどの基板(50)上には、Crからなる遮
光層(51)、及び、電荷保持用の補助容量電極(5
2)が形成され、これら遮光層(51)と補助容量電極
(52)を覆う全面には層間絶縁層(53)が形成され
ている。層間絶縁層(53)上には、画素電極(54
P)、ドレインライン(54L)、TFTのソース電極
(54S)及びドレイン電極(54D)が、酸化インジ
ウム・スズ(ITO:indium tin oxide)により形成さ
れている。ソース電極(54S)とドレイン電極(54
D)上には、ソース・ドレイン領域にそれぞれ形成され
たN+a−Si層(55N)を介してa−Si層(5
5)、ゲート絶縁層(56)及びゲート電極(57G)
が同一のパターンで積層されてTFTを構成している。
また画素電極(54P)の周辺、ドレインライン(54
L)に交差する領域には、ゲートライン(57L)が配
置され、TFT部と同一の構造で、下層にa−Si層
(55)とゲート絶縁層(56)を配した積層体からな
る。A conventional example of a liquid crystal display device using a positive stagger type in which a gate is disposed above a semiconductor layer as a TFT will be described below. 5 is a plan view of a unit pixel portion, and FIG. 6 is a sectional view taken along line BB of FIG. On a substrate (50) such as glass, a light shielding layer (51) made of Cr and an auxiliary capacitance electrode (5) for holding charges are provided.
2) is formed, and an interlayer insulating layer (53) is formed on the entire surface covering the light shielding layer (51) and the auxiliary capacitance electrode (52). A pixel electrode (54) is formed on the interlayer insulating layer (53).
P), the drain line (54L), the source electrode (54S) and the drain electrode (54D) of the TFT are formed of indium tin oxide (ITO). Source electrode (54S) and drain electrode (54
D) on the a-Si layer (5) via the N + a-Si layers (55N) formed in the source / drain regions, respectively.
5), gate insulating layer (56) and gate electrode (57G)
Are stacked in the same pattern to form a TFT.
The periphery of the pixel electrode (54P) and the drain line (54P
A gate line (57L) is arranged in a region intersecting L), and has a structure identical to that of the TFT part, and is composed of a laminated body in which an a-Si layer (55) and a gate insulating layer (56) are arranged as a lower layer.
【0005】遮光層(51)は、TFT部を覆う領域に
配置されており、基板(50)の下方からの光がa−S
i層(55)へ入射するのを遮り、TFTのOFF抵抗
が下がって電圧の保持率が低下するのを防いでいる。画
素電極(54P)は、平面的に、ゲートライン(57
L)とドレインライン(54L)に囲まれた領域に位置
し、補助容量電極(52)は画素電極(54P)に部分
的に重畳されて電荷保持用の補助容量を構成している。The light-shielding layer (51) is arranged in a region covering the TFT portion, and light from below the substrate (50) is aS.
It blocks the incidence on the i layer (55) and prevents the OFF resistance of the TFT from decreasing and the voltage holding ratio from decreasing. The pixel electrode (54P) has a gate line (57P) in plan view.
L) and the drain line (54L), the auxiliary capacitance electrode (52) partially overlaps the pixel electrode (54P) to form an auxiliary capacitance for holding charges.
【0006】以上の構造のTFTアレイ基板の対向位置
には、液晶層(70)を挟んで、基板(60)上にCr
からなる遮光層(61)と、遮光層(61)を覆う全面
にITOの共通電極(62)が形成されてなる対向基板
が配置されている。共通電極(62)は、液晶を挟ん
で、基板(50)側の各画素電極(54P)に共通に対
向されて画素容量を構成し、遮光層(61)は各画素容
量間の全域に配置されて、ブラックマトリクスを形成し
ている。即ち、各画素電極(54P)により液晶層(7
0)及び共通電極(62)が規格されて表示画素である
画素容量が構成されるとともに、画素容量の領域外には
遮光層(61)が配置され、ブラックマトリクスとして
変調されない光を遮断することによりコントラスト比が
向上されている。At a position facing the TFT array substrate having the above structure, a liquid crystal layer (70) is sandwiched, and Cr is provided on the substrate (60).
A light shielding layer (61) made of and a counter substrate having a common electrode (62) of ITO formed on the entire surface covering the light shielding layer (61) are arranged. The common electrode (62) is commonly opposed to each pixel electrode (54P) on the substrate (50) side with the liquid crystal sandwiched therebetween to form a pixel capacitance, and the light shielding layer (61) is arranged in the entire area between each pixel capacitance. To form a black matrix. That is, the liquid crystal layer (7
0) and the common electrode (62) are standardized to form a pixel capacitance which is a display pixel, and a light shielding layer (61) is arranged outside the region of the pixel capacitance to block light that is not modulated as a black matrix. The contrast ratio is improved by.
【0007】[0007]
【発明が解決しようとする課題】遮光層(61)を構成
するCrは反射率が高く、対向基板側を表示画面とした
構成の場合、周囲光がブラックマトリクスとして形成さ
れた遮光層(61)により反射され、この反射光により
視認が妨害され、表示品位の悪化を招いていた。また、
TFTアレイ基板側を表示画面とした場合でも、ノーマ
リ・ホワイト・モードでは、TFTアレイ基板側から画
素領域外に入射した周囲光は、Crからなる補助容量電
極(52)やAlからなるゲートライン(57L)で反
射されるか、あるいは、ITOからなるドレインライン
(54L)から液晶層(70)を通り抜けて、遮光層
(61)で反射され、同じ光路を戻って射出されるた
め、やはり、視認の妨害となる。Cr constituting the light-shielding layer (61) has a high reflectance, and when the counter substrate side is used as a display screen, the light-shielding layer (61) in which ambient light is formed as a black matrix is used. The reflected light interferes with the visual recognition, resulting in deterioration of display quality. Also,
Even when the TFT array substrate side is used as the display screen, in the normally white mode, ambient light incident from the TFT array substrate side to the outside of the pixel region is accompanied by the auxiliary capacitance electrode (52) made of Cr and the gate line made of Al ( 57L), or it passes through the liquid crystal layer (70) from the drain line (54L) made of ITO, is reflected by the light shielding layer (61), and is emitted back through the same optical path. Will interfere with.
【0008】一方、このような問題を解決するために、
遮光層(61)をCrと低反射のCrOXの2層構造と
し、CrOX膜を表示画面側に配することにより、周囲
光の反射を抑え、表示品位を向上するものがある。しか
し、CrとCrOXの積層体の成膜には、例えば、Cr
のスパッタリングにおいて、遮光性の高いCrを厚めに
積層するとともに、反射防止用のCrOXを成膜するた
めに酸素を所定時間導入する必要がある。このため、成
膜装置として、酸素を導入する系、及び、これの制御系
を備えたものが要され、コスト的に負担が大きくなって
いた。On the other hand, in order to solve such a problem,
There is a light-shielding layer (61) having a two-layer structure of Cr and CrOx having low reflection, and arranging the CrOx film on the display screen side to suppress reflection of ambient light and improve display quality. However, for forming a laminated body of Cr and CrO x, for example, Cr
In the sputtering, it is necessary to stack Cr having a high light-shielding property thickly and to introduce oxygen for a predetermined time in order to form CrOx for antireflection. Therefore, as a film forming apparatus, an apparatus for introducing oxygen and a control system for the same are required, and the cost is increased.
【0009】[0009]
【課題を解決するための手段】本発明はこの課題を解決
するために成され、第1に、内部に液晶を密封して貼り
合わされた一対の基板の対向面の一方に形成され液晶駆
動用の画素容量の一方を成す複数の画素電極と、該各画
素電極に接続された薄膜トランジスタと、前記対向面の
他方に全面的に形成され前記各画素電極により規格され
る複数の前記画素容量の他方を一体的に成す共通電極
と、前記画素容量の領域外に形成された遮光層を有する
液晶表示装置において、前記遮光層は前記共通電極と同
一の前記基板上に形成され、前記遮光層と前記共通電極
の接触界面には、前記遮光層の表面が酸化された膜が形
成されていることを特徴とする液晶表示装置。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. First, it is formed on one of opposing surfaces of a pair of substrates in which liquid crystal is hermetically bonded and used for driving a liquid crystal. A plurality of pixel electrodes forming one of the pixel capacitances, a thin film transistor connected to each of the pixel electrodes, and the other of the plurality of pixel capacitances entirely formed on the other of the facing surfaces and standardized by the pixel electrodes. In a liquid crystal display device having a common electrode integrally formed with and a light shielding layer formed outside the area of the pixel capacitance, the light shielding layer is formed on the same substrate as the common electrode, and the light shielding layer and the light shielding layer A liquid crystal display device, wherein a film in which the surface of the light shielding layer is oxidized is formed at the contact interface of the common electrode.
【0010】第2に、第1の構成において、前記共通電
極はインジウムとスズの酸化物合金により形成され、前
記遮光層はCrにより形成され、かつ、前記遮光層の表
面が酸化された膜は、加熱処理により形成されたCrの
酸化膜である構成とした。Secondly, in the first structure, the common electrode is formed of an oxide alloy of indium and tin, the light shielding layer is formed of Cr, and the surface of the light shielding layer is oxidized. The Cr oxide film is formed by heat treatment.
【0011】[0011]
【作用】前記第1の構成で、遮光層上に、遮光層の表面
酸化膜を形成することにより、周囲光が遮光層表面で反
射されて視認を妨害するのが防がれ、表示品位が向上す
る。前記第2の構成で、遮光層を構成するCrと共通電
極を構成するインジウム・スズの酸化物合金との界面
に、加熱処理により低反射であるCrの酸化膜を形成す
ることにより、光の反射が抑えられ、表示品位が向上す
る。また、このCrの酸化膜の形成は、加熱処理の工程
を追加するのみで、特別の成膜装置が不要であるので、
コストの増大が避けられる。With the first structure, by forming the surface oxide film of the light-shielding layer on the light-shielding layer, it is possible to prevent ambient light from being reflected on the surface of the light-shielding layer and hindering visual recognition, and to improve the display quality. improves. In the second configuration, a low-reflectance Cr oxide film is formed by heat treatment at the interface between Cr that forms the light-shielding layer and the indium-tin oxide alloy that forms the common electrode, and Reflection is suppressed and display quality is improved. Further, since the formation of the Cr oxide film is performed only by adding a heat treatment step, no special film forming apparatus is required.
Increased cost can be avoided.
【0012】[0012]
【実施例】続いて、本発明の実施例を図面を参照しなが
ら説明する。図1は本発明の第1の実施例に係る液晶表
示装置の単位画素部分の平面図であり、図2は図1のA
−A線に沿った断面図である。ガラスなどの透明な基板
(10)上には、Crのスパッタリングとフォトエッチ
により、TFTの領域に遮光層(11)が形成され、画
素容量領域に補助容量電極(12)が形成されている。
遮光層(11)及び補助容量電極(12)を覆う全面に
は、CVDによりSiO2が積層されて層間絶縁層(1
3)が形成されている。層間絶縁層(13)上にはIT
Oのスパッタリングとフォトエッチにより、画素電極
(14P)とドレインライン(14L)が形成され、そ
れぞれソース電極(14S)部とドレイン電極(14
D)部をもって近接されている。ソース電極(14S)
とドレイン電極(14D)が近接された領域上には、ソ
ース・ドレイン領域上のN+a−Si層(15N)を介
して、a−Si、SiNX及びAlを連続的に成膜し、
同じパターンでエッチングすることにより、a−Si層
(15)、ゲート絶縁層(16)及びゲート電極(17
G)が積層されてTFTを構成している。画素電極(1
4P)の周辺、ドレインライン(14L)に交差する領
域には、ゲート電極(17G)と一体のゲートライン
(17L)が形成され、TFT部と同様、下層にa−S
i層(15)とゲート絶縁層(16)が配された構造と
なっている。N+a−Si層(15N)は、CVDによ
る成膜とフォトエッチ、あるいは、スパッタリング時に
ソース・ドレイン配線(14)を成すITO中に含有さ
せた燐を、a−SiのプラズマCVDによる成膜中に反
応させることで、界面にN+型の薄膜を形成したもので
ある。Embodiments of the present invention will now be described with reference to the drawings. 1 is a plan view of a unit pixel portion of a liquid crystal display device according to a first embodiment of the present invention, and FIG.
It is a sectional view taken along the line A. On a transparent substrate (10) such as glass, a light shielding layer (11) is formed in the TFT region and an auxiliary capacitance electrode (12) is formed in the pixel capacitance region by Cr sputtering and photoetching.
SiO2 is deposited on the entire surface covering the light shielding layer (11) and the auxiliary capacitance electrode (12) by CVD to form an interlayer insulating layer (1
3) is formed. IT on the interlayer insulation layer (13)
A pixel electrode (14P) and a drain line (14L) are formed by O sputtering and photoetching, and the source electrode (14S) portion and the drain electrode (14L) are formed, respectively.
They are close to each other with part D). Source electrode (14S)
On the region where the drain electrode (14D) and the drain electrode (14D) are close to each other, a-Si, SiNX and Al are continuously formed through the N + a-Si layer (15N) on the source / drain region,
By etching with the same pattern, the a-Si layer (15), the gate insulating layer (16) and the gate electrode (17).
G) is laminated to form a TFT. Pixel electrode (1
4P), a gate line (17L) integrated with the gate electrode (17G) is formed in a region crossing the drain line (14L), and a-S is formed in the lower layer as in the TFT part.
It has a structure in which an i layer (15) and a gate insulating layer (16) are arranged. The N + a-Si layer (15N) is formed by CVD and photoetching, or is formed by a-Si plasma CVD of phosphorus contained in ITO forming the source / drain wiring (14) during sputtering. By reacting inside, an N + type thin film is formed at the interface.
【0013】以上のように電極が形成されたTFTアレ
イ基板の、液晶層(30)を挟んだ対向位置には透明な
基板(20)が配置され、基板(20)の内側上には、
Crのスパッタリングとフォトエッチにより、画素容量
間領域に遮光層(21)が形成され、ブラックマトリク
スとされている。遮光層(21)の更に内側上を覆う全
域には、ITOのメタルマスクスパッタリングにより、
表示画面領域の全域に共通電極(22)が形成され、遮
光層(21)と共通電極(22)の界面には、ベーキン
グによりCrが酸化されて低反射のCrOXが生成さ
れ、反射防止膜(21ox)とされている。A transparent substrate (20) is arranged at a position facing the TFT array substrate having electrodes formed as described above with a liquid crystal layer (30) interposed therebetween, and on the inner side of the substrate (20),
The light-shielding layer (21) is formed in the inter-pixel capacitance region by sputtering of Cr and photoetching to form a black matrix. By the metal mask sputtering of ITO on the entire area that covers the inner side of the light shielding layer (21),
A common electrode (22) is formed over the entire display screen area, and Cr is oxidized by baking at the interface between the light-shielding layer (21) and the common electrode (22) to generate CrOX with low reflection, and an antireflection film ( 21 ox).
【0014】ここで、Crのスパッタリングは、Crの
ターゲットを備えたチャンバ内で、圧力を0.40p
a、温度を200℃に設定した状態で、1.00kwの
直流放電により電界を形成し、Arガスを80sccm
の流量で導入することにより行われ、1500Åの厚さ
に成膜される。また、ITOのスパッタリングは、イン
ジウムとスズのターゲットを備えたチャンバ内で、表示
画面の周辺領域にメタルマスクを施し、圧力を0.75
pa、温度を200℃に設定した状態で、0.55kw
の直流放電により電界を形成し、Arガスを200sc
cm、O2ガスを2.0sccmの流量で導入すること
により行われ、1400Åの厚さに成膜される。Here, the Cr sputtering is performed in a chamber equipped with a Cr target at a pressure of 0.40 p.
a, with the temperature set to 200 ° C., an electric field is formed by a direct current discharge of 1.00 kw, and Ar gas is set to 80 sccm.
Is carried out at a flow rate of 1, and a film is formed to a thickness of 1500Å. In addition, ITO sputtering is performed in a chamber equipped with a target of indium and tin by applying a metal mask to the peripheral area of the display screen at a pressure of 0.75.
0.55 kW with pa and temperature set to 200 ° C
An electric field is formed by the direct current discharge of Ar gas at 200 sc
cm, O2 gas is introduced at a flow rate of 2.0 sccm to form a film having a thickness of 1400Å.
【0015】また、CrOXを生成するベーキングは、
Crからなる遮光層(21)のパターン上にITOの補
助容量電極(22)を被覆形成した後に、400℃、3
0分間で行われ、これにより、CrがITO中の酸素に
より酸化され、接触界面にCrOXの薄膜が形成され
る。図3に、前述の如くベーキングによりCrとITO
の界面に形成したCrOXの反射率を示し、比較例とし
て、従来通りの酸素を導入しながらCrを積層する成膜
法により形成したCrOXの反射率及びCr単層の反射
率を示した。(a)は本発明のCrOX、(b)は従来
のCrOX、(c)はCr単層について、それそれ波長
400nm〜600nmの光の反射率である。図より、
Cr単層では60%前後の反射率があり表示に悪影響が
でるが、CrOXでは、可視領域において20%以下に
抑えられ、良好な視認性が得られるのが分かる。また、
(a)と(b)を比べて、本発明によるCrOXは、従
来のCrOXよりも更に特性が安定している。これは、
熱処理によりCrとITOの界面において、ITO中の
酸素によってCrの酸化を促進する本発明の成膜法が、
酸素を導入しながらCrをスパッタリングする従来の成
膜法よりも、質の良い膜が得られることを示している。Further, the baking for producing CrOX is
After forming the ITO auxiliary capacitance electrode (22) on the pattern of the light shielding layer (21) made of Cr, the temperature is set to 400 ° C. for 3
This is performed for 0 minutes, whereby Cr is oxidized by oxygen in ITO and a thin film of CrOx is formed at the contact interface. In FIG. 3, Cr and ITO are baked by baking as described above.
The reflectance of CrOx formed at the interface of No. 2 is shown, and as a comparative example, the reflectance of CrOx formed by the conventional film forming method of stacking Cr while introducing oxygen and the reflectance of the Cr single layer are shown. (A) is the reflectance of CrOx of the present invention, (b) is the conventional CrOX, and (c) is the reflectance of light having a wavelength of 400 nm to 600 nm for the Cr single layer. From the figure,
It can be seen that the Cr single layer has a reflectance of about 60%, which adversely affects the display, but CrOx is suppressed to 20% or less in the visible region and good visibility is obtained. Also,
Comparing (a) and (b), the characteristics of CrOx according to the present invention are more stable than those of the conventional CrOX. this is,
At the interface between Cr and ITO by heat treatment, the film forming method of the present invention, which promotes oxidation of Cr by oxygen in ITO,
It is shown that a film with better quality can be obtained as compared with the conventional film forming method in which Cr is sputtered while introducing oxygen.
【0016】本発明では、図2の如く遮光層(21)の
内側にCrOXよりなる反射防止膜(21ox)を介在
させた構造により、TFTアレイ基板の側から入射する
光の反射が抑えられる。このため、特に、ノーマリ・ホ
ワイト・モードにおいて、画素容量間領域にTFTアレ
イ基板側より入射した周囲光が、ITOよりなるドレイ
ンライン(14L)から液晶層(30)を通り抜け、遮
光層(21)で反射されて同じ道筋を戻る光路が遮断さ
れるので、反射光による視認の妨害が防がれる。従っ
て、図1及び図2に示した液晶表示装置は、TFTアレ
イ基板側を表示画面に用いた構成とすることにより、視
認性の優れた、表示品位の良好な表示画面が得られる。In the present invention, as shown in FIG. 2, the structure in which the antireflection film (21ox) made of CrOx is interposed inside the light shielding layer (21) suppresses the reflection of light incident from the TFT array substrate side. Therefore, especially in the normally white mode, ambient light incident on the inter-pixel capacitance region from the TFT array substrate side passes through the liquid crystal layer (30) from the drain line (14L) made of ITO, and the light shielding layer (21). Since the optical path that is reflected by and returns to the same path is blocked, it is possible to prevent visual interference due to reflected light. Therefore, the liquid crystal display device shown in FIG. 1 and FIG. 2 has a structure in which the TFT array substrate side is used as the display screen, whereby a display screen having excellent visibility and good display quality can be obtained.
【0017】また、遮光層(21)の内側において反射
が抑えられるので、基板間で光が反射されてパネル内で
散乱されてa−Si層(15)へ入射し、リークを起こ
して電圧保持率が低下するといったことが防がれるの
で、特に、プロジェクターなどの光源強度が高い用途に
適している。そして、このような本発明の液晶表示装置
は、Crのパターニング及びITOの成膜後にベーキン
グ工程を追加するのみで製造される。即ち、CrO2を
形成するための特別なスパッタリング装置は不要である
ので、コスト的に有利である。Further, since reflection is suppressed inside the light-shielding layer (21), light is reflected between the substrates and scattered in the panel to enter the a-Si layer (15), causing leakage and holding voltage. Since it is possible to prevent the rate from being lowered, it is particularly suitable for applications such as a projector having a high light source intensity. Then, such a liquid crystal display device of the present invention is manufactured only by adding a baking step after patterning Cr and forming an ITO film. That is, a special sputtering device for forming CrO2 is unnecessary, which is advantageous in terms of cost.
【0018】次に、本発明の第2の実施例を説明する。
平面構造は図1で示した第1の実施例と同じであり、本
実施例では図1のA−A線に沿った断面構造は図4のよ
うになっている。以下、第1の実施例と重複する説明は
割愛しながら、要点及び相違点を述べる。ガラスなどの
基板(10)上には、第1の実施例と同様、Crからな
る遮光層(11)と補助容量電極(12)が形成され、
これらの上には層間絶縁層(13)が被覆されている。
層間絶縁層(13)上には、ITOにより画素電極(1
4P)、ドレインライン(14L)、ソース電極(14
S)及びドレイン電極(14D)が形成されている。ド
レインライン(14L)に交差する方向には、下層にa
−Si層(15)とゲート絶縁層(16)を配したゲー
トライン(17L)が形成され、一部がソース電極(1
4S)及びドレイン電極(14D)上に乗せられ、それ
ぞれN+a−Si(15N)を介した上に、a−Si
(15)、ゲート絶縁層(16)及びゲート電極(17
G)が積層されてTFTを構成している。Next, a second embodiment of the present invention will be described.
The planar structure is the same as that of the first embodiment shown in FIG. 1. In this embodiment, the sectional structure taken along the line AA of FIG. 1 is as shown in FIG. Hereinafter, the main points and differences will be described while omitting the description overlapping with that of the first embodiment. On the substrate (10) such as glass, the light shielding layer (11) made of Cr and the auxiliary capacitance electrode (12) are formed as in the first embodiment.
An interlayer insulating layer (13) is coated on these.
On the interlayer insulating layer (13), the pixel electrode (1
4P), drain line (14L), source electrode (14P)
S) and the drain electrode (14D) are formed. In the direction intersecting the drain line (14L), a
A gate line (17L) including the -Si layer (15) and the gate insulating layer (16) is formed, and a part of the gate line (17L) is formed.
4S) and the drain electrode (14D), respectively, via N + a-Si (15N) and a-Si.
(15), gate insulating layer (16) and gate electrode (17
G) is laminated to form a TFT.
【0019】一方、液晶層(30)を挟んだ対向位置に
は基板(20)が配置され、基板(20)の内側上に
は、先に、ITOからなる共通電極(22)が形成され
ており、共通電極(22)の更に内側上に、Crからな
る遮光層(21)が形成されてブラックマトリクスとな
っている。共通電極(22)と遮光層(21)との界面
には、前述の如く、ベーキングによりCrが酸化されて
低反射のCrOXが生成され、反射防止膜(21ox)
とされている。On the other hand, the substrate (20) is arranged at opposite positions with the liquid crystal layer (30) interposed therebetween, and the common electrode (22) made of ITO is first formed on the inner side of the substrate (20). The light shielding layer (21) made of Cr is formed on the inner side of the common electrode (22) to form a black matrix. At the interface between the common electrode (22) and the light-shielding layer (21), Cr is oxidized by baking and low-reflecting CrOx is generated as described above, and the antireflection film (21ox) is formed.
It has been.
【0020】本実施例では、ブラックマトリクスの外側
に反射防止膜(21ox)が形成されているので、対向
基板側からの光の反射が全て抑えられる。このため、周
囲光が反射されて視認を妨害するといったことがなくな
るので、この構造は、対向基板側を表示画面に用いた直
視型の用途に適している。In this embodiment, since the antireflection film (21ox) is formed on the outer side of the black matrix, all the reflection of light from the counter substrate side can be suppressed. For this reason, the ambient light is not reflected and hinders visual recognition. Therefore, this structure is suitable for a direct-view type application in which the counter substrate side is used as a display screen.
【0021】[0021]
【発明の効果】以上の説明から明らかな如く、本発明に
より、対向基板側でブラックマトリクスを構成する遮光
層と液晶駆動用の共通電極の接触界面に、遮光層の表面
酸化膜を形成することで光の反射が抑えられた。酸化膜
を遮光層の液晶層側に形成した場合は、基板間内での光
の反射が防がれて光リーク電流が抑えられので、プロジ
ェクターなどの強光源の用途に適した液晶表示装置とで
きる。一方、酸化膜を遮光層の基板側に形成した場合
は、対向基板側からの光の反射が抑えられるので、対向
基板側を表示画面に用いることにより、周囲光の反射の
無い、視認性の優れた液晶表示装置となる。また、この
ような酸化膜は、加熱処理の工程を追加するのみで遮光
層と共通電極の接触界面に選択的に形成されるので、製
造コストの増大が避けられる。As is apparent from the above description, according to the present invention, the surface oxide film of the light shielding layer is formed at the contact interface between the light shielding layer forming the black matrix on the counter substrate side and the common electrode for driving the liquid crystal. The reflection of light was suppressed by. When the oxide film is formed on the liquid crystal layer side of the light shielding layer, the light reflection between the substrates is prevented and the light leak current is suppressed, so that the liquid crystal display device is suitable for the use of a strong light source such as a projector. it can. On the other hand, when the oxide film is formed on the substrate side of the light shielding layer, reflection of light from the counter substrate side can be suppressed. Therefore, by using the counter substrate side for the display screen, there is no reflection of ambient light and visibility is improved. It becomes an excellent liquid crystal display device. Further, since such an oxide film is selectively formed at the contact interface between the light shielding layer and the common electrode only by adding a heat treatment step, an increase in manufacturing cost can be avoided.
【図1】本発明の実施例に係る液晶表示装置の単位画素
の平面図である。FIG. 1 is a plan view of a unit pixel of a liquid crystal display device according to an exemplary embodiment of the present invention.
【図2】本発明の第1の実施例に係る液晶表示装置の単
位画素の断面図である。FIG. 2 is a cross-sectional view of a unit pixel of the liquid crystal display device according to the first embodiment of the present invention.
【図3】本発明の作用効果を説明する特性図である。FIG. 3 is a characteristic diagram illustrating the function and effect of the present invention.
【図4】本発明の第2の実施例に係る液晶表示装置の単
位画素の断面図である。FIG. 4 is a cross-sectional view of a unit pixel of a liquid crystal display device according to a second embodiment of the present invention.
【図5】従来の液晶表示装置の単位画素の平面図であ
る。FIG. 5 is a plan view of a unit pixel of a conventional liquid crystal display device.
【図6】従来の液晶表示装置の単位画素の断面図であ
る。FIG. 6 is a cross-sectional view of a unit pixel of a conventional liquid crystal display device.
10,20 基板 11,21 遮光層 12 補助容量電極 13 層間絶縁層 14 ソース・ドレイン配線 15 a−Si 16 ゲート絶縁層 17 ゲート配線 22 共通電極 30 液晶層 10, 20 Substrate 11, 21 Light-shielding layer 12 Auxiliary capacitance electrode 13 Interlayer insulating layer 14 Source / drain wiring 15 a-Si 16 Gate insulating layer 17 Gate wiring 22 Common electrode 30 Liquid crystal layer
Claims (2)
対の基板の対向面の一方に形成され液晶駆動用の画素容
量の一方を成す複数の画素電極と、該各画素電極に接続
された薄膜トランジスタと、前記対向面の他方に全面的
に形成され前記各画素電極により規格され複数の前記画
素容量の他方を一体的に成す共通電極と、前記画素容量
の領域間に形成された遮光層を有する液晶表示装置にお
いて、 前記遮光層は前記共通電極と同一の前記基板上に形成さ
れ、前記遮光層と前記共通電極の接触界面には、前記遮
光層の表面が酸化された膜が形成されていることを特徴
とする液晶表示装置。1. A plurality of pixel electrodes, which are formed on one of opposing surfaces of a pair of substrates in which liquid crystal is hermetically bonded and are formed inside, and which constitute one of pixel capacitances for driving liquid crystal, and are connected to the respective pixel electrodes. A thin film transistor, a common electrode that is formed entirely on the other of the facing surfaces and integrally forms the other of the plurality of pixel capacitors standardized by the pixel electrodes, and a light shielding layer formed between the regions of the pixel capacitor. In the liquid crystal display device, the light shielding layer is formed on the same substrate as the common electrode, and a film in which a surface of the light shielding layer is oxidized is formed at a contact interface between the light shielding layer and the common electrode. A liquid crystal display device characterized in that
物合金により形成され、前記遮光層はCrにより形成さ
れ、かつ、前記遮光層の表面が酸化された膜は、加熱処
理により形成されたCrの酸化膜であることを特徴とす
る請求項1記載の液晶表示装置。2. The common electrode is formed of an oxide alloy of indium and tin, the light shielding layer is formed of Cr, and the film in which the surface of the light shielding layer is oxidized is formed by heat treatment. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is an oxide film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30655594A JPH08160409A (en) | 1994-12-09 | 1994-12-09 | Liquid crystal display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30655594A JPH08160409A (en) | 1994-12-09 | 1994-12-09 | Liquid crystal display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08160409A true JPH08160409A (en) | 1996-06-21 |
Family
ID=17958464
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30655594A Pending JPH08160409A (en) | 1994-12-09 | 1994-12-09 | Liquid crystal display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08160409A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998016868A1 (en) * | 1996-10-16 | 1998-04-23 | Seiko Epson Corporation | Liquid crystal device substrate, liquid crystal device, and projection display |
JP2009047822A (en) * | 2007-08-17 | 2009-03-05 | Epson Imaging Devices Corp | Liquid crystal display device and electronic device |
JP2010256655A (en) * | 2009-04-27 | 2010-11-11 | Seiko Epson Corp | Electro-optical device and electronic apparatus |
WO2013031171A1 (en) * | 2011-09-01 | 2013-03-07 | シャープ株式会社 | Display device and production method for same |
CN103165626A (en) * | 2011-12-12 | 2013-06-19 | 松下液晶显示器株式会社 | Display panel and display device |
-
1994
- 1994-12-09 JP JP30655594A patent/JPH08160409A/en active Pending
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998016868A1 (en) * | 1996-10-16 | 1998-04-23 | Seiko Epson Corporation | Liquid crystal device substrate, liquid crystal device, and projection display |
US6297862B1 (en) | 1996-10-16 | 2001-10-02 | Seiko Epson Corporation | Light shielding structure of a substrate for a liquid crystal device, liquid crystal device and projection type display device |
US6388721B1 (en) | 1996-10-16 | 2002-05-14 | Seiko Epson Corporation | Light shielding structure of a substrate for a liquid crystal device, liquid crystal device and projection type display device |
US6573955B2 (en) | 1996-10-16 | 2003-06-03 | Seiko Epson Corporation | Capacitance substrate for a liquid crystal device and a projection type display device |
KR100516558B1 (en) * | 1996-10-16 | 2005-12-26 | 세이코 엡슨 가부시키가이샤 | Liquid crystal device substrate, liquid crystal device and projection display device |
CN1294451C (en) * | 1996-10-16 | 2007-01-10 | 精工爱普生株式会社 | Base plate for liquid crystal apparatus, liquid crystal apparatus and projecting display device |
CN100520543C (en) * | 1996-10-16 | 2009-07-29 | 精工爱普生株式会社 | Light shielding structure of a substrate for a liquid crystal device, liquid crystal device and projection type display device |
JP2009047822A (en) * | 2007-08-17 | 2009-03-05 | Epson Imaging Devices Corp | Liquid crystal display device and electronic device |
JP2010256655A (en) * | 2009-04-27 | 2010-11-11 | Seiko Epson Corp | Electro-optical device and electronic apparatus |
WO2013031171A1 (en) * | 2011-09-01 | 2013-03-07 | シャープ株式会社 | Display device and production method for same |
CN103165626A (en) * | 2011-12-12 | 2013-06-19 | 松下液晶显示器株式会社 | Display panel and display device |
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