JPH08153749A - Semiconductor package - Google Patents

Abstract

PURPOSE: To obtain a small sized semiconductor package which enables a multi- terminal connection by reducing the pitch between leads and is excellent in heat radiation and electric characteristics at low cost by serving a lead wiring on a tape carrier also for external leads. CONSTITUTION: A semiconductor chip 1 is supported on a tap carrier 2 such as insulative resin film and electrically connected to an inside end 3a of a lead wiring previously formed on the carrier 2. The lead wiring 3 is composed of Cu leads and hence can be etched finely, allowing the chip 1 to be easily connected to the wiring 3 in the form of a narrow pitched multi-terminal. The chip 1 is bonded to a chip mount 4a formed on the back of an Al nitride substrate 4 through a bonding material 5. The outside end 3b of the wiring 3 is protruded up to the outside of the substrate 4 and hence functions as external leads.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor package.

[0002]

2. Description of the Related Art Generally, a plastic package, a metal package, or a ceramic package is used for packaging a semiconductor chip. As the structure, a DIP (dual in-line package) using a lead frame, a QFP (quad flood package), a PGA (pin grid array) using lead pins, and a BGA (ball) using solder bumps as input / output terminals. Grid array) and the like are known.

Of these package structures, a package using a lead frame is widely used for various semiconductor chips because of its simple structure and low cost. In particular, the QFP is widely used because it can cope with an increase in the number of input / output signals to some extent and is a surface mount type.

By the way, recently, due to the rapid progress of semiconductor manufacturing technology, high integration of semiconductor chips has been rapidly advanced, and the number of input / output signals per chip has been increasing steadily. Therefore, with respect to a package in which such a highly integrated semiconductor chip is mounted, it is required to enable connection with the semiconductor chip at multiple terminals and at a narrow pitch.

However, in the conventional QFP, the lead frame used therefor is 42 wt% Ni-Fe or 29 wt% Ni-16.
Since it is manufactured by etching a Fe-Ni alloy thin plate such as wt% Co-Fe, the lead pitch limit is 100 μm.
However, there is a problem in that the pitch cannot be further narrowed and the number of terminals cannot be increased. In addition, when the number of terminals is increased by the lead pitch as described above, the package itself naturally becomes large, which violates the demand for miniaturization of various electronic devices. Furthermore, since the wiring length in the package becomes long, a signal delay or the like is also caused. The lead frame made of the Fe-Ni alloy mentioned above is
It also has a problem in electrical characteristics. In particular, when handling a high-speed signal, the voltage level of the output signal decreases and the noise level increases.

On the other hand, as a method of mounting a semiconductor chip having a large number of inputs and outputs on a package, there is known a method of bonding the semiconductor chip to a tape carrier so-called TAB (tape automated bonding) tape and mounting the TAB chip on the package. ing. However, a package using a conventional TAB chip has a structure in which a connecting pad connected to an input / output pin or the like which is an external connecting terminal through an internal wiring and a lead wiring provided on a tape carrier are connected. Therefore, there is a drawback that it is structurally expensive.

Also, an inexpensive package in which the TAB chip itself is resin-sealed is known, but in this case, the heat radiation performance is remarkably deteriorated, and the highly integrated semiconductor chip as described above cannot be coped with at all. . Furthermore, in the package using the TAB chip, bending or distortion of the lead wiring,
In order to prevent so-called lead skew, a structure has been proposed in which a metal plate is bonded to the TAB tape portion (see Japanese Patent Laid-Open No. 6-69275). However, this structure does not improve heat dissipation, and there is a risk that the lead wiring and the metal plate may be short-circuited. In addition, since the metal plate is used, external noise is picked up by the so-called antenna effect, which causes malfunction. Further, there are various problems such as rust of the metal plate and occurrence of warpage due to low rigidity.

[0008]

As described above, in the package using the lead frame such as the conventional QFP, there is a limitation in the lead pitch, and there is a problem that the pitch cannot be narrowed and the number of terminals cannot be increased. there were. On the other hand, a package using TAB, which is known as a method of mounting a semiconductor chip having a large number of inputs and outputs, has the problems of structurally high cost, low heat dissipation, short circuit and malfunction. Had.

As described above, in the conventional semiconductor package, the lead pitch can be narrowed to enable multi-terminal connection, the structure can be simplified to reduce the cost, and the heat dissipation can be improved. It was a challenge to improve the.

The present invention has been made in order to solve such a problem, and enables a multi-terminal connection by narrowing the pitch between leads, and is an inexpensive semiconductor package excellent in heat dissipation, and further, a small size. The object is to provide a semiconductor package having excellent electrical characteristics.

[0011]

A first semiconductor package according to the present invention, as set forth in claim 1, is a tape carrier having a lead wire, and is electrically supported by the tape carrier and supported by the tape carrier. A semiconductor chip connected to the tape carrier and an aluminum nitride substrate to which the semiconductor chip is bonded together with the tape carrier, and the lead wiring provided on the tape carrier also serves as an external lead.

The second semiconductor package according to the present invention has a tape carrier having lead wires and is supported by the tape carrier.
And a semiconductor chip electrically connected to one end of the lead wiring, and a lead frame serving as an external lead, and an aluminum nitride substrate to which the semiconductor chip is bonded. The other end of the formed lead wiring is electrically connected to the lead frame.

In the first semiconductor package, a semiconductor chip so-called TAB chip supported by a tape carrier having a lead wire is joined to an aluminum nitride substrate, and the lead wire provided on the tape carrier is used as an external lead. ing. The second semiconductor package is a semiconductor chip supported by a tape carrier having a lead wire, a so-called TAB chip, which is bonded to an aluminum nitride substrate and also serves as an external lead which is bonded in advance to the outer peripheral side of the aluminum nitride substrate. The lead frame and the semiconductor chip are electrically connected by the lead wiring provided on the tape carrier.

The lead wiring used for the TAB chip is
Since fine etching is possible, it is possible to connect the semiconductor chip and the lead wiring with multiple terminals and at a narrow pitch. Further, since the semiconductor chip itself is bonded to the aluminum nitride substrate, heat from the semiconductor chip can be efficiently dissipated, and high heat dissipation of the semiconductor package can be secured. In addition, since an aluminum nitride substrate having an insulating property is used, there is no risk of short circuit between the lead wiring and the ground surface, and there is no disturbance due to external noise.

Further, the package structure is simple,
Further, since the rigidity is high, it is possible to improve the reliability of the package and reduce the manufacturing cost of the package. In particular, the first semiconductor package can effectively reduce the size of the package and further improve reliability when reducing the size of the package.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments for carrying out the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing the structure of a semiconductor package according to an embodiment of the present invention. In the figure, 1
Is a semiconductor chip, and this semiconductor chip 1 is a so-called TAB chip. That is, the semiconductor chip 1 is a tape carrier (TAB tape) such as an insulating resin film.
The tape carrier 2 is electrically connected to the inner end 3a of the lead wire 3 which is provided in advance on the tape carrier 2. The connection between the semiconductor chip 1 and the lead wiring 3 is made by bumps (not shown) as in a normal TAB chip.
Is done by.

Here, the lead wiring 3 is a normal TA.
It is a copper-based lead made of copper or a copper alloy used for B tape. Therefore, it can be extremely finely etched like a normal TAB chip. Specifically, 0.
A lead pitch of about 05 to 0.5 mm can be realized. By using such lead wiring 3, it becomes possible to easily connect the semiconductor chip 1 and the lead wiring 3 with multiple terminals and at a narrow pitch.

In the semiconductor chip 1 as described above, a brazing material, a solder, a glass-based adhesive agent, etc. are mounted on the chip mounting portion (metallized portion) 4a provided on the rear surface side of the single plate-shaped aluminum nitride substrate 4 on the rear surface. Are joined via the joining material 5. The tape carrier 2 portion is joined and fixed to the outer peripheral portion of the aluminum nitride substrate 4 via an insulating adhesive 6.

The outer shape of the lead wiring 3 is set in advance to be larger than the outer shape of the aluminum nitride substrate 4. Since the outer end 3b of the lead wiring 3 projects to the outside of the aluminum nitride substrate 4, the outer end 3b of the lead wiring 3 functions as an external lead (outer lead). That is, the lead wiring 3 provided on the tape carrier 2 has both the functions of an inner lead (internal lead) and an outer lead. The outer end 3b of the lead wiring 3 is connected to a wiring layer on the side of a mounting board such as a printed board.

The semiconductor chip 1 is sealed with a potting resin 7 or the like and protected by this.

In the semiconductor package having the above-mentioned structure, the lead wiring 3 provided on the tape carrier (TAB tape) 2 and capable of narrowing the lead pitch is used as a lead similar to the lead frame of the conventional QFP. Therefore, it is possible to easily cope with the increase in the number of terminals of the semiconductor chip 1.

That is, the semiconductor chip 1 and the leads can be easily connected to each other with a large number of terminals and at a narrow pitch. Further, the lead wiring 3 electrically connected to the semiconductor chip 1
Since it is used as an outer lead as it is, the conventional connection by wire bonding or the like can be omitted.

Furthermore, since the semiconductor chip 1 to the mounting board such as a printed circuit board can be directly connected by the lead wiring 3 made of copper or copper alloy, the electrical characteristics can be improved. 2, 3 and 4
The electrical characteristics (shown by the solid line) of the semiconductor package of this embodiment are shown in comparison with the semiconductor package of the conventional QFP structure (lead frame material: 42 wt% Ni-Fe) (shown by the broken line). It can be seen that the semiconductor package of the present invention is superior in any of inductance, capacitance, and resistance. Further, since the semiconductor chip 1 and the lead wiring 3 are bonded to the aluminum nitride substrate 4 having an insulating property, there is no risk of short-circuiting the lead wiring 3 and the ground surface, and there is a possibility of being disturbed by external noise. Absent. Regarding the heat dissipation of the semiconductor package,
Since the semiconductor chip 1 is bonded to the aluminum nitride substrate 4 having high heat dissipation, it is possible to secure good heat dissipation. FIG. 5 shows the thermal resistance (shown by a solid line) of the semiconductor package of this embodiment in comparison with a conventional package (Metal-TCP) having a structure in which a metal plate is bonded to a TAB tape portion (shown by a broken line). From FIG. 5, it can be seen that the semiconductor package of the present invention has low thermal resistance and excellent heat dissipation.

Further, as described above, since the lead wiring 3 capable of a narrow pitch is used and the lead structure is simplified, the package structure itself is extremely simple and
The package shape (outer shape) can be easily reduced.
The single plate-shaped aluminum nitride substrate 4 is particularly effective for simplifying the package structure. Further, these can reduce the manufacturing cost. FIG. 6 compares the outer shape (indicated by a solid line) with respect to the number of leads of the semiconductor package (lead pitch: 0.25 mm) of this embodiment with a conventional semiconductor package having a QFP structure (lead pitch: 0.5 mm) (indicated by a broken line). And show it. As is clear from FIG. 6, the semiconductor package of the present invention is effective for miniaturization.

In the above-described embodiments, the so-called face-down type package structure in which the semiconductor chip 1 is bonded to the back surface side of the aluminum nitride substrate 4 has been described, but the semiconductor package of the present invention is not limited to this. . For example, as shown in FIG. 7, the semiconductor package of the present invention can be applied to a so-called face-up type package structure in which the semiconductor chip 1 is bonded to the surface side of the aluminum nitride substrate 4. The basic structure at this time is similar to the face-down type package structure, and similar effects can be obtained.

Further, as shown in FIGS. 8 and 9, it is possible to use an aluminum nitride substrate 8 having a cavity 8a. Even when the cavity type aluminum nitride substrate 8 is used, the basic structure is the same as that of the package structure shown in FIG. 1, and the same effect can be obtained. 8 and 9, the same parts as those in FIG. 1 are designated by the same reference numerals.

Next, another embodiment of the present invention will be described with reference to FIG.

In the semiconductor package shown in FIG.
The semiconductor chip 11 is a TAB chip supported by a tape carrier such as an insulating resin film as in the above-described embodiment. The semiconductor chip 11 is electrically connected to the inner end portion 12a of the lead wiring 12 provided in advance on the tape carrier by a bump (not shown). Therefore, similarly to the above-described embodiment, the lead wiring 12 made of a copper-based lead and the semiconductor chip 11 can be connected with multiple terminals and at a narrow pitch.

The semiconductor chip 11 has a back surface on a chip mounting portion (metallized portion) 13a provided on the front surface side of a single plate-shaped aluminum nitride substrate 13, and a bonding material 14 such as a brazing material, solder, or a glass-based adhesive. Are joined through. In addition, a lead frame 15 serving as an outer lead is previously bonded and fixed to the outer peripheral side of the aluminum nitride substrate 13 via an insulating bonding agent 16 such as a resin-based bonding agent or a glass-based bonding agent. It is also possible to use a metal-based bonding agent by subjecting the outer surface of the lead frame 15 to an insulation treatment such as a surface oxidation treatment in advance.

The lead frame 15 can be made of Fe-Ni alloy, but copper or copper alloy similar to the lead wiring 12 is preferably used. This allows
The electrical characteristics can be improved. In this case, the lead frame 15 may be bonded to the aluminum nitride substrate 13 using a resin-based bonding agent.

The other end portion (outer end portion) 12b of the lead wiring 12 is shaped according to the pitch of the lead frame 15. The outer end 12b of the lead wire 12 is an inner end 15a of the lead frame 15.
Is electrically connected to. That is, the semiconductor chip 1
1 and the lead frame 15 are electrically connected by a lead wire 12 provided on the tape carrier, and the lead wire 12 functions as an inner lead.

The semiconductor chip 11 may be hermetically sealed with a lid as in the conventional QFP, or may be resin-sealed with a potting resin or the like as in the above-described embodiments.

In the semiconductor package having the above-described structure, the finely-etchable lead wiring 12 provided on the tape carrier (TAB tape) is used as an inner lead between the semiconductor chip 11 and the lead frame 15. Therefore, it is possible to easily cope with the increase in the number of terminals of the semiconductor chip 11. That is, it becomes possible to easily connect the semiconductor chip 11 and the lead frame 12 with multiple terminals and at a narrow pitch.

The basic structure of the package is the conventional Q
Like the FP, it has a structure using a lead frame, and since the aluminum nitride substrate 13 that secures heat dissipation is a single plate, it has a multi-layered package using a conventional TAB chip (for example, pins as input / output terminals. Manufacturing cost can be reduced as compared with the case of using (). Regarding the heat dissipation of the semiconductor package, the aluminum nitride substrate 4 can secure good heat dissipation as described above. Further, since the lead frame 15 is used as the outer lead, it is possible to suppress an increase in wiring resistance due to the thin lead wiring (TAB lead) 12.

[0036]

As described above, according to the present invention, it is possible to provide a multi-terminal connection by narrowing the pitch between leads, and to provide a semiconductor package which is inexpensive and has excellent heat dissipation. Further, according to the first semiconductor package, it is possible to further reduce the size of the package and improve the electrical characteristics. Further, according to the second semiconductor package, it is possible to suppress an increase in wiring resistance and the like.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a structure of a semiconductor package according to an embodiment of the present invention.

FIG. 2 is a diagram showing the relationship between the external shape and the inductance of the semiconductor package shown in FIG. 1 in comparison with a conventional QFP package.

3 is a diagram showing the relationship between the external shape and capacitance of the semiconductor package shown in FIG. 1 in comparison with a conventional QFP package.

FIG. 4 is a diagram showing the relationship between the outer shape and the resistance of the semiconductor package shown in FIG. 1 in comparison with a conventional QFP package.

5 is a diagram showing the thermal resistance of the semiconductor package shown in FIG. 1 in comparison with a conventional TAB package.

6 is a diagram showing the relationship between the number of leads and the outer shape of the semiconductor package shown in FIG. 1 in comparison with a conventional QFP package.

7 is a sectional view showing a modification of the semiconductor package shown in FIG.

8 is a sectional view showing another modification of the semiconductor package shown in FIG.

9 is a sectional view showing still another modification of the semiconductor package shown in FIG.

FIG. 10 is a sectional view schematically showing a structure of a semiconductor package according to another embodiment of the present invention.

[Explanation of symbols]

 1, 11 ... Semiconductor chip (TAB chip) 2 ... Tape carrier (TAB tape) 3, 12 ... Lead wiring (TAB lead) 4, 13 ... Aluminum nitride substrate 15 ... Lead frame

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hiroki Asai 4 shares 2-4 Suehiro-cho, Tsurumi-ku, Yokohama-shi, Kanagawa Toshiba Keihama office (72) Inventor Shun Monma 4 shares 2-2, Suehiro-cho, Tsurumi-ku, Yokohama-shi, Kanagawa Company Toshiba Keihin Office (72) Inventor Koji Yamakawa 2-4 shares of Suehiro-cho, Tsurumi-ku, Yokohama-shi, Kanagawa Prefecture (72) Inventor Mitsuyoshi Endo 1 Komukai-Toshiba-cho, Kawasaki-shi, Kanagawa 1-share company (72) Inventor Hirohisa Oshiguchi 7-1 Nisshin-cho, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Electronics Engineering Co., Ltd.

Claims (6)

[Claims] 1. A tape carrier having lead wires,
The lead provided on the tape carrier, comprising a semiconductor chip supported by the tape carrier and electrically connected to the lead wiring, and an aluminum nitride substrate on which the semiconductor chip is joined together with the tape carrier. A semiconductor package in which the wiring doubles as an external lead. 2. The semiconductor package according to claim 1, wherein the lead wiring has a copper lead. 3. The semiconductor package according to claim 1, wherein the outer end portion of the lead wire projects outside the aluminum nitride substrate. 4. A tape carrier having lead wires,
A semiconductor chip supported by the tape carrier and electrically connected to one end of the lead wiring, and a lead frame serving as an external lead, and an aluminum nitride substrate to which the semiconductor chip is bonded are provided. A semiconductor package, wherein the other end of the lead wire provided on the tape carrier and the lead frame are electrically connected. 5. The semiconductor package according to claim 4, wherein the lead wiring has a copper lead. 6. The semiconductor package according to claim 4, wherein the lead frame has a copper lead.