JPH08153747A - Semiconductor chip and semiconductor device using the chip - Google Patents

Abstract

PURPOSE: To avoid degrading of reliability on the electric connection between a semiconductor chip and substrate by providing circuit connecting pads formed near the chip corners when the chip is used for a semiconductor device having a one-side resin sealed package structure. CONSTITUTION: Connection-reinforcing pads 2c formed at the corners of an element-pad forming face of a semiconductor chip and circuit connecting pads 2b are formed on pad forming regions on the element-pad forming face, except its corners, and electrically connected to an integrated circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip and a semiconductor device using the same, and more particularly to a semiconductor device having a single-sided resin-sealed package structure and a semiconductor chip used therein.

[0002]

2. Description of the Related Art For semiconductor devices used in, for example, integrated circuit cards, mask ROM cards for games, small mobile phones, etc., there is a strong demand for miniaturization and thinning of packages. In order to meet such demands, mounting technology of bare semiconductor chips (bare chips) has been developed,
Chip-on-board (COB) mounting, flip-chip mounting, etc. are known.

In the flip chip mounting, the metal bump electrodes on the element forming surface of the bare chip are pressed against the electrode pads formed on one main surface of the wiring board to connect (flip chip bonding). This has a higher mounting density than the COB mounting which requires wire bonding, but has a problem that stress due to thermal expansion of the substrate is applied to the connecting portion between the substrate and the chip to impair the reliability of the connection.

As an improved example of the flip chip mounting,
A single-sided resin-sealed package structure in which a resin is interposed between a bare chip and a substrate to mechanically fix the substrate and the chip together is known, for example, from Japanese Patent Publication No. 2-7180.

Further, as an improved example of the single-sided resin-encapsulated package structure and a manufacturing method thereof, Japanese Patent Application Nos. Hei 6-32296 and Hei 6-5075, filed by the applicant of the present application, are disclosed.
Various proposals have been made in Japanese Patent No. 7 and Japanese Patent Application No. 6-60493.

[0006] FIG. 5 is a Japanese Patent Application No. 6-507 related to the above proposal.
57 shows an example of a single-sided resin-sealed package structure disclosed in No. 57. This package structure has a wiring board 1 having a wiring 1a including a connected portion (for example, a connection pad 1b) on one main surface, a semiconductor chip 2 mounted face down on the one main surface of the board, and the chip described above. And a wiring layer, and a resin layer 5 filled between the wiring board and the wiring board, and an external connection terminal 4 which is led out and exposed on the other main surface side of the board and electrically connected to the chip. In FIG. 5, 2a is a bump electrode, 3 is a through-hole wiring, and the exposed upper surface of the chip 2 is made of a dense and robust material (for example, silicon) and is reliable without resin sealing. There are few sexual problems.

FIG. 6 shows a Japanese Patent Application No. 6-604 relating to the above proposal.
An example of a single-sided resin-sealed package structure disclosed in No. 93 is shown. This package structure is an improved example of the package structure shown in FIG. 5, and the wiring 1a is formed by embedding so as to form substantially the same plane (planarity is about ± 10 μm) with respect to one main surface of the substrate 1. . Note that FIG.
5, the same parts as those in FIG. 5 are designated by the same reference numerals.

According to this package structure, when the resin is poured between the chip and the substrate by utilizing the capillary phenomenon,
The flatness between the chip and substrate is good, and the resin easily flows in, so a dense resin layer without voids can be formed.
The reliability of fixation between substrates can be improved.

In addition, since the semiconductor device having the package structure according to the above proposal can be subjected to the burn-in test for applying the temperature stress and / or the electric field stress after the resin sealing, the resin sealing is not performed. Better than flip chip mounting.

FIG. 7 shows an example of an element / pad formation surface of a semiconductor chip used in a conventional resin-sealed semiconductor device. On the element / pad formation surface of this chip 70,
The pad 71 is provided in the pad formation region other than the corner portion, that is, the pad 71 is not provided in the corner portion, or even if the pad is provided,
It is a pad for a test pattern such as TEG (Test Element Group).

By the way, the semiconductor chip 7 as described above is used.
0 is used for a semiconductor device having a single-sided resin-encapsulated package structure as described above, and a conductive material (for example, bump electrode made of metal) formed on the pad 71 of the chip and a flat surface formed on the wiring board. Consider the case where the mold connection pad is fixed and electrically connected. in this case,
In a semiconductor device having such a structure, there are no pads at the chip corners where thermal stress is most concentrated due to thermal cycles, etc., so that the circuit connection pads 71 provided near the chip corners are stressed. Accordingly, the electrical connection between the pad portion and the wiring substrate may be impaired, and the reliability of the electrical connection between the chip and the substrate may be reduced.

[0012]

As described above, the conventional semiconductor device having the single-sided resin-sealed package structure and the semiconductor chip used in the semiconductor device have a circuit connecting pad portion provided in the vicinity of a chip corner. However, there is a problem that the reliability of electrical connection between the chip and the substrate is deteriorated.

The present invention has been made to solve the above problems, and when used in a semiconductor device having a single-sided resin-sealed package structure, a circuit connection pad portion provided in the vicinity of a chip corner. It is an object of the present invention to provide a semiconductor chip capable of preventing a decrease in reliability of electrical connection between a chip and a substrate in the above and a semiconductor device using the same.

[0014]

A semiconductor chip according to the present invention comprises a connection reinforcing pad formed at each corner of an element / pad formation surface and a pad formation region other than each corner of the element / pad formation surface. And a circuit connection pad electrically connected to the integrated circuit.

The connection reinforcing pad is a dummy pad that is not electrically connected to an integrated circuit including the element, or a power supply to which a power supply potential or a ground potential of the integrated circuit including the element is applied. Pad for
It may be formed in a corner peripheral portion including each of the corner portions.

Further, the semiconductor device of the present invention has the semiconductor chip and a wiring including a connected portion on one main surface, the semiconductor chip is mounted face down on the one main surface, and the connected portion A pad of the semiconductor chip is fixed to the portion in a state of being electrically connected via a bump electrode, and a wiring board having an external connection terminal that is derived / exposed from the connected portion to the other main surface side, It is characterized by comprising a resin layer filled and cured between the semiconductor chip and the wiring board.

[0017]

In the semiconductor chip of the present invention, the connection reinforcing pad is formed at each corner of the element / pad formation surface. The semiconductor device of the present invention has a single-sided resin-sealed package structure using the semiconductor chip.

According to such a semiconductor chip and a semiconductor device using the same, since the connection reinforcing pad exists in the chip corner portion where the thermal stress is most concentrated due to the thermal cycle, it is provided in the vicinity of the chip corner. The circuit connection pads provided are less susceptible to stress.

Therefore, the electrical connection between the circuit connecting pad portion and the wiring substrate is not impaired, the reliability of the connection between the chip and the substrate is prevented from decreasing, and the reliability and yield of the semiconductor device are improved. Cost reduction is possible.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1A schematically shows an example of an element / pad formation surface of a semiconductor chip used in a semiconductor device having a single-sided resin-sealed package structure according to an embodiment of the present invention.

FIG. 1B schematically shows an example of one main surface of a wiring board on which the chip of FIG. 1A is flip-chip bonded. 2A and 2B are a perspective view and a cross-sectional view showing an example of a semiconductor device having a single-sided resin-sealed package structure using the chip of FIG. 1A and the substrate of FIG. 1B. is there.

The semiconductor chip shown in FIG. 1A has connection reinforcing pads 2c (in this example, it is not electrically connected to the integrated circuit including the element) at each corner of the element / pad formation surface. Dummy pad) is formed,
Circuit-connecting pads 2b electrically connected to the integrated circuit are formed in the pad-forming regions other than the corners of the element / pad-forming surface. In this case, in this example, the dummy pad 2c is formed with the same size as the circuit connecting pad 2b.

As shown in FIG. 2B, the semiconductor chip has a conductive material for flip-chip bonding on each pad portion 2c, 2b on the element forming surface of the chip 2. For example, bump electrodes 2a made of metal (for example, diameter 100 μm, height 30 μm) 2a are formed. The bump electrodes 2a are, for example, gold bumps formed by electroplating or gold ball bumps formed by ball bonding.

The substrate 1 shown in FIG. 1B has a wiring 1a including a connected portion (connection pad) 1b on one main surface, and a connection reinforcing pad 1c is provided at each corner of the one main surface. Has been formed. When forming the connected portion 1b on the substrate 1, the substrate 1 is fixed on, for example, a stage of a screen printing machine having a vacuum suction mechanism, and the portion on the substrate 1 corresponding to the metal bump electrode 2a of the chip is fixed. A conductive paste, for example, a silver paste (silver particle size: 1 μm, viscosity: 100 ps) is screen-printed to produce a flat-type connection pad (for example, diameter 15).
0 μm, height 80 μm) 1b is formed.

Further, as shown in FIG. 2B, the substrate 1 has external connection terminals which are led out and exposed from the connected portion 1b to the other main surface side through, for example, the through-hole wiring 3. Have 4.

In this example, the wiring 1a of the substrate 1 and the external connection terminal 4 are embedded and formed so as to be substantially flush with the main surface of the substrate 1 (planarity is about ± 10 μm). ing. The size of the substrate 1 is, for example, 15 mm in length and width and 0.2 mm in thickness, and the size of the chip 2 is, for example, 13 mm in length and width and thickness of 0.
It is 25 mm.

In the semiconductor device shown in FIGS. 2A and 2B, the chip 2 is mounted face down on one main surface of the substrate 1, and the chip 2 is mounted on the connected portion 1b of the substrate 1.
The pad 2c is fixed in a state of being electrically connected, and includes a resin layer 5 filled between the chip 2 and the substrate 1 and cured.

The substrate 1 and the chip 2 are connected and fixed via the bump electrodes 2a. At the time of this fixing, the bump electrode 2a is press-fitted into the connection pad 1b of the substrate 1 so as to embed at least the tip end portion of the bump electrode 2a to fix them, and in this state, the silver paste for the connection pad 1b is heat-cured to bond the two. It is joined. In this case, on the element / pad formation surface of the chip 2, in addition to the circuit connecting pad 2b, the connection reinforcing pads 2c are connected to the respective corners as described above. Since the connection reinforcing pad 1c is also formed at each corner of the surface, the flatness of the opposing surface between the chip 2 and the substrate 1 is improved, and the bondability between the chip 2 and the substrate 1 is improved.

The resin layer 5 is filled between the chip and the substrate (30 to 40 μm in this example), and has substantially even fillets on the outer peripheral side surfaces of the chip. In addition, the resin used when forming the resin layer 5 is a resin that is formed as the resin layer, and the internal stress caused by the difference in the material of the chip and the substrate (Young's modulus, coefficient of thermal expansion, etc.) causes mutual stress between the chip and the substrate. It is desirable to select one having a property of alleviating the deterioration of the connection part of (1) and containing a filler having a diameter (for example, 25 μm or less) that can enter between the chip and the substrate when filling between the chip and the substrate.

That is, in the semiconductor chip of the above-mentioned embodiment, the connection reinforcing pad 2c is formed at each corner of the element / pad formation surface. Further, the semiconductor device of the above embodiment has an ultra-thin and ultra-small single-sided resin-sealed package structure using the semiconductor chip 2.

According to such a semiconductor chip and a semiconductor device, since the connection reinforcing pad 2c exists at the chip corner portion where the thermal stress is most concentrated due to the thermal cycle, etc., it is provided in the vicinity of the chip corner. The circuit connecting pad 2b is less susceptible to stress. Therefore, the electrical connection between the circuit connection pad and the substrate is not impaired, the reliability of the connection between the chip and the substrate is prevented from decreasing, and the reliability and yield of the semiconductor device can be improved and the cost can be reduced. become.

In the above embodiment, the example in which the dummy pad is formed at each corner portion of the element / pad formation surface of the chip is shown, but the invention is not limited to this, and each corner portion on the element / pad formation surface (or Around the corner)
To the connection reinforcing pad other than the dummy pad of the above embodiment,
For example, when the power supply pad to which the power supply potential or the ground potential of the integrated circuit is applied is formed, the same effect as that of the above embodiment can be obtained. Moreover, in this case, even if the connection between a part of the power supply pad and the connection pad on the substrate side is lost, the operation of the integrated circuit is hardly affected.

Further, in the above-mentioned embodiment, the example is shown in which the connection reinforcing pads are formed in the respective corner portions of the element / pad formation surface of the semiconductor chip, but the present invention is not limited to this, and in the corner peripheral portion including the respective corner portions. When the connection-reinforcing pad is formed, the effect described in the above embodiment can be more remarkably obtained.

Examples of the semiconductor chip and the substrate in this case are shown in FIGS. 3 (a) and 3 (b). FIG.
The semiconductor chip 12 shown in (a) shows an example in which, for example, three connection reinforcing pads 2c are formed in an L-shaped arrangement in a corner peripheral portion including each corner portion of the element / pad formation surface.

The substrate 11 shown in FIG. 3 (b) has a substantially L-shape having a size in which, for example, three connection reinforcing pads 1c are connected to a corner peripheral portion including each corner portion on one main surface. 2 shows an example in which the solid type connection reinforcing pad 11c is formed.

As described above, the solid-type connection reinforcing pad 11 is provided around the corners including the corners on the main surface of the substrate.
If the product with c is prepared, the occurrence of cracks and warpage of the substrate is suppressed by the reinforcing action of the solid type connection reinforcing pad 11c during flip chip bonding, and the yield of finished products is improved. Improves noise resistance when the finished product is incorporated into a memory card. Further, the bump electrodes may be formed on the substrate side instead of the chip side.

FIGS. 4A and 4B are perspective views showing an example of a semiconductor device having a single-sided resin-sealed package structure using the chip of FIG. 3A and the substrate of FIG. 3B. FIG.

The substrate and the chip are not limited to have a square outer shape, and may have a rectangular outer shape. Also,
The substrate is not limited to an alumina-based or aluminum nitride-based substrate, and a resin-based substrate (BT resin substrate or the like) may be used.

Further, as shown in FIG. 6, the substrate is one in which wiring and external connection terminals are embedded so as to be substantially flush with the wiring substrate (for example, for an alumina-based insulating base material). Not formed by a green sheet method or a resin-based insulating base material formed by a prepreg method), as shown in FIG. What is formed in the protruding state may be used.

Further, the substrate may have a structure in which the upper and lower surfaces are electrically connected via a blind via hole or a multilayer structure. Further, when the chip is flip-chip bonded onto the substrate, the method is not limited to the method of press-fitting so that at least the tip end of the bump electrode is embedded in the connection pad as in the above-described embodiment, but the details are described in Japanese Patent Application No. 6-50757. As described, solid phase diffusion may occur between the gold connection pads and the gold bump electrodes for bonding.

[0041]

As described above, according to the present invention, even if the distance between the outer edge of the chip and the outer edge of the substrate is very small, the resin can be sealed so as to cover the outer peripheral side surfaces of the bare chip. It is possible to provide a semiconductor device having a single-sided resin-encapsulated package structure capable of further miniaturization, improvement of an effective area ratio occupied by chips on a wiring board, and cost reduction, and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a semiconductor chip and a wiring board flip-chip bonded to the semiconductor chip according to an embodiment of the present invention.

2A and 2B are a perspective view and a cross-sectional view showing an example of a semiconductor device formed using the chip and the substrate of FIG.

FIG. 3 is a plan view schematically showing a semiconductor chip and a wiring board flip-chip bonded to the semiconductor chip according to another embodiment of the present invention.

4A and 4B are a perspective view and a cross-sectional view showing an example of a semiconductor device formed using the chip and the substrate of FIG.

FIG. 5 is a sectional view showing an example of a single-sided resin-sealed package structure according to the prior application.

FIG. 6 is a sectional view showing an example of a single-sided resin-sealed package structure according to another prior application.

FIG. 7 is a view showing an example of an element / pad formation surface of a semiconductor chip used in a conventional resin-sealed semiconductor device.

[Explanation of symbols]

1, 11 ... Wiring board, 1a ... Wiring, 1b ... Connected part, 1
c, 11c ... Pads for reinforcing connection, 2, 12 ... Semiconductor chips, 2a ... Bump electrodes, 2b ... Pads for circuit connection, 2c
... Connection reinforcing pads (dummy pads), 3 ... Through-hole wiring, 4 ... External connection terminals, 5 ... Resin layer, 5a ... Resin.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/04 21/822

Claims (5)

[Claims] 1. A connection-reinforcing pad formed at each corner of an element / pad formation surface and a pad formation region other than each corner of the element / pad formation surface, and electrically connected to the integrated circuit. A semiconductor chip comprising a connected circuit connection pad. 2. The semiconductor chip according to claim 1, wherein
The semiconductor chip, wherein the connection reinforcing pad is a dummy pad that is not electrically connected to an integrated circuit including the element. 3. The semiconductor chip according to claim 1, wherein
The semiconductor chip, wherein the connection reinforcing pad is a power supply pad to which a power supply potential or a ground potential of an integrated circuit including the element is applied. 4. The semiconductor chip according to claim 1,
The semiconductor chip, wherein the connection reinforcing pad is formed at a corner peripheral portion including each corner portion on the element / pad formation surface. 5. The semiconductor chip according to claim 1, and wiring having a connected portion on one main surface, wherein the semiconductor chip is mounted face down on the one main surface, and the connected portion has the above-mentioned structure. A wiring board having pads of a semiconductor chip fixed in a state of being electrically connected via bump electrodes, and a wiring board having external connection terminals that are led out / exposed from the connected portion to the other main surface side, and the semiconductor chip A semiconductor device comprising: a resin layer that is filled between the wiring board and the wiring board and cured.