JPH08153126A - Device and method for supporting circuit designing - Google Patents

Abstract

PURPOSE: To reduce the repetition of redundant operation and shorten the development time by automatically replacing circuit information with circuit information of a synchronous reset system or asynchronous reset system according to setting contents. CONSTITUTION: When a description for adding a reset system in RTL is inputted on a keyboard or with a mouse so as to put plural descriptions regarding a specific circuit together and select and set the reset system while the descriptions of a specific circuit are given, the contents of the reset system, i.e., whether a clock is reset synchronously or asynchronously is automatically selected and judged. When the asynchronous resetting is judged, a description regarding the asynchronous reset system is automatically added. When the synchronous resetting is judged, on the other hand, a description regarding the synchronous reset system is automatically added. Then, after the description of the reset system is added, logic composition and optimization at a gate level are performed by a conversion program.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an ASIC (Appli)
Cation Specific Integrate
d Circuit: The present invention relates to a circuit design support device and method used in CAD for designing a circuit such as a special purpose IC).

[0002]

2. Description of the Related Art In a CAD environment for designing a circuit such as an ASIC, usually, in either case of input in a drawing or input in a hardware description language, a cell is selected in consideration of a reset circuit in advance. And I was supposed to make a description.

That is, in a gate level design such as drawing input, the cells and connections of the register used differ depending on whether the reset method is synchronous or asynchronous. Similarly, even in a register transfer level (hereinafter abbreviated as "RTL") design using a hardware description language (hereinafter abbreviated as "HDL"), the description differs depending on whether the reset method is synchronous or asynchronous. ing.

[0004]

Generally, in circuit design,
It is extremely rare to mix registers with synchronous and asynchronous reset methods in the same module, and if a reset method of synchronous or asynchronous is decided, description of the reset circuit regardless of whether it is RTL input or gate level input. Can be uniformly determined regardless of the function of the circuit.

However, it is indispensable to describe the reset function and select the cell of the register with reset.
Redundant operations such as connecting the same description or the reset source and the reset pin of the cell had to be repeated.

In addition, particularly in the synchronous reset method, when a gate for taking a logical product of the reset signal and the input data of the register is inserted, the reset signal and the input data of the register are input by performing logic synthesis and optimization. There has been a problem that a plurality of combinational circuits are inserted between the gate that takes the logical product of and and the input of the register, and as a result, the clearing of the register is not normally performed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to shorten the development time by reducing the repetition of redundant work in circuit design,
Another object of the present invention is to provide a circuit design support device and method capable of obtaining a circuit whose operation is guaranteed by the reset method.

[0008]

That is, according to the present invention, by setting whether the reset method is synchronous or asynchronous with respect to the RTL circuit information described in the hardware description language, the circuit information is set according to the setting contents. A reset description is automatically added to the circuit information or it is set whether the reset method is synchronous or asynchronous with respect to the circuit information described at the gate level. The circuit information of the reset method is automatically replaced.

[0009]

By taking the above-mentioned means, no matter whether the circuit is designed at the RTL or the gate level, the description about the reset method and the redundant source for connecting the reset source and the reset pin of the cell are redundant. The number of operations can be reduced and the development time can be shortened.

[0010]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit configuration when a CAD system is constructed by a workstation. SB is a system bus, 11 is a microprocessor (CPU), and 12 is an RA accessed by the microprocessor 11.
M and 13 are the same ROM.

Microprocessor (hereinafter referred to as CPU)
Reference numeral 11 is for controlling the entire apparatus, and is for the RAM 12
Also, the ROM 13 is accessed to execute various circuit design processes by starting a program according to the input instruction.

The RAM 12 comprises an area for storing each circuit information described at the level of circuit design and other various data for data processing, and the ROM 13 stores programs such as an operating system and fixed information at various places.

Reference numeral 14 is a keyboard (KB), 16 is a mouse as a pointing device, 17 is a CRT which is a display unit, 20 is a hard disk device (HDD),
22 is a floppy disk device (FDD), and 24 is an interface device (IF).

The keyboard 14 is a keyboard interface (KB-IF) 15 for inputting information necessary for circuit design and the like.
It is input to the CPU 11 via the keyboard 16. The keyboard interface 15 also serves as a pointing input operation control for the mouse 16.

Under the control of the CPU 11 via the disk interface (HDD-IF) 21, the hard disk device 20 converts the HDL conversion program and R associated with the circuit design.
The circuit information described at the TL or the gate level, the library required for the above conversion, and the like are stored.

Similarly, the floppy disk device 22 is a C interface via a disk interface (FDD-IF) 23.
Under the control of the PU 11, various information equivalent to that of the hard disk device 20 is stored and saved.

The interface device 24 transmits / receives data to / from another workstation (not shown) connected to the network under the control of the CPU 11. Next, the specific operation of the above embodiment will be described.

FIG. 2 shows the contents of the reset type setting process at the time of circuit design in RTL using HDL, and FIG. 4 shows VHDL (VHSIC Hardware).
An example of description in the above RTL using eDescription Language) is shown.

That is, FIG. 4A shows one circuit in which the operation and the function are described in RTL without being aware of the reset method.
The flip-flop (F / F) circuit that does not reset and latches the input data at the rising edge of the clock is shown in bold in the figure. "If (CLK) 'event and CLK =' 1 ') then Q <= D; end if ; ”Is used for the description.

In the state where a plurality of descriptions about the circuit as shown in FIG. 4 (1) are made, the description of adding the reset method by RTL is keyboarded so that the reset method can be selected and set collectively. -When inputting with the mouse 14 or the mouse 16, the contents of the reset method, that is, the synchronous reset or the asynchronous reset of the clock is automatically selected and determined by the processing of FIG. 2 (step A1).

If it is determined that the reset is an asynchronous reset, the register is cleared when the reset signal is input regardless of the clock in the description regarding the F / F circuit shown in FIG. 4 (1). A description about the asynchronous reset method is automatically added as indicated by an underline in FIG. 4 (2) (step A2).

That is, in FIG. 4B, a description indicating that the F / F circuit is an asynchronous reset. Is additionally inserted before the description of the F / F circuit, and the description “process (CLK, RESET)” indicates that the F / F circuit takes a processing step directly based on the input of the clock and the reset signal. This is to rewrite and additionally insert a description "end if;" after the description of the F / F circuit.

When it is determined in step A1 that the synchronous reset is performed, the F / F shown in FIG.
In the description of the circuit, the description of the synchronous reset method in which the register is reset in synchronization with the clock is shown in FIG.
(3) is automatically added as underlined (step A)
3).

That is, in FIG. 4 (3), a description indicating that the F / F circuit is in synchronous reset. In the above description of the F / F circuit is additionally inserted after "if (RESET = '0'then"), and a description "end if;" is additionally inserted after the description of this F / F circuit. .

After the process of adding the description of the reset method in step A2 or step A3, the logic synthesis and optimization at the gate level are executed by the conversion program (step A4), and the process of FIG. 2 is completed. is there.

As described above, by simply selecting and setting the reset method for a plurality of circuit information described in RTL, the circuit information of the description corresponding to the reset method can be collectively added to each circuit information. Therefore, it is possible to reduce redundant operations and significantly reduce development time.

2 and 4, the circuit information described according to the reset method is added and inserted into each circuit information at once in the RTL, but the same processing is performed at the gate level. It is possible.

FIG. 3 shows the contents of the reset type setting process at the time of circuit design at the gate level, and FIG. 5 specifically shows the F / F circuit at the gate level.

Here, the circuit information (logic circuit diagram) at the gate level may be information inputted in the drawing or information obtained by logical synthesis from HDL in RTL. Thus, FIG. 5 (1) illustrates an F / F circuit having no reset input at the gate level.

When a plurality of gate level circuits are described as shown in FIG. 5 (1), an instruction to add a reset input is issued in order to collectively select and set the reset method. Board 14 or mouse 1
6 is input, the contents of the reset method, that is, the synchronous reset or the asynchronous reset of the clock is first automatically selected and determined by the processing of FIG. 3 (step B1).

If it is determined that the asynchronous reset has occurred, the F / F circuit shown in FIG.
Automatic replacement is performed so as to form an asynchronous reset type F / F circuit in which a register is cleared when a reset signal is input regardless of the clock shown in (2) (step B2) and an unconnected reset pin is used. Connect and wire to the reset source.

When it is determined in step B1 that the synchronous reset is performed, the F / F shown in FIG.
Instead of the circuit, automatic replacement is performed so as to be a synchronous reset type F / F circuit in which the register is reset in synchronization with the clock shown in FIG. 5C (step B3).
Connect and connect the unconnected reset pin and the reset source.

Further, instead of the processing shown in step B3, instead of the F / F circuit shown in FIG. 5 (1),
Automatic replacement may be performed (step B4) so as to form an F / F circuit of a synchronous reset system using a register with a gate that performs a logical product with the reset signal shown in FIG. 5 (4).

After the replacement processing of the reset type F / F circuit in the above step B2, B3 or B4 is executed, a portion which influences the performance such as a critical path is instructed to be preferentially arranged and wired, and the fan-out is performed. Is adjusted (step B5), and the processing of FIG. 3 is completed.

As described above, by simply selecting and setting the reset method for a plurality of circuit information described at the gate level, the logic circuit diagram corresponding to the reset method is collectively replaced and necessary wiring is performed. Therefore, it is possible to reduce redundant operations and significantly reduce development time.

[0036]

As described above, according to the present invention, by setting whether the reset method is synchronous or asynchronous with respect to the register transfer level circuit information described in the hardware description language, it is possible to respond to the setting contents. By automatically adding a reset description to the circuit information described above, or by setting whether the reset method is synchronous or asynchronous with respect to the circuit information described at the gate level, the circuit information can be synchronized according to the setting contents. Since the circuit information of the reset method or the asynchronous reset method is automatically replaced, the redundant work in the circuit design can be reduced, the development time can be shortened, and a circuit whose operation is guaranteed by the reset method can be obtained. It is possible to provide a possible circuit design support device and method.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the processing contents of the operation according to the embodiment.

FIG. 3 is a flowchart showing the processing contents of the operation according to the embodiment.

FIG. 4 is a view for explaining the operation according to the embodiment.

FIG. 5 is a view for explaining the operation according to the embodiment.

[Explanation of symbols]

11 ... Microprocessor (CPU), 12 ... RAM,
13 ... ROM, 14 ... Keyboard (KB), 16 ... Mouse, 17 ... CRT, 20 ... Hard disk drive (HD
D), 22 ... Floppy disk device (FDD), 24
... interface device (IF).

Claims (6)

[Claims] 1. Setting means for setting whether the reset method is synchronous or asynchronous with respect to register transfer level circuit information described in a hardware description language, and resetting to the circuit information according to the setting contents of the setting means. And a description adding means for automatically adding the description of 1. 2. A setting means for setting whether the reset method is synchronous or asynchronous with respect to the circuit information described at the gate level, and the circuit information is a synchronous reset method or an asynchronous reset method according to the setting content of the setting means. And a description replacement means for automatically replacing the same circuit information with the above circuit information. 3. The circuit design support according to claim 2, wherein the description replacing means adds circuit information of a gate which takes a logical product with a reset signal instead of replacing the circuit information in the synchronous reset method. apparatus. 4. A setting process for setting whether the reset method is synchronous or asynchronous with respect to register transfer level circuit information described in a hardware description language, and resetting the circuit information according to the setting content of this setting process. And a description adding process for automatically adding the description of 1. 5. A setting process for setting whether the reset method is synchronous or asynchronous with respect to the circuit information described at the gate level, and the circuit information is synchronously reset or asynchronously reset according to the setting contents of this setting process. And a description replacement process for automatically replacing the same circuit information with the circuit design support method. 6. The circuit design support according to claim 5, wherein the description replacement process adds circuit information of a gate that takes a logical product with a reset signal instead of replacing the circuit information with the synchronous reset method. Method.