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JPH0815143B2 - Method for manufacturing 3C-SiC semiconductor device - Google Patents

Method for manufacturing 3C-SiC semiconductor device

Info

Publication number
JPH0815143B2
JPH0815143B2 JP24984786A JP24984786A JPH0815143B2 JP H0815143 B2 JPH0815143 B2 JP H0815143B2 JP 24984786 A JP24984786 A JP 24984786A JP 24984786 A JP24984786 A JP 24984786A JP H0815143 B2 JPH0815143 B2 JP H0815143B2
Authority
JP
Japan
Prior art keywords
substrate
sic
single crystal
buffer layer
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP24984786A
Other languages
Japanese (ja)
Other versions
JPS63102311A (en
Inventor
昭一郎 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
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Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP24984786A priority Critical patent/JPH0815143B2/en
Publication of JPS63102311A publication Critical patent/JPS63102311A/en
Publication of JPH0815143B2 publication Critical patent/JPH0815143B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、Si(シリコン)基板と3C(Cubic)−SiC
(シリコンカーバイド)単結晶との間に3C−SiC炭化バ
ッファ層を備えた3C−SiC半導体装置を製造する方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a Si (silicon) substrate and 3C (Cubic) -SiC.
The present invention relates to a method for manufacturing a 3C-SiC semiconductor device having a 3C-SiC carbonization buffer layer between a (silicon carbide) single crystal.

〔従来の技術〕[Conventional technology]

3C−SiC半導体装置は、第4図に示す如くSi基板1の
上に3C−SiC炭化バッファ層2を形成したのち目的とす
る3C−SiC単結晶膜3を形成した構成としている。
As shown in FIG. 4, the 3C-SiC semiconductor device has a structure in which a 3C-SiC carbonization buffer layer 2 is formed on a Si substrate 1 and then a desired 3C-SiC single crystal film 3 is formed.

このように炭化バッファ層を形成するのは、仮にSi基
板上に3C−SiC単結晶を直接形成した場合は、Si基板と3
C−SiC単結晶との格子定数が異なることにより3C−SiC
単結晶に格子欠陥が発生し易いからであり、このため炭
化バッファ層を形成することにより格子欠陥の発生を防
止している。
The carbonized buffer layer is formed in this way if the 3C-SiC single crystal is directly formed on the Si substrate and the Si substrate and the 3C-SiC single crystal are formed.
Due to the difference in lattice constant from C-SiC single crystal, 3C-SiC
This is because lattice defects are likely to occur in the single crystal. Therefore, the formation of the carbonization buffer layer prevents the lattice defects from occurring.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

ところで、上述の3C−SiC半導体装置をCVD(Che−mic
al Vapor Deposition)法を用いて成長させる場合、3C
−SiC炭化バッファ層2及び3C−SiC単結晶3を形成する
ときの基板温度は夫々1360℃,1350℃と高温である。
By the way, the above 3C-SiC semiconductor device is
3C when growing using the al Vapor Deposition method
The substrate temperatures when forming the -SiC carbonization buffer layer 2 and the 3C-SiC single crystal 3 are as high as 1360 ° C and 1350 ° C, respectively.

このため、3C−SiC炭化バッファ層2及び3C−SiC単結
晶3へ反応系からの不純物が取込まれ易い。
Therefore, impurities from the reaction system are easily incorporated into the 3C-SiC carbonization buffer layer 2 and the 3C-SiC single crystal 3.

また、Si基板1がその融点(1420℃)に近い温度とな
るため、Si基板1にスリップライン等の格子欠陥が発生
して半導体装置が劣化し易くなる等の問題がある。
Further, since the temperature of the Si substrate 1 is close to its melting point (1420 ° C.), lattice defects such as slip lines occur in the Si substrate 1 and the semiconductor device is apt to deteriorate.

この問題は基板温度を低くすることにより解決できる
が、基板温度を低くした場合は、成長速度を速くする
と、成長膜が双晶,多結晶となって3C−SiC単結晶を成
長させ得ず、3C−SiC単結晶を成長させるためには成長
速度を遅くしなければならない。このため厚い3C−SiC
単結晶の形成に長時間を要し、不利である。
This problem can be solved by lowering the substrate temperature, but when the substrate temperature is lowered, if the growth rate is increased, the growth film becomes twinned or polycrystalline, and 3C-SiC single crystal cannot be grown, In order to grow a 3C-SiC single crystal, the growth rate must be slowed down. Therefore, thick 3C-SiC
It takes a long time to form a single crystal, which is disadvantageous.

また、基板温度が低い場合には、格子定数の違いに基
づく格子欠陥が発生しやすい状態となる。
In addition, when the substrate temperature is low, a lattice defect due to a difference in lattice constant is likely to occur.

従って、CVD法による場合は、基板温度を低くするだ
けでは格子欠陥のない良質の3C−SiC半導体装置を製造
できない。
Therefore, in the case of the CVD method, it is not possible to manufacture a good quality 3C-SiC semiconductor device having no lattice defects simply by lowering the substrate temperature.

本発明は斯かる事情に鑑みてなされたものであり、格
子欠陥のない3C−SiC半導体装置を製造する方法を提供
することを目的とする。
The present invention has been made in view of such circumstances, and an object thereof is to provide a method for manufacturing a 3C-SiC semiconductor device having no lattice defect.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、反応雰囲気を高真空度雰囲気とし、その雰
囲気中で炭化水素ガスとシリコンとを反応させ、その反
応生成物のSiCを比較的低温度のSi基板上に層状に形成
して3C−SiC半導体装置を製造する。
The present invention, the reaction atmosphere is a high vacuum atmosphere, the hydrocarbon gas and silicon are reacted in the atmosphere, SiC of the reaction product is formed into a layer on a Si substrate of relatively low temperature 3C- Manufactures SiC semiconductor devices.

即ち、本発明に係る3C−SiC半導体装置の製造方法
は、Si基板と3C−SiC単結晶との間に3C−SiC炭化バッフ
ァ層を備えた3C−SiC半導体装置の製造方法において、
高真空に保持した反応室内にて炭化水素ガスとSiとを反
応させ、反応室内のSi基板上に3C−SiC炭化バッファ層
を形成し、次いでSi基板温度を昇温してその上に3C−Si
C単結晶バッファ層を形成したのち、Si基板温度を更に
昇温して3C−SiC単結晶バッファ層形成時より速い速度
で3C−SiC単結晶を形成することを特徴とする。
That is, the method for manufacturing a 3C-SiC semiconductor device according to the present invention is a method for manufacturing a 3C-SiC semiconductor device having a 3C-SiC carbonization buffer layer between a Si substrate and a 3C-SiC single crystal,
Hydrocarbon gas and Si are reacted in a reaction chamber held in a high vacuum to form a 3C-SiC carbonization buffer layer on the Si substrate in the reaction chamber, and then the temperature of the Si substrate is raised to 3C- Si
After the C single crystal buffer layer is formed, the temperature of the Si substrate is further raised to form the 3C-SiC single crystal at a faster rate than when forming the 3C-SiC single crystal buffer layer.

〔実施例〕〔Example〕

以下本発明を図面に基づき具体的に説明する。第1図
は本発明の実施状態を示す模式図であり、図中10は化成
分子線装置の釣鐘状の反応室を示す。反応室10の周面の
一部は開口され、その開口部の外側には基板挿入,取出
用の挿入室11が設けられており、挿入室11及び反応室10
は図示しないポンプにて高真空度に真空引きされるよう
になっている。挿入室11より反応室10内へ挿入されたSi
基板1は、反応室10の天井部分に設けられたマニュピュ
レータ14にて高さ制御及び水平方向の回転制御がなされ
る基板ホルダ13に取付けられて所定位置で所定方向に向
けてセットされ、また反応室外へ取出せるようになって
いる。基板ホルダ13のSi基板1取付部分にはヒータ(図
示せず)が設けられており、Si基板1はこのヒータによ
り所定温度に加熱される。
The present invention will be specifically described below with reference to the drawings. FIG. 1 is a schematic diagram showing an embodiment of the present invention. In the figure, reference numeral 10 denotes a bell-shaped reaction chamber of a chemical vapor line device. A part of the peripheral surface of the reaction chamber 10 is opened, and an insertion chamber 11 for inserting and removing the substrate is provided outside the opening.
Is evacuated to a high degree of vacuum by a pump (not shown). Si inserted into the reaction chamber 10 from the insertion chamber 11
The substrate 1 is attached to a substrate holder 13 whose height and horizontal rotation are controlled by a manipulator 14 provided on the ceiling of the reaction chamber 10 and set at a predetermined position in a predetermined direction. It can be taken out of the reaction chamber. A heater (not shown) is provided on the portion of the substrate holder 13 where the Si substrate 1 is attached, and the Si substrate 1 is heated to a predetermined temperature by this heater.

セットされたSi基板1の反応面と直交する方向の反応
室10部分は、開口してその開口部に円筒の一端を取付
け、その他端を蓋で密封してあり、その蓋にはKnudsen
セル12及びガス噴出用ノズル15が設けられている。ノズ
ル15はその先端を反応室10内に挿入してガス噴出方向を
Si基板1の反応面に向けている。
The reaction chamber 10 in the direction orthogonal to the reaction surface of the set Si substrate 1 is opened, one end of a cylinder is attached to the opening, and the other end is sealed with a lid, and the lid is Knudsen.
A cell 12 and a gas ejection nozzle 15 are provided. The tip of the nozzle 15 is inserted into the reaction chamber 10 so that the direction of gas ejection is
It faces the reaction surface of the Si substrate 1.

ノズル15の基端は管を介して図示しないガスタンクに
連結されており、ガスタンクには高純度炭化水素ガス、
例えば純度が5nineのアセチレンガスが貯留されてい
る。
The base end of the nozzle 15 is connected to a gas tank (not shown) via a pipe, and the gas tank has a high-purity hydrocarbon gas,
For example, acetylene gas with a purity of 5nine is stored.

ノズル15の先端とSi基板1とが対向する間のすぐ下に
はるつぼ17が設けられており、るつぼ17には例えば純度
が10nineの高純度シリコンが貯留されている。るつぼ17
の近傍にはエレクトロンビーム発生装置16が設けられて
おり、エレクトロンビーム発生装置16は電子(e-)を発
生させてこれをるつぼ17内のシリコンに衝突させる。
A crucible 17 is provided immediately below the tip of the nozzle 15 and the Si substrate 1 facing each other. The crucible 17 stores, for example, high-purity silicon having a purity of 10 nine. Crucible 17
In the vicinity of which is provided an electron beam generator 16, an electron beam generator 16 is an electronic (e -) which collide in the silicon in the crucible 17 by generating.

反応室10の周面には、電子線発生装置18が電子線出射
口を反応室内に挿入し、出射方向をシリコン基板1に向
けて設けられており、反応室10の内壁にはスクリーン18
aがSi基板1を通過した回析線を捉え得るように設けら
れている。電子線発生装置18とスクリーン18aとは電子
線回析装置を構成し、電子線回析装置は成長膜の表面状
態等を検出する。
An electron beam generator 18 is provided on the peripheral surface of the reaction chamber 10 so that the electron beam emission port is inserted into the reaction chamber and the emission direction is directed toward the silicon substrate 1. The screen 18 is provided on the inner wall of the reaction chamber 10.
a is provided so that a diffraction line passing through the Si substrate 1 can be captured. The electron beam generator 18 and the screen 18a constitute an electron beam diffractometer, and the electron beam diffractometer detects the surface state of the growth film and the like.

また、反応室10の周面には基板ホルダ13近傍での分子
線強度を測定する分子線強度測定装置(図示せず)及び
質量分析計19が設けられており、質量分析計19は反応室
内での分子,原子等の存在を確認するためのものであ
る。
Further, a molecular beam intensity measuring device (not shown) for measuring the molecular beam intensity in the vicinity of the substrate holder 13 and a mass spectrometer 19 are provided on the peripheral surface of the reaction chamber 10, and the mass spectrometer 19 is the reaction chamber. This is to confirm the existence of molecules, atoms, etc. in.

このように構成された装置による本発明の製造方法を
次に説明する。
The manufacturing method of the present invention using the apparatus thus configured will be described below.

まず、マニュピュレータ14にて基板ホルダ13を挿入室
11近傍の基板取付可能位置にまで移動させ、Si基板1を
挿入室11より挿入して基板ホルダ13上に取付ける。その
後、マニュピュレータ14により基板ホルダ13を移動させ
てセットしたのち図示しないホンプを作動させて反応室
10及び挿入室11の内部を真空引きする。
First, insert the substrate holder 13 into the insertion chamber with the manipulator 14.
The substrate is moved to a position where the substrate can be mounted in the vicinity of 11, and the Si substrate 1 is inserted from the insertion chamber 11 and mounted on the substrate holder 13. After that, the substrate holder 13 is moved and set by the manipulator 14, and then a not shown hump is operated to activate the reaction chamber.
The inside of 10 and the insertion chamber 11 is evacuated.

然る後、所定真空度に達すると基板ホルダ13のヒータ
(図示せず)に通電してSi基板1の加熱を開始する。Si
基板1の温度が1100℃となると暫くの間その温度に保持
してSi基板1表面の清浄化を図る(第1工程)。
After that, when the predetermined vacuum degree is reached, the heater (not shown) of the substrate holder 13 is energized to start heating the Si substrate 1. Si
When the temperature of the substrate 1 reaches 1100 ° C., the temperature is maintained for a while to clean the surface of the Si substrate 1 (first step).

次いで、基板温度を降下させて炭化温度が安定化する
750℃〜820℃の或る一定温度に基板温度を保持し、反応
室10内へノズル15よりアセチレンガスを導入してアセチ
レンガス圧力を7×10-6Torrとした。この状態を5分間
維持する(第2工程)。これにより、第2図に示す如
く、Si基板1上に3C−SiC炭化バッファ層2が成長す
る。
Then, the substrate temperature is lowered to stabilize the carbonization temperature.
The substrate temperature was maintained at a certain constant temperature of 750 ° C. to 820 ° C., and acetylene gas was introduced into the reaction chamber 10 through the nozzle 15 to adjust the acetylene gas pressure to 7 × 10 −6 Torr. This state is maintained for 5 minutes (second step). As a result, as shown in FIG. 2, the 3C-SiC carbonization buffer layer 2 grows on the Si substrate 1.

この3C−SiC炭化バッファ層2は厚み方向各位置で組
成が異なるが、上表面層は単結晶となっている。
The composition of the 3C-SiC carbonized buffer layer 2 is different at each position in the thickness direction, but the upper surface layer is a single crystal.

然る後、基板温度を昇温させて1150℃に保持し、反応
室10内へノズル15よりアセチレンガスを導入し、また同
時にエレクトロンビーム発生装置16を作動させてルツボ
17内のシリコンを原子状態でSi基板1に照射する。この
とき、分子線強度測定装置(図示せず)を監視してアセ
チレンの分子線強度(Ia)とシリコンの分子線強度(I
b)との比、つまり分子線強度比(Ia/Ib)を100以下と
する(第3工程)。これにより、第2図に示す如く3C−
SiC単結晶バッファ層4が30Å/分以下の遅い成長速度
で形成される。この3C−SiC単結晶バッファ層4は3C−S
iC炭化バッファ層2の表面が粗いため、3C−SiC単結晶
バッファ層4の上に成長させる層の厚みを均一にすべ
く、上表面を平滑に形成する。3C−SiC単結晶バッファ
層4の平滑度は前記電子線回析装置にて検出される。
After that, the temperature of the substrate is raised and maintained at 1150 ° C., acetylene gas is introduced into the reaction chamber 10 through the nozzle 15, and at the same time, the electron beam generator 16 is activated to operate the crucible.
The Si substrate 1 is irradiated with the silicon in 17 in an atomic state. At this time, the molecular beam intensity measuring device (not shown) is monitored to monitor the molecular beam intensity (Ia) of acetylene and the molecular beam intensity (Ia) of silicon.
b), that is, the molecular beam intensity ratio (Ia / Ib) is 100 or less (third step). As a result, as shown in FIG.
The SiC single crystal buffer layer 4 is formed at a slow growth rate of 30 Å / min or less. This 3C-SiC single crystal buffer layer 4 is 3C-S
Since the surface of the iC carbonization buffer layer 2 is rough, the upper surface is formed smooth so that the thickness of the layer grown on the 3C-SiC single crystal buffer layer 4 becomes uniform. The smoothness of the 3C-SiC single crystal buffer layer 4 is detected by the electron beam diffraction apparatus.

3C−SiC単結晶バッファ層4をその上表面が平滑にな
るように形成した後、基板温度を更に上昇して1200℃に
保持し、上記分子線強度比を100以下とする(第4工
程)。これにより第2図に示す如く3C−SiC単結晶3が3
C−SiC単結晶バッファ層4のときよりも速い100Å/分
以下の成長速度で形成される。
After the 3C-SiC single crystal buffer layer 4 is formed so that its upper surface is smooth, the substrate temperature is further raised and maintained at 1200 ° C to set the molecular beam intensity ratio to 100 or less (fourth step). . As a result, the 3C-SiC single crystal 3 becomes 3 as shown in FIG.
It is formed at a growth rate of 100 Å / min or less, which is higher than that of the C-SiC single crystal buffer layer 4.

この3C−SiC単結晶3が所望厚形成されるとアセチレ
ンガス及びシリコンの反応室10内への供給等を停止し、
反応を終了する。
When the desired thickness of the 3C-SiC single crystal 3 is formed, the supply of acetylene gas and silicon into the reaction chamber 10 is stopped,
The reaction is completed.

第3図は上述の本発明の各工程での基板温度を示すグ
ラフであり、横軸に時間をとり、縦軸に基板温度(℃)
をとって示している。
FIG. 3 is a graph showing the substrate temperature in each step of the present invention described above, where the horizontal axis represents time and the vertical axis represents the substrate temperature (° C.).
Is shown.

この図より理解される如く本発明による場合は、高真
空中で層成長を行うので、基板温度が低くても格子欠陥
なしに3C−SiC炭化バッファ層2、3C−SiC単結晶バッフ
ァ層4及び3C−SiC単結晶を形成することができる。ま
た基板温度を低くできることで製造された半導体装置は
反応系から取込まれる不純物量が少なく、またスリップ
ライン等の格子欠陥がない。
As understood from this figure, in the case of the present invention, since the layer growth is performed in a high vacuum, the 3C-SiC carbonization buffer layer 2, the 3C-SiC single crystal buffer layer 4 and A 3C-SiC single crystal can be formed. Further, since the substrate temperature can be lowered, the manufactured semiconductor device has a small amount of impurities taken in from the reaction system and has no lattice defects such as slip lines.

なお、上記実施例では化成分子線装置の反応室内にシ
リコン源を予め入れておき、層成長を行っているが、本
発明はこの装置を使用せずともよく、例えば高真空度に
反応室内を保持できる半導体製造装置の反応室内へ外部
からSiを含むガス(例えば、SiH4、SiHC1)と炭化水素
ガス(例えばC3H8)とを供給しても実施できる。尚、こ
の場合、ソース源の種類によって、最適成長温度や分子
線強度比は異なる。
In the above example, the silicon source was previously placed in the reaction chamber of the chemical vapor beam apparatus to perform layer growth, but the present invention does not need to use this apparatus. It can also be carried out by supplying a gas containing Si (for example, SiH 4 , SiHC 1) and a hydrocarbon gas (for example, C 3 H 8 ) into the reaction chamber of the semiconductor manufacturing apparatus that can be held from the outside. In this case, the optimum growth temperature and the molecular beam intensity ratio differ depending on the type of the source.

また、ガスソースを或る高い温度で加熱することによ
り、安定な分子状態から活性な分子状態にクラッキング
させた後に供給しても、3C−SiC単結晶層の生成が可能
であり、成長温度も当然低温化される。
Further, by heating the gas source at a certain high temperature, even if the gas source is cracked from a stable molecular state to an active molecular state and then supplied, a 3C-SiC single crystal layer can be generated, and the growth temperature is also increased. Naturally the temperature is lowered.

〔効果〕〔effect〕

以上詳述した如く、本発明による場合には高真空中で
層成長を行うので、基板を比較的低い温度にした状態で
各層を成長させ得、このため反応系から各層へ取込まれ
る不純物量を減少でき、また格子欠陥の発生を防止でき
る。更に、3C−SiC単結晶バッファ層を形成するので、3
C−SiC単結晶の表面を平滑にできる等、本発明は優れた
効果を奏する。
As described above in detail, in the case of the present invention, since the layers are grown in a high vacuum, it is possible to grow each layer while keeping the substrate at a relatively low temperature. Therefore, the amount of impurities taken in from the reaction system to each layer can be increased. Can be reduced and the occurrence of lattice defects can be prevented. Furthermore, since a 3C-SiC single crystal buffer layer is formed,
The present invention has excellent effects such as smoothing the surface of a C-SiC single crystal.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の実施状態を示す模式図、第2図は本発
明により製造した半導体装置の断面構造図、第3図は本
発明による場合の基板温度の推移を示すグラフ、第4図
は従来装置の断面構造図である。 1……Si基板、2……3C−SiC炭化バッファ層、3……3
C−SiC単結晶、4……3C−SiC単結晶バッファ層、10…
…反応室
FIG. 1 is a schematic diagram showing an embodiment of the present invention, FIG. 2 is a sectional structural view of a semiconductor device manufactured by the present invention, FIG. 3 is a graph showing a transition of substrate temperature in the case of the present invention, and FIG. FIG. 4 is a cross-sectional structure diagram of a conventional device. 1 ... Si substrate, 2 ... 3C-SiC carbonized buffer layer, 3 ... 3
C-SiC single crystal, 4 ... 3C-SiC single crystal buffer layer, 10 ...
… Reaction chamber

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】Si基板と3C−SiC単結晶との間に3C−SiC炭
化バッファ層を備えた3C−SiC半導体装置の製造方法に
おいて、 高真空に保持した反応室内にて炭化水素ガスとSiとを反
応させ、反応室内のSi基板上に3C−SiC炭化バッファ層
を形成し、次いでSi基板温度を昇温してその上に3C−Si
C単結晶バッファ層を形成したのち、Si基板温度を更に
昇温して3C−SiC単結晶バッファ層形成時より速い速度
で3C−SiC単結晶を形成することを特徴とする3C−SiC半
導体装置の製造方法。
1. A method of manufacturing a 3C-SiC semiconductor device comprising a 3C-SiC carbonization buffer layer between a Si substrate and a 3C-SiC single crystal, wherein a hydrocarbon gas and Si are contained in a reaction chamber kept at a high vacuum. Are reacted to form a 3C-SiC carbonization buffer layer on the Si substrate in the reaction chamber, and then the temperature of the Si substrate is raised to raise the temperature of 3C-Si on the Si substrate.
After forming the C single crystal buffer layer, the Si substrate temperature is further raised to form the 3C-SiC single crystal at a faster rate than when the 3C-SiC single crystal buffer layer is formed. Manufacturing method.
JP24984786A 1986-10-20 1986-10-20 Method for manufacturing 3C-SiC semiconductor device Expired - Lifetime JPH0815143B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24984786A JPH0815143B2 (en) 1986-10-20 1986-10-20 Method for manufacturing 3C-SiC semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24984786A JPH0815143B2 (en) 1986-10-20 1986-10-20 Method for manufacturing 3C-SiC semiconductor device

Publications (2)

Publication Number Publication Date
JPS63102311A JPS63102311A (en) 1988-05-07
JPH0815143B2 true JPH0815143B2 (en) 1996-02-14

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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002220299A (en) * 2001-01-19 2002-08-09 Hoya Corp Single crystal SiC and method of manufacturing the same, SiC semiconductor device, and SiC composite material

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02159020A (en) * 1988-12-13 1990-06-19 Fujitsu Ltd Manufacture of semiconductor device
US5972801A (en) * 1995-11-08 1999-10-26 Cree Research, Inc. Process for reducing defects in oxide layers on silicon carbide
DE19755979A1 (en) 1996-12-09 1999-06-10 Inst Halbleiterphysik Gmbh Silicon germanium heterobipolar transistor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
第33回応用物理学会学術講演会講演予稿集(1986)P.6352P−T−7

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002220299A (en) * 2001-01-19 2002-08-09 Hoya Corp Single crystal SiC and method of manufacturing the same, SiC semiconductor device, and SiC composite material

Also Published As

Publication number Publication date
JPS63102311A (en) 1988-05-07

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