JPH08148948A - Power amplifier circuit - Google Patents
Power amplifier circuitInfo
- Publication number
- JPH08148948A JPH08148948A JP6287842A JP28784294A JPH08148948A JP H08148948 A JPH08148948 A JP H08148948A JP 6287842 A JP6287842 A JP 6287842A JP 28784294 A JP28784294 A JP 28784294A JP H08148948 A JPH08148948 A JP H08148948A
- Authority
- JP
- Japan
- Prior art keywords
- amplifier circuit
- input terminal
- output
- speaker
- signal
- Prior art date
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Abstract
(57)【要約】
【目的】 スピーカの逆起電圧と同相同振幅の信号を発
生させ、両者間に電位差を発生させず、信号成分のみを
スピーカに供給する。
【構成】 本発明の電力増幅回路は、差動入力を持つ第
一および第二の増幅回路と緩衝増幅回路20より構成さ
れ、前記第一の増幅回路10の正の入力端子11は信号
入力端子40に接続され、前記第一の増幅回路の出力は
前記第二の増幅回路30の正入力端子32と前記緩衝増
幅回路20の正入力端子に接続され、前記第二の増幅回
路30の出力は前記第一の増幅回路10の負の入力端子
12に接続され、前記緩衝増幅回路20の出力が前記第
二の増幅回路30の負入力端子31と信号出力端子41
に接続して構成される。
(57) [Abstract] [Purpose] Generates a signal of the same phase and amplitude as the back electromotive voltage of the speaker, does not generate a potential difference between the two, and supplies only the signal component to the speaker. A power amplifier circuit of the present invention comprises first and second amplifier circuits having differential inputs and a buffer amplifier circuit 20, and the positive input terminal 11 of the first amplifier circuit 10 is a signal input terminal. 40, the output of the first amplifier circuit is connected to the positive input terminal 32 of the second amplifier circuit 30 and the positive input terminal of the buffer amplifier circuit 20, and the output of the second amplifier circuit 30 is It is connected to the negative input terminal 12 of the first amplifier circuit 10, and the output of the buffer amplifier circuit 20 is the negative input terminal 31 and the signal output terminal 41 of the second amplifier circuit 30.
Connected to.
Description
【0001】[0001]
【産業上の利用分野】本発明は、主にAV機器および情
報通信機器等に用いられる音響用スピーカ駆動電力増幅
回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speaker drive power amplifier circuit for audio, which is mainly used in AV equipment and information communication equipment.
【0002】[0002]
【従来の技術】従来より、AV機器等に用いられる音響
用スピーカ駆動電力増幅回路は入力の波形を忠実に負荷
であるスピーカに供給する事が求められている。とりわ
けダイナミックスピーカはそのインダクタンス成分によ
り逆起電圧を発生することが知られている。このような
ダイナミックスピーカを無帰還又は電圧帰還増幅回路で
駆動すると、逆起電圧は増幅回路を通じてスピーカのボ
イスコイルを流れて、本来原音にない音を鳴らし聴感を
著しく損なっていた。そこで逆起電圧による音を減少さ
せるために、従来から図5に示すような電流帰還増幅回
路が用いられていた。この電流帰還増幅回路はスピーカ
のボイスコイルLを流れる電流波形を微小抵抗rで検知
して帰還を行うために、入力の波形に忠実な電流がスピ
ーカのボイスコイルLに流れることになる。また、スピ
ーカのボイスコイルLで発生した逆起電圧vの発生源も
この電流帰還増幅回路の負帰還ループの中に含んでしま
うため、負帰還作用により逆起電圧vが抑制されてしま
うメリットがあった。しかし、電流帰還増幅回路には次
の欠点がある。2. Description of the Related Art Conventionally, an audio speaker driving power amplifier circuit used in AV equipment or the like has been required to faithfully supply an input waveform to a speaker as a load. In particular, it is known that a dynamic speaker generates a counter electromotive voltage due to its inductance component. When such a dynamic speaker is driven by a non-feedback or voltage feedback amplifier circuit, a counter electromotive voltage flows through the amplifier's voice coil through the amplifier circuit, and a sound that is not originally the original sound is produced, resulting in a significant loss of hearing. Therefore, in order to reduce the sound due to the counter electromotive voltage, a current feedback amplifier circuit as shown in FIG. 5 has been conventionally used. Since the current feedback amplifier circuit detects the current waveform flowing through the voice coil L of the speaker by the small resistance r and performs feedback, a current faithful to the waveform of the input flows through the voice coil L of the speaker. Further, since the source of the counter electromotive voltage v generated in the voice coil L of the speaker is also included in the negative feedback loop of the current feedback amplifier circuit, there is an advantage that the counter electromotive voltage v is suppressed by the negative feedback action. there were. However, the current feedback amplifier circuit has the following drawbacks.
【0003】即ち、スピーカのインピーダンスは周波数
により変動するので、電流帰還増幅回路は負荷インピー
ダンスが上がると負帰還量が減少して利得が上がりスピ
ーカの音圧が上がる。即ちスピーカの負荷インピーダン
スに対応した音圧が発生し、求める平坦な周波数(音
圧)特性から外れたものとなってしまう欠点があった。
電圧帰還増幅回路では平坦な周波数特性は得られるが逆
起電圧を抑制できず、電流帰還増幅回路では逆起電圧は
抑制できるが平坦な周波数特性が得られない欠点があっ
た。That is, since the impedance of the speaker fluctuates depending on the frequency, when the load impedance of the current feedback amplifier circuit increases, the amount of negative feedback decreases, the gain increases, and the sound pressure of the speaker increases. That is, there is a drawback that a sound pressure corresponding to the load impedance of the speaker is generated, which is out of the desired flat frequency (sound pressure) characteristic.
The voltage feedback amplifier circuit has a drawback that flat frequency characteristics cannot be suppressed but the counter electromotive voltage cannot be suppressed, and the current feedback amplifier circuit can suppress counter electromotive voltage but a flat frequency characteristic cannot be obtained.
【0004】[0004]
【発明が解決しようとする課題】本発明は、スピーカの
インピーダンス特性に依存せず、且つ電圧帰還や電流帰
還に依ることなく、スピーカが発生する逆起電圧の影響
を取り除く電力増幅回路を提供することを目的とする。SUMMARY OF THE INVENTION The present invention provides a power amplifier circuit that eliminates the influence of a back electromotive force generated by a speaker without depending on the impedance characteristic of the speaker and on voltage feedback or current feedback. The purpose is to
【0005】[0005]
【課題を解決するための手段】上記従来の課題を解決す
るために本発明の電力増幅回路は、差動入力を持つ第一
および第二の増幅回路と緩衝増幅回路より構成され、前
記第一の増幅回路の正の入力端子は信号入力端子に接続
され、前記第一の増幅回路の出力は前記第二の増幅回路
の正入力端子と前記緩衝増幅回路の正入力端子に接続さ
れ、前記第二の増幅回路の出力は前記第一の増幅回路の
負の入力端子に接続され、前記緩衝増幅回路の出力が前
記第二の増幅回路の負入力端子と信号出力端子に接続し
て構成される。In order to solve the above-mentioned conventional problems, a power amplifier circuit of the present invention comprises first and second amplifier circuits having differential inputs and a buffer amplifier circuit. The positive input terminal of the amplifier circuit is connected to the signal input terminal, the output of the first amplifier circuit is connected to the positive input terminal of the second amplifier circuit and the positive input terminal of the buffer amplifier circuit, The output of the second amplifier circuit is connected to the negative input terminal of the first amplifier circuit, and the output of the buffer amplifier circuit is connected to the negative input terminal and the signal output terminal of the second amplifier circuit. .
【0006】[0006]
【作用】この構成によって、電力増幅回路の出力には、
電力増幅回路の利得倍された入力信号と、スピーカの端
子に発生した逆起電圧と同相同振幅の電圧とを発生する
ため、スピーカの逆起電圧による電位差は発生せず、入
力信号成分のみがスピーカに流れ、且つ周波数特性もス
ピーカのインピーダンスとは無関係に平坦とすることが
できる。With this configuration, the output of the power amplifier circuit is
Since the input signal multiplied by the gain of the power amplifier circuit and the voltage having the same phase and same amplitude as the counter electromotive voltage generated at the speaker terminals are generated, the potential difference due to the counter electromotive voltage of the speaker does not occur and only the input signal component is generated. It can flow to the speaker and the frequency characteristic can be flattened regardless of the impedance of the speaker.
【0007】[0007]
(実施例1)以下に本発明の実施例について、図面を参
照しながら説明する。(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.
【0008】図1は本発明の第1の実施例の動作原理を
説明するための説明図である。図1において、40およ
び41は本発明の電力増幅回路1のそれぞれ信号入力端
子および信号出力端子、11および12は利得Aを有す
る第一の増幅回路10のそれぞれ正の入力端子および負
の入力端子、31および32は利得Bを有する第二の増
幅回路30のそれぞれ負入力端子および正入力端子、1
3および33はそれぞれ第一および第二の増幅回路の出
力端子、20は緩衝増幅回路、42は本発明の電力増幅
回路1の信号出力端子41に接続されたスピーカであ
る。FIG. 1 is an explanatory diagram for explaining the operating principle of the first embodiment of the present invention. In FIG. 1, 40 and 41 are signal input terminals and signal output terminals of the power amplifier circuit 1 of the present invention, and 11 and 12 are positive input terminals and negative input terminals of the first amplifier circuit 10 having a gain A, respectively. , 31 and 32 are the negative input terminal and the positive input terminal of the second amplifier circuit 30 having the gain B, respectively.
3 and 33 are output terminals of the first and second amplifier circuits, 20 is a buffer amplifier circuit, and 42 is a speaker connected to the signal output terminal 41 of the power amplifier circuit 1 of the present invention.
【0009】第一および第二の増幅回路は共に差動入力
を有し、入出力直線性も同等なものであることが好まし
い。また緩衝増幅回路20は利得が1で非反転の増幅回
路であり、たとえばコンプリメンタリーのエミッタフォ
ロワー回路を用いることができる。It is preferable that both the first and second amplifier circuits have differential inputs and have the same input / output linearity. The buffer amplifier circuit 20 is a non-inverting amplifier circuit having a gain of 1, and for example, a complementary emitter follower circuit can be used.
【0010】いま信号入力端子40から入った入力信号
EIは、第一の増幅回路10の正の入力端子11に供給
される。第一の増幅回路10の出力端子13に現れた出
力電圧EOは緩衝増幅回路20の入力に供給される一
方、第二の増幅回路30の正入力端子32に供給され
る。第二の増幅回路30の負入力端子31には緩衝増幅
回路20の出力が供給されると同時に信号出力端子41
にも供給されている。The input signal E I that has just entered from the signal input terminal 40 is supplied to the positive input terminal 11 of the first amplifier circuit 10. The output voltage E O appearing at the output terminal 13 of the first amplifier circuit 10 is supplied to the input of the buffer amplifier circuit 20, while being supplied to the positive input terminal 32 of the second amplifier circuit 30. The output of the buffer amplifier circuit 20 is supplied to the negative input terminal 31 of the second amplifier circuit 30, and at the same time the signal output terminal 41 is supplied.
Is also supplied.
【0011】信号出力端子41にはスピーカ42が接続
され、第一の増幅回路の出力端子13に現れた出力電圧
EOが利得1の非反転増幅回路である緩衝増幅回路に供
給されるとその出力はEOとなるが、すでに前述したよ
うにスピーカの逆起電圧EBが発生し、信号出力端子4
1には下式に示すEO’が現れる。A speaker 42 is connected to the signal output terminal 41, and when the output voltage E O appearing at the output terminal 13 of the first amplifying circuit is supplied to a buffer amplifying circuit which is a non-inverting amplifying circuit having a gain of 1. The output becomes E O , but the counter electromotive voltage E B of the speaker is generated as described above, and the signal output terminal 4
Appears E O 'shown in the following formula to 1.
【0012】 EO’=EO+EB ・・・・・・・・・・・・・・・・・・・・・・・・・・・・(式1) EO’は第二の増幅回路30の負入力端子31に供給さ
れ、正入力端子32のEOとの差動入力と利得Bによっ
て以下に示す式の出力電圧−EBBが出力端子33に現
れる。E O '= E O + E B (Equation 1) E O ' is the second is supplied to the negative input terminal 31 of the amplifier circuit 30, the output voltage -E B B of the formula shown below by the differential input and the gain B of the E O of the positive input terminal 32 appears at the output terminal 33.
【0013】 {EO−(EO+EB)}B=−EBB ・・・・・・・(式2) この出力電圧は第一の増幅回路10の負の入力端子12
に供給され、信号入力端子40に供給された入力信号E
Iと共に差動入力され、利得A倍された出力が出力端子
13に現れる。即ちEOは以下の式により導出される。{E O − (E O + E B )} B = −E B B (Equation 2) This output voltage is the negative input terminal 12 of the first amplifier circuit 10.
The input signal E supplied to the signal input terminal 40
An output that is differentially input together with I and has a gain of A times appears at the output terminal 13. That is, E O is derived by the following equation.
【0014】 EO={EI−(−EBB)}A=AEI+ABEB ・・・・・・・・・・・(式3) いまAB=1となる第二の増幅回路の利得Bを求める
と、B=1/Aとなり、(式3)は(式4)の如く表さ
れる。E O = {E I − (− E B B)} A = AE I + ABE B (Equation 3) In the second amplifier circuit where AB = 1 now When the gain B is obtained, B = 1 / A, and (Equation 3) is expressed as (Equation 4).
【0015】 EO=AEI+EB ・・・・・・・・・・・・・・・・・・・・・・・・・・・・(式4) (式4)の電圧は緩衝増幅回路20の出力電圧にも同じ
電圧が現れる。E O = AE I + E B ... (Equation 4) The voltage of (Equation 4) is buffered. The same voltage appears in the output voltage of the amplifier circuit 20.
【0016】緩衝増幅回路20に現れたEBとスピーカ
に発生した逆起電圧EBとは同相同振幅であるため、そ
こにEBによる電圧差は発生せず、結局、入力信号EIを
第一の増幅回路でA倍に増幅したAEIがスピーカに流
れることになる。Since the E B appearing in the buffer amplifier circuit 20 and the counter electromotive voltage E B generated in the speaker have the same phase and the same amplitude, no voltage difference occurs due to the E B there, and eventually the input signal E I AE I amplified by A times in the first amplifier circuit flows to the speaker.
【0017】上述の説明は、緩衝増幅回路20の入出力
直線性が理想的な直線であるとして説明を行ったが、実
際にはある程度の非直線性を有している。このため、同
一の入出力直線性を有するもう一つの緩衝増幅回路を第
一の増幅回路の出力端子13と第二の増幅回路の正入力
端子32との間に挿入して(図示せず)、同相除去を第
二の増幅回路30で行うのが好ましい。Although the above description has been made assuming that the input / output linearity of the buffer amplifier circuit 20 is an ideal straight line, it actually has a certain degree of non-linearity. Therefore, another buffer amplifier circuit having the same input / output linearity is inserted between the output terminal 13 of the first amplifier circuit and the positive input terminal 32 of the second amplifier circuit (not shown). It is preferable that the common mode removal be performed by the second amplifier circuit 30.
【0018】図3は図1の説明図を実際の回路図で表し
たものである。図3において添付番号は図1と同じで、
利得を決める入出力抵抗の構成とその抵抗値を記してい
る。一般的な差動入力増幅回路の利得を決定する入出力
抵抗の構成と抵抗値は既に公知であり、利得Aを得るた
めには、それぞれの入力端子11および12からの入力
抵抗Rと、帰還抵抗ARと、分割抵抗ARとから構成さ
れる。一方、第二の増幅回路30の利得Bは前述の如く
B=1/Aであるため、第一の増幅回路で成したと同様
に、入力抵抗Rに対して、帰還抵抗がR/A、分割抵抗
がR/Aで構成することができる。FIG. 3 is an actual circuit diagram showing the explanatory diagram of FIG. In FIG. 3, the attached numbers are the same as those in FIG.
The configuration of the input / output resistance that determines the gain and its resistance value are described. The configuration and resistance value of the input / output resistors that determine the gain of a general differential input amplifier circuit are already known, and in order to obtain the gain A, the input resistors R from the respective input terminals 11 and 12 and the feedback It is composed of a resistor AR and a divided resistor AR. On the other hand, since the gain B of the second amplifier circuit 30 is B = 1 / A as described above, the feedback resistance is R / A with respect to the input resistance R, as in the first amplifier circuit. The dividing resistor can be composed of R / A.
【0019】また緩衝増幅回路20は図1では便宜上非
反転で利得が1の演算増幅器で記述したが、これにこだ
わることなく図3に示すように、たとえばコンプリメン
タリーのエミッタフォロワー回路を用いることができる
ことは言うまでもない。Although the buffer amplifier circuit 20 is described as an operational amplifier having a non-inversion and a gain of 1 in FIG. 1 for convenience, it is possible to use a complementary emitter follower circuit as shown in FIG. 3 without paying attention to this. It goes without saying that you can do it.
【0020】以上の説明で明らかな様に、この構成によ
って、電力増幅回路の出力には、第一の増幅回路の利
得、即ちA倍された入力信号と、スピーカの逆起電圧と
同相同振幅の電圧とが発生するため、スピーカの逆起電
圧による電位差は発生せず、入力信号成分のみがスピー
カに流れ原音に忠実な波形が再生される。また電流帰還
による方法と異なるため、周波数特性もスピーカのイン
ピーダンスとは無関係に平坦とすることができる効果が
ある。As is clear from the above description, according to this configuration, the output of the power amplifier circuit has the gain of the first amplifier circuit, that is, the input signal multiplied by A, and the same amplitude as the back electromotive force of the speaker. , The potential difference due to the back electromotive force of the speaker does not occur, and only the input signal component flows through the speaker and a waveform faithful to the original sound is reproduced. Further, since it is different from the method using current feedback, there is an effect that the frequency characteristic can be flattened regardless of the impedance of the speaker.
【0021】(実施例2)図2に本発明の第2の実施例
を説明するための説明図を示す。(Embodiment 2) FIG. 2 shows an explanatory view for explaining a second embodiment of the present invention.
【0022】図2は図1の構成要素と同じものは同一番
号で記しているため再度の説明は省略する。図1と図2
の相違点は、図1では第二の増幅回路30の正入力端子
32を第一の増幅回路10の出力端子13と接続してい
たのに対して、図2では第二の増幅回路30の正入力端
子32を信号入力端子40と接続していることである。In FIG. 2, the same elements as those of FIG. 1 are denoted by the same reference numerals, and therefore the repetitive description will be omitted. 1 and 2
1 is that the positive input terminal 32 of the second amplifier circuit 30 is connected to the output terminal 13 of the first amplifier circuit 10 in FIG. 1, whereas the second amplifier circuit 30 of FIG. That is, the positive input terminal 32 is connected to the signal input terminal 40.
【0023】また緩衝増幅回路20は特に必要ではない
ため、ここでは省略して第一の増幅回路10の出力端子
13は直接信号出力端子41に接続した。Since the buffer amplifier circuit 20 is not particularly necessary, it is omitted here and the output terminal 13 of the first amplifier circuit 10 is directly connected to the signal output terminal 41.
【0024】いま信号入力端子40から入った入力信号
EIは、第一の増幅回路10の正の入力端子11に供給
される一方、第二の増幅回路30の正入力端子32に供
給される。第一の増幅回路10の出力端子13に現れた
出力電圧EOは第二の増幅回路30の負入力端子31に
供給されると同時に信号出力端子41にも供給されてい
る。The input signal E I, which has just entered from the signal input terminal 40, is supplied to the positive input terminal 11 of the first amplifier circuit 10 and is supplied to the positive input terminal 32 of the second amplifier circuit 30. . The output voltage E O appearing at the output terminal 13 of the first amplifier circuit 10 is supplied to the negative input terminal 31 of the second amplifier circuit 30 and simultaneously to the signal output terminal 41.
【0025】信号出力端子41にはスピーカ42が接続
され、第一の増幅回路の出力端子13に現れた出力電圧
EOと、すでに前述したようにスピーカの逆起電圧EBと
が信号出力端子41に現れ、下式に示すEO’となる。A speaker 42 is connected to the signal output terminal 41, and the output voltage E O appearing at the output terminal 13 of the first amplifier circuit and the counter electromotive voltage E B of the speaker as described above are output to the signal output terminal. 41, and becomes E O 'shown in the following equation.
【0026】 EO’=EO+EB ・・・・・・・・・・・・・・・・・・・・・・・・・・・・(式5) EO’は第二の増幅回路30の負入力端子31に供給さ
れ、正入力端子32のEIとの差動入力と利得Bによっ
て以下に示す式の出力電圧が出力端子33に現れる。E O '= E O + E B (Equation 5) E O ' is the second The output voltage of the formula shown below appears at the output terminal 33, which is supplied to the negative input terminal 31 of the amplifier circuit 30 and is differentially input with E I of the positive input terminal 32 and the gain B.
【0027】 {EI−(EO+EB)}B ・・・・・・・・・・・・・・・・・・・・(式6) この出力電圧は第一の増幅回路10の負の入力端子12
に供給され、信号入力端子40に供給された入力信号E
Iと共に差動入力され、利得A倍された出力が出力端子
13に現れる。即ちEOは以下の式により導出される。{E I − (E O + E B )} B (Equation 6) This output voltage is the output voltage of the first amplifier circuit 10. Negative input terminal 12
The input signal E supplied to the signal input terminal 40
An output that is differentially input together with I and has a gain of A times appears at the output terminal 13. That is, E O is derived by the following equation.
【0028】 EO={EI−(EI−EO−EB)B}A EO=(A−AB)EI+ABEO+ABEB (1−AB)EO=(A−AB)EI+ABEB EO=(A−AB)EI/(1−AB)+ABEB/(1−AB) ・・・・・・・・・・・(式7) いまAB/(1−AB)=1となる第二の増幅回路の利
得Bを求めると、B=1/2Aとなり、(式7)は(式
8)の如く表される。E O = {E I − (E I −E O −E B ) B} A E O = (A−AB) E I + ABE O + ABE B (1-AB) E O = (A−AB) E I + ABE B E O = (A-AB) E I / (1-AB) + ABE B /(1-AB).....(Equation 7) Now AB / (1-AB) ) = 1, the gain B of the second amplifier circuit is obtained, and B = 1 / 2A, and (Equation 7) is expressed as (Equation 8).
【0029】 EO=(2A−1)EI+EB ・・・・・・・・・・・・・・・・・・(式8) (式8)の電圧は第一の増幅回路10の出力端子13に
現れ、スピーカに発生した逆起電圧EBとは同相同振幅
であるため、スピーカの逆起電圧による電位差は発生し
ないため、結局、入力信号EIを(2A−1)倍に増幅
した(2A−1)EIがスピーカに流れることになる。[0029] E O = (2A-1) E I + E B ·················· ( Equation 8) voltage first amplifier circuit (8) 10 It appears at the output terminal 13 of, for the counter-electromotive voltage E B generated in the speaker in phase the same amplitude, because the potential difference due to the counter electromotive voltage of the speaker does not occur, after all, the input signal E I (2A-1) times The amplified (2A-1) E I will flow to the speaker.
【0030】上述の説明は、第一の増幅回路10の入出
力直線性が理想的な直線であるとして説明を行ったが、
実際にはある程度の非直線性を有している。このため
に、第一の増幅回路と同一の入出力直線性を有し、非反
転で且つ利得Aを有する第三の増幅回路を、信号入力端
子40と第二の増幅回路の正入力端子32の間に挿入し
て(図示せず)非直線性の同相除去を第二の増幅回路3
0で行うのが好ましい。Although the above description has been made assuming that the input / output linearity of the first amplifier circuit 10 is an ideal straight line,
In reality, it has some non-linearity. To this end, a third amplifier circuit having the same input / output linearity as the first amplifier circuit, non-inverted, and having a gain A is connected to the signal input terminal 40 and the positive input terminal 32 of the second amplifier circuit. (Not shown) between the second amplification circuit 3 and the non-linear common-mode removal.
It is preferable to carry out at 0.
【0031】この時は前記で求めた電圧条件や、利得条
件が異なるため、以下に示す。第二の増幅回路の正入力
端子32の電圧がEIからAEIとなるため、第二の増幅
回路の出力端子に現れる出力電圧、即ち(式6)は(式
9)に示す如くなる。At this time, since the voltage condition and the gain condition obtained above are different, the following will be shown. Since the voltage of the positive input terminal 32 of the second amplifier circuit changes from E I to AE I , the output voltage appearing at the output terminal of the second amplifier circuit, that is, (Equation 6) is as shown in (Equation 9).
【0032】 {AEI−(EO+EB)}B ・・・・・・・・・・・・・・・・・・(式9) この電圧は第一の増幅回路の負の入力端子に供給され、
信号入力端子40のE Iと共にA倍に増幅される。従っ
て第一の増幅回路の出力電圧、即ちEOは(式10)に
示す如く導出される。{AEI-(EO+ EB)} B ···· (Equation 9) This voltage is supplied to the negative input terminal of the first amplifier circuit,
E of signal input terminal 40 IAmplifies with A times. Follow
Output voltage of the first amplifier circuit, that is, EOIn (Equation 10)
It is derived as shown.
【0033】 EO={EI−(AEI−EO−EB)B}A (1−AB)EO=(1−AB)AEI+ABEB EO=AEI+ABEB/(1−AB) ・・・・・・・・・・(式10) いま、AB/(1−AB)=1となる第二の増幅回路の
利得Bを求めると、B=1/2Aとなり、(式10)は
(式11)の如く表される。E O = {E I − (AE I −E O −E B ) B} A (1-AB) E O = (1−AB) AE I + ABE B E O = AE I + ABE B / (1 -AB) (Equation 10) Now, when the gain B of the second amplifier circuit with AB / (1-AB) = 1 is obtained, B = 1 / 2A, Formula 10) is expressed as Formula 11.
【0034】 EO=AEI+EB ・・・・・・・・・・・・・・・・・・・・・・・・・・・・(式11) (式11)の電圧は第一の増幅回路10の出力端子13
に現れ、スピーカに発生した逆起電圧EBとは同相同振
幅であるため、スピーカの逆起電圧による電位差は発生
しないため、結局、入力信号EIをA倍に増幅したAEI
がスピーカに流れることになる。E O = AE I + E B ... (Equation 11) The voltage of (Equation 11) is the first Output terminal 13 of one amplifier circuit 10
Appeared, for the counter-electromotive voltage E B generated in the speaker in phase the same amplitude, because the potential difference due to the counter electromotive voltage of the speaker does not occur, after all, the input signal E I was amplified A times AE I
Will flow into the speaker.
【0035】図4は図2の説明図を実際の回路図で表し
たものである。図4において添付番号は図1と同じで、
利得を決める入出力抵抗の構成とその抵抗値を記してい
る。一般的な差動入力増幅回路の利得を決定する入出力
抵抗の構成と抵抗値は既に公知であり、利得Aを得るた
めには、それぞれの入力端子11および12からの入力
抵抗Rと、帰還抵抗ARと、分割抵抗ARとから構成さ
れる。一方、第二の増幅回路30の利得Bは前述の如く
B=1/2Aであるため、第一の増幅回路で成したと同
様に、入力抵抗Rに対して、帰還抵抗がR/2A、分割
抵抗がR/2Aで構成することができる。FIG. 4 is an actual circuit diagram showing the explanatory diagram of FIG. In FIG. 4, the attached numbers are the same as in FIG.
The configuration of the input / output resistance that determines the gain and its resistance value are described. The configuration and resistance value of the input / output resistance that determines the gain of a general differential input amplifier circuit are already known, and in order to obtain the gain A, the input resistance R from each of the input terminals 11 and 12 and the feedback It is composed of a resistor AR and a divided resistor AR. On the other hand, since the gain B of the second amplifier circuit 30 is B = 1 / 2A as described above, the feedback resistance is R / 2A with respect to the input resistance R as in the first amplifier circuit. The dividing resistor can be composed of R / 2A.
【0036】本発明の実施例1および2において、図3
および図4の回路図を便宜上すべて演算増幅回路で記述
したが、これに限定されるものではない。In Embodiments 1 and 2 of the present invention, FIG.
Further, although the circuit diagram of FIG. 4 is described as an operational amplifier circuit for convenience, the present invention is not limited to this.
【0037】以上の説明で明らかな様に、実施例1の構
成より簡単な構成で、電力増幅回路の出力には、(2A
−1)倍の入力信号と、スピーカの逆起電圧と同相同振
幅の電圧とが発生するため、スピーカの逆起電圧による
電位差は発生しないため、入力信号成分のみがスピーカ
に流れ原音に忠実な波形が再生される。また電流帰還に
よる方法と異なるため、周波数特性もスピーカのインピ
ーダンスとは無関係に平坦とすることができる効果があ
る。As is apparent from the above description, the output of the power amplifier circuit is (2A
-1) times the input signal and a voltage with the same amplitude as the back electromotive force of the speaker are generated, so there is no potential difference due to the back electromotive force of the speaker, so only the input signal component flows to the speaker and the original sound is faithful. The waveform is played. Further, since it is different from the method using current feedback, there is an effect that the frequency characteristic can be flattened regardless of the impedance of the speaker.
【0038】[0038]
【発明の効果】以上のように本発明はスピーカが発生す
る逆起電圧を検知して、それと同相同振幅の信号を発生
させ、両信号間に電位差を生じさせなくして信号成分の
みをスピーカに伝えるため、原音に忠実な波形が再生さ
れる。As described above, the present invention detects a back electromotive force generated by a speaker, generates a signal having the same phase and the same amplitude as that of the back electromotive force, does not generate a potential difference between the two signals, and outputs only the signal component to the speaker. To convey, a waveform faithful to the original sound is reproduced.
【0039】また逆起電圧の抑制を電流帰還で行わない
ため、周波数特性もスピーカのインピーダンスとは無関
係になり、第一の増幅回路10の周波数特性並みの平担
性を得ることができる効果がある。またスピーカの振幅
が大きくなる低音域では逆起電圧による影響が大きくな
るが、この影響を阻止することによって大電力を投入し
質の良い低音を伸ばすことができる。即ち再生音を明瞭
繊細にし、低音も伸びた良い音を得る効果がある。Further, since the counter electromotive voltage is not suppressed by the current feedback, the frequency characteristic is independent of the impedance of the speaker, and the flatness equivalent to the frequency characteristic of the first amplifier circuit 10 can be obtained. is there. Further, in the low sound range where the amplitude of the speaker becomes large, the influence of the back electromotive force becomes large, but by preventing this influence, a large amount of electric power can be supplied and a good bass can be extended. That is, there is an effect that the reproduced sound is made clear and delicate, and a good sound with extended low tone is obtained.
【図1】本発明の第1の実施例の動作原理を説明するた
めの説明図FIG. 1 is an explanatory diagram for explaining an operation principle of a first embodiment of the present invention.
【図2】本発明の第2の実施例の動作原理を説明するた
めの説明図FIG. 2 is an explanatory diagram for explaining the operation principle of the second embodiment of the present invention.
【図3】本発明の第1の実施例における電力増幅回路の
回路図FIG. 3 is a circuit diagram of a power amplifier circuit according to a first embodiment of the present invention.
【図4】本発明の第2の実施例における電力増幅回路の
回路図FIG. 4 is a circuit diagram of a power amplifier circuit according to a second embodiment of the present invention.
【図5】従来例における電流帰還増幅回路の構成図FIG. 5 is a configuration diagram of a current feedback amplifier circuit in a conventional example.
1 電力増幅回路 10 第一の増幅回路 20 緩衝増幅回路 30 第二の増幅回路 42 スピーカ 1 Power Amplifier Circuit 10 First Amplifier Circuit 20 Buffer Amplifier Circuit 30 Second Amplifier Circuit 42 Speaker
Claims (2)
路と緩衝増幅回路より構成され、前記第一の増幅回路の
正の入力端子は信号入力端子に接続され、前記第一の増
幅回路の出力は前記第二の増幅回路の正入力端子と前記
緩衝増幅回路の正入力端子に接続され、前記第二の増幅
回路の出力は前記第一の増幅回路の負の入力端子に接続
され、前記緩衝増幅回路の出力が前記第二の増幅回路の
負入力端子と信号出力端子に接続してなる電力増幅回
路。1. A first and second amplification circuit having differential inputs and a buffer amplification circuit, wherein a positive input terminal of the first amplification circuit is connected to a signal input terminal, and the first amplification circuit is connected. The output of the circuit is connected to the positive input terminal of the second amplifier circuit and the positive input terminal of the buffer amplifier circuit, and the output of the second amplifier circuit is connected to the negative input terminal of the first amplifier circuit. A power amplifier circuit in which an output of the buffer amplifier circuit is connected to a negative input terminal and a signal output terminal of the second amplifier circuit.
路より構成され、前記第一の増幅回路の正の入力端子と
第二の増幅回路の正入力端子とを信号入力端子に接続す
ると共に、前記第二の増幅回路の出力を前記第一の増幅
回路の負の入力端子に接続し、前記第一の増幅回路の出
力を前記第二の増幅回路の負入力端子および信号出力端
子に接続してなる電力増幅回路。2. A first and a second amplifier circuit having a differential input, wherein a positive input terminal of the first amplifier circuit and a positive input terminal of the second amplifier circuit are connected to a signal input terminal. The output of the second amplifier circuit is connected to the negative input terminal of the first amplifier circuit, and the output of the first amplifier circuit is connected to the negative input terminal and the signal output terminal of the second amplifier circuit. Power amplifier circuit connected to.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6287842A JPH08148948A (en) | 1994-11-22 | 1994-11-22 | Power amplifier circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6287842A JPH08148948A (en) | 1994-11-22 | 1994-11-22 | Power amplifier circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08148948A true JPH08148948A (en) | 1996-06-07 |
Family
ID=17722486
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6287842A Pending JPH08148948A (en) | 1994-11-22 | 1994-11-22 | Power amplifier circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08148948A (en) |
-
1994
- 1994-11-22 JP JP6287842A patent/JPH08148948A/en active Pending
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