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JPH08139265A - Molded package for semiconductor device - Google Patents

Molded package for semiconductor device

Info

Publication number
JPH08139265A
JPH08139265A JP6302769A JP30276994A JPH08139265A JP H08139265 A JPH08139265 A JP H08139265A JP 6302769 A JP6302769 A JP 6302769A JP 30276994 A JP30276994 A JP 30276994A JP H08139265 A JPH08139265 A JP H08139265A
Authority
JP
Japan
Prior art keywords
resin
lead
external lead
semiconductor element
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6302769A
Other languages
Japanese (ja)
Other versions
JP2655501B2 (en
Inventor
Osamu Sato
佐藤  修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6302769A priority Critical patent/JP2655501B2/en
Publication of JPH08139265A publication Critical patent/JPH08139265A/en
Application granted granted Critical
Publication of JP2655501B2 publication Critical patent/JP2655501B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To provide a package which enables matching of characteristic imped ance of an outside lead-out lead and is excellent in transmission characteristic of a high frequency signal, relating to a mold package for a semiconductor device which seals a semiconductor element by resin. CONSTITUTION: After a semiconductor element 1 and a first outside lead-out lead 2 whereto an electrode thereof is connected are sealed by first resin 3, a second outside lead-out lead 4 forming a metallic layer for forming a conductive layer is mounted on the first resin 3. Thereafter, the first resin 3 and the second outside lead-out lead 4 are sealed by second resin 5. A second outside lead-out lead is grounded, and a thickness of the first resin 3 and a signal line width of a first outside lead-out lead are optimized for enabling matching of impedance.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置用モールド
パッケージに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mold package for a semiconductor device.

【0002】[0002]

【従来の技術】従来の半導体装置用モールドパッケージ
は、図7に示すように半導体素子(61)及び外部導出
リード(62)とが一つの樹脂(63)によりモールド
されている。このような構造の半導体装置用モールドパ
ッケージは、安価に大量に生産することが可能なため、
民生用の半導体装置用モールドパッケージとして最も一
般的に使用されている。
2. Description of the Related Art In a conventional mold package for a semiconductor device, as shown in FIG. 7, a semiconductor element (61) and an external lead (62) are molded with one resin (63). Since a semiconductor device mold package having such a structure can be mass-produced at low cost,
It is most commonly used as a mold package for consumer semiconductor devices.

【0003】一方、通信用半導体装置や産業用半導体装
置など特に高い周波数で使用される半導体装置には、そ
の半導体素子の高周波特性を生かすために、信号線路の
特性インピーダンスを考慮したセラミックス製のパッケ
ージが使われている。ところが近年、衛星放送や携帯電
話など民生用の電子機器においても数百MHzから数G
Hzという非常に高い周波数が使われるようになってき
ているため、これらの電子機器に使用される半導体装置
に対しても安価で、なおかつ高周波特性に優れたものが
要求されるようになってきている。
On the other hand, semiconductor devices used at particularly high frequencies, such as communication semiconductor devices and industrial semiconductor devices, are provided with ceramic packages in consideration of the characteristic impedance of signal lines in order to make use of the high-frequency characteristics of the semiconductor elements. Is used. However, in recent years, consumer electronic devices such as satellite broadcasts and mobile phones have been developed to have several hundred MHz to several G
Since a very high frequency of Hz is used, semiconductor devices used in these electronic devices are required to be inexpensive and have excellent high frequency characteristics. There is.

【0004】これに対して、従来のモールドパッケージ
は、価格は安くできるものの信号線路のインピーダンス
整合が取れていないために、数百MHz以上の高周波信
号の伝達特性が悪く半導体素子の高周波特性を減じてし
まうという欠点がある。また、高周波信号の伝達特性に
優れたセラミックスパッケージは、モールドパッケージ
に比べ価格が数十倍から数百倍もするため、民生用半導
体装置には適さないという欠点があった。
On the other hand, in the conventional molded package, although the cost can be reduced, the impedance of the signal line is not matched, so that the transmission characteristic of a high frequency signal of several hundred MHz or more is poor and the high frequency characteristic of the semiconductor element is reduced. There is a disadvantage that it will. Further, the price of a ceramic package having excellent high-frequency signal transmission characteristics is several tens to several hundreds of times that of a molded package, and thus it is not suitable for consumer semiconductor devices.

【0005】これらの欠点を解決するため従来から、モ
ールドパッケージにおいてインピーダンスの整合が取れ
る方法が考えられている。例えば、特開平1−2028
53(以下従来例1という)、実開昭63−12475
9(以下従来例2という)、特開平2−119166
(以下従来例3という)などである。従来例1〜3につ
いて図8〜図10で説明する。
[0005] In order to solve these drawbacks, a method for matching impedance in a mold package has been proposed. For example, Japanese Patent Laid-Open No. 1-2028
53 (hereinafter referred to as the conventional example 1), Sekikai 63-12475
9 (hereinafter referred to as Conventional Example 2), JP-A-2-119166.
(Hereinafter referred to as Conventional Example 3). Conventional examples 1 to 3 will be described with reference to FIGS.

【0006】図8は、従来例1において提案された高周
波用モールドパッケージの平面から見た断面図である。
この従来例1では、信号用リード(72)と接地用リー
ド(71)が、それぞれの露出リード部で構成された分
布定数線路の特性インピーダンスと、非露出リード部で
構成された分布定数線路の特性インピーダンスが一致す
るように、信号用リードの幅(a1、a2)および信号
用リードと接地用リードとの相互間隔(w1、w2)を
設定している。
FIG. 8 is a sectional view of a high-frequency mold package proposed in Conventional Example 1 as viewed from the top.
In the first conventional example, the signal lead (72) and the grounding lead (71) are formed by the characteristic impedance of the distributed constant line constituted by the respective exposed leads and the characteristic impedance of the distributed constant line constituted by the non-exposed leads. The width (a1, a2) of the signal lead and the mutual interval (w1, w2) between the signal lead and the ground lead are set so that the characteristic impedances match.

【0007】図9は、従来例2において提案されたモー
ルドパッケージの断面図である。この従来例2では、半
導体素子に接続された外部導出リード(82)に絶縁性
接着用樹脂(82)を介して接地層(83)を並設して
いるものである。図10は、従来例3において提案され
たモールドパッケージの断面図である。この従来例3で
は、半導体素子を搭載するアイランドと一体を成す金属
からなる一外部導出リード(98)とこのリードと独立
の少なくとも一つの他の外部導出リードとが共に半導体
素子を囲んでシールドする金属シールド部材(91)を
有しているものである。
FIG. 9 is a sectional view of a mold package proposed in the conventional example 2. As shown in FIG. In the second conventional example, a ground layer (83) is juxtaposed with an external lead (82) connected to a semiconductor element via an insulating adhesive resin (82). FIG. 10 is a cross-sectional view of the mold package proposed in Conventional Example 3. In the third conventional example, one external lead-out lead (98) made of metal and integrated with an island on which a semiconductor element is mounted, and at least one other lead-out lead independent of this lead both surround and shield the semiconductor element. It has a metal shield member (91).

【0008】[0008]

【発明が解決しようとする課題】上記従来技術には、次
のような課題がある。従来例1の高周波用モールドパッ
ケージは、隣接するリードの幅と間隔を最適化すること
によって、信号用リードのインピーダンスを整合しよう
としているが、通常信号用リードとインピーダンスの整
合をとるために必要な対向する接地用リードの幅は、信
号用リードの幅の3倍以上が必要であり、限られたパッ
ケージの大きさではその効果が十分ではない。また、常
に信号用リードと接地用リードとを隣接させる必要があ
るために半導体素子の電極配置の制約を受けるという欠
点がある。
The above-mentioned conventional techniques have the following problems. The high-frequency mold package of Conventional Example 1 attempts to match the impedance of signal leads by optimizing the width and spacing of adjacent leads, but usually requires impedance matching with signal leads. The width of the opposing ground lead must be at least three times the width of the signal lead, and the effect is not sufficient with a limited package size. Further, there is a drawback that the electrode arrangement of the semiconductor element is restricted because the signal lead and the grounding lead always have to be adjacent to each other.

【0009】また、従来例2の半導体装置の構造は、隣
接するリード間の信号伝達の相互干渉(いわゆるクロス
トーク)を少なくする効果が得られると共に絶縁性接着
用樹脂厚と信号用リードとなる外部導出リードの幅を最
適化することにより、特性インピーダンスの整合も可能
になるというものである。しかしながら、その製造工程
において、リードフレームに個片の接着性のある絶縁性
樹脂を貼り、さらに個片の接地層、すなわち金属板を貼
るために並設リードと接地層との間に位置ズレを生じ易
いという欠点がある。さらに、リードフレームに絶縁性
接着用樹脂を貼るという通常の樹脂封止型半導体装置の
製造工程とは全く異なる工程を経るためにコストが高く
なるという欠点がある。
Further, the structure of the semiconductor device of the prior art example 2 has the effect of reducing the mutual interference (so-called crosstalk) of signal transmission between adjacent leads, and has the thickness of the insulating adhesive resin and the signal leads. By optimizing the width of the external lead, matching of the characteristic impedance becomes possible. However, in the manufacturing process, a piece of adhesive insulating resin is adhered to the lead frame, and furthermore, a positional shift is caused between the juxtaposed leads and the ground layer in order to attach the individual ground layer, that is, a metal plate. There is a disadvantage that it is easy to occur. Further, there is a drawback that the cost is high because the process is completely different from the usual process of manufacturing a resin-encapsulated semiconductor device in which an insulating resin is attached to a lead frame.

【0010】また、従来例3の半導体装置では、金属シ
ールド部材をリードフレーム上に載置してからモールド
するため、金属シールド部材の位置ズレを生じ易いとい
う欠点がある。さらに、この構造は外部に導出するリー
ドが増えると金属シールド部材の形状が複雑になるため
コストが大幅に上昇してしまうという欠点がある。
In the semiconductor device of Conventional Example 3, since the metal shield member is mounted on the lead frame and then molded, there is a disadvantage that the metal shield member is likely to be displaced. Further, this structure has a disadvantage that the cost is greatly increased because the shape of the metal shield member becomes complicated as the number of leads led out increases.

【0011】[0011]

【課題を解決するための手段】本発明は、半導体素子を
樹脂により封止する半導体装置用モールドパッケージに
おいて、半導体素子及び該半導体素子の電極と接続され
た第1の外部導出リードとが第1の樹脂によりモールド
され、前記第1の樹脂上の前記第1の外部導出リードが
封入された部分に導電層を形成するための金属層を有
し、該金属層は第2の外部導出リードをなすようにして
第1の樹脂及び金属層を含む部分が第2の樹脂によりモ
ールドされていることを特徴とする半導体装置用モール
ドパッケージである。また本発明は、第1の外部導出リ
ードが櫛状に第1の樹脂によりモールドされ、第2の外
部導出リードが同軸に近い断面構造に形成されているこ
とを特徴とする半導体装置用モールドパッケージであ
る。
According to the present invention, in a semiconductor device mold package for encapsulating a semiconductor element with a resin, a semiconductor element and a first external lead connected to an electrode of the semiconductor element are first. And a metal layer for forming a conductive layer on a portion of the first resin in which the first outer lead is encapsulated, the metal layer forming a second outer lead. A molded package for a semiconductor device, characterized in that the portion including the first resin and the metal layer is molded with the second resin as described above. According to the present invention, there is provided a mold package for a semiconductor device, wherein a first external lead is molded in a comb shape with a first resin, and a second external lead is formed in a cross-sectional structure close to coaxial. It is.

【0012】[0012]

【作用】本発明においては、信号用リードのインピーダ
ンスを整合することができるもので、具体的には第2の
外部導出リードをグランドし、第1の樹脂の厚さと第1
の外部導出リードの信号線路幅とを最適化することによ
り特性インピーダンスを整合させることができるもので
ある。また、第2の外部導出リードの形状を工夫するこ
とにより隣接リード間のクロストークをほとんど消去で
きるものである。即ち、二重モールド構造として一次モ
ールド後に、第二のリードフレームを重ねて二次モール
ドし、この際一次モールド厚、二次モールド厚を最適化
することによりインピーダンス整合が可能となるもので
ある。
In the present invention, the impedance of the signal lead can be matched. Specifically, the second external lead is grounded, and the thickness of the first resin and the first
The characteristic impedance can be matched by optimizing the signal line width of the external lead. Also, by devising the shape of the second external lead, crosstalk between adjacent leads can be almost eliminated. That is, as a double mold structure, after the primary molding, the second lead frame is overlaid and the secondary molding is performed, and the impedance matching is possible by optimizing the primary mold thickness and the secondary mold thickness.

【0013】[0013]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。 [実施例1]図1は、本発明の第1の実施例のモールド
パッケージの構造を示す断面図であり、図2及び図3
は、本発明の第1の実施例のモールドパッケージの製法
を示す工程図である。図1に示すように、本発明のモー
ルドパッケージは、半導体素子(1)の電極と接続され
る第1の外部導出リード(2)が第1の樹脂(3)によ
り一次モールドされ、一次モールド上に金属層が第2の
外部導出リード(4)を成すように載置され、第1及び
第2の外部導出リードが一次モールドと共に第2の樹脂
(5)により二次モールドされている。
Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a sectional view showing the structure of a mold package according to a first embodiment of the present invention.
FIG. 3 is a process chart showing a method for manufacturing a mold package according to the first embodiment of the present invention. As shown in FIG. 1, in the mold package of the present invention, a first external lead-out (2) connected to an electrode of a semiconductor element (1) is primarily molded with a first resin (3), and is formed on a first mold. A metal layer is placed on the second resin layer so as to form a second external lead (4), and the first and second external leads are secondarily molded with the first resin and the second resin (5).

【0014】このモールドパッケージの製法について、
図2(a)(b)及び図3(c)(d)で説明する。図
2(a)に示すように、本発明のモールドパッケージに
おいても、通常の樹脂封止型半導体装置と同様に、第1
のリードフレームのアイランド(22)上に半導体素子
(1)を載置し、半導体素子(1)の電極と外部導出リ
ード(2)とを金属細線(23)により接続する。次
に、図2(b)に示すように、半導体素子及び金属細線
部分を含む箇所を第1の樹脂(3)により封止する。
Regarding the manufacturing method of this mold package,
This will be described with reference to FIGS. 2A and 2B and FIGS. 3C and 3D. As shown in FIG. 2A, also in the mold package of the present invention, as in the case of a normal resin-sealed semiconductor device, the first package is used.
The semiconductor element (1) is mounted on the island (22) of the lead frame, and the electrode of the semiconductor element (1) and the external lead (2) are connected by the thin metal wire (23). Next, as shown in FIG. 2B, a portion including the semiconductor element and the thin metal wire portion is sealed with a first resin (3).

【0015】次に、図3(c)に示すように、この第1
の樹脂(3)上に金属層を成す第2の外部導出リード
(4)を載置する。次に、図3(d)に示すように、第
1の樹脂および第2の外部導出リード(4)を含む箇所
を第2の樹脂(5)により封止する。本発明のモールド
パッケージでは、第2の外部導出リードを接地すること
により第1の外部導出リードの特性インピーダンスを整
合することが容易となる。
Next, as shown in FIG.
A second external lead (4) forming a metal layer is placed on the resin (3). Next, as shown in FIG. 3D, the portion including the first resin and the second external lead (4) is sealed with the second resin (5). In the molded package of the present invention, by grounding the second external lead, it is easy to match the characteristic impedance of the first external lead.

【0016】このような構造における、信号用リードの
特性インピーダンス(Z)は、信号用リードの幅を
(w)、樹脂の厚さ(すなわち信号用リードと接地用リ
ードとの間隔)を(h)、樹脂の比誘電を(ε)とし
た場合、[数1]と表されるから、例えば50Ωの特性
インピーダンスを得たい場合、樹脂のε=4.0とす
ると第1の樹脂のモール厚さと第1の外部導出リードの
信号線路幅との比を1:2とすればよい。
In such a structure, the characteristic impedance (Z) of the signal lead is such that the width of the signal lead is (w) and the thickness of the resin (ie, the distance between the signal lead and the ground lead) is (h). ), When the relative dielectric constant of the resin is (ε r ), it is expressed by [Equation 1]. For example, when it is desired to obtain a characteristic impedance of 50Ω, when ε r = 4.0 of the resin, The ratio between the molding thickness and the signal line width of the first external lead may be 1: 2.

【数1】 [Equation 1]

【0017】本発明のモールドパッケージの構造は、イ
ンピーダンスの整合を第2の外部導出リードを成す接地
層を設けることにより行うため、その信号線路に対向す
る接地層の幅を充分にとることができるためにインピー
ダンス整合の効果が大きくなると共に半導体素子の電極
配置の制約を受けることがないという長所がある。さら
に、第1の樹脂封止、第2の外部導出リード載置、第2
の樹脂封止までの工程はいずれも第1のリードフレーム
の位置決め穴を基準として行うため、第2の外部導出リ
ードのズレが起きる心配はない。また外部導出リードの
数が増えてもコストが上昇することもないという長所が
ある。
In the structure of the molded package of the present invention, impedance matching is performed by providing a ground layer constituting the second external lead, so that the width of the ground layer facing the signal line can be made sufficiently large. Therefore, there is an advantage that the effect of impedance matching is increased and the arrangement of electrodes of the semiconductor element is not restricted. Furthermore, the first resin sealing, the second external lead placement, the second
Since the steps up to the resin sealing are all performed with reference to the positioning holes of the first lead frame, there is no fear that the second lead-out leads are displaced. Also, there is an advantage that the cost does not increase even if the number of externally derived leads increases.

【0018】[実施例2]つぎに、本発明の第2の実施
例について、図4〜図6で説明する。図4は本発明の第
2の実施例のモールドパッケージの第1の樹脂の形状を
示す図、図5は第2の実施例の外部導出リードの形状を
示す図であり、図6(a)は、本発明の第2の実施例の
モールドパッケージの構造を示す上面図、図6(b)
は、図6(a)のX−X´断面図である。この実施例の
モールドパッケージは、図4に示すように半導体素子の
電極と接続される第1の外部導出リード(32)が第1
の樹脂(33)により一次モールドされるもので、第1
の外部導出リード(32)が図4に示す形状の第1の樹
脂(33)により封止されている。即ち、第1の外部導
出リード(32)の部分に櫛状に第1の樹脂(33)に
より封止されているものである。
[Embodiment 2] Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a diagram showing the shape of the first resin of the mold package according to the second embodiment of the present invention, and FIG. 5 is a diagram showing the shape of the external lead-out lead of the second embodiment. FIG. 6B is a top view showing the structure of the mold package according to the second embodiment of the present invention, and FIG.
FIG. 7 is a sectional view taken along line XX ′ in FIG. In the mold package of this embodiment, as shown in FIG. 4, a first external lead (32) connected to an electrode of a semiconductor element has a first configuration.
The first molding is performed by using the resin (33).
Are lead-out leads (32) are sealed with a first resin (33) having the shape shown in FIG. That is, the first external lead (32) is sealed in a comb shape with the first resin (33).

【0019】一次モールドである第1の樹脂(33)上
に金属層が第2の外部導出リードを成すように載置され
るが、その第2の外部導出リード(接地)となるリード
フレームを、図5(a)及び図5(b)に示すものであ
る。即ち、図5(a)の第2の外部導出リードA(3
4)は、第1の外部導出リードの部分に櫛状になってい
る第1の樹脂に対応するようにコの字状に形成され、第
2の外部導出リードB(35)は図5(b)のようにな
っているものである。そして、第2の外部導出リード
(接地)となるリードフレームを、図5(a)の第2の
外部導出リードA(34)及び図5(b)の第2の外部
導出リードB(35)を載置して、図6(a)に示すよ
うに第2の樹脂(36)により封止する。
A metal layer is placed on a first resin (33), which is a primary mold, so as to form a second lead-out lead. 5 (a) and 5 (b). That is, the second external lead A (3) shown in FIG.
4) is formed in a U-shape so as to correspond to the first resin which is in the shape of a comb at the first external lead, and the second external lead B (35) is shown in FIG. b). The lead frame serving as the second external lead (ground) is connected to the second external lead A (34) in FIG. 5A and the second external lead B (35) in FIG. 5B. Is mounted and sealed with a second resin (36) as shown in FIG.

【0020】図6(b)は、図6(a)のX−X´断面
図である。第1の外部導出リード(32)が第1の樹脂
(33)により封止され、第1の樹脂(33)上にコの
字状に形成されている第2の外部導出リードA(34)
と第2の外部導出リードB(35)を設け、第2の樹脂
(36)により封止されているものである。このような
構造とすることにより信号用リード周辺の断面構造とし
て同軸に近い構造を実現できるため、第1の外部導出リ
ードの特性インピーダンスの整合が容易にできると共に
隣接リード間のクロストークをほとんど消去することが
できる。
FIG. 6 (b) is a sectional view taken along line XX 'of FIG. 6 (a). The first external lead A (34) is formed by sealing the first external lead (32) with the first resin (33) and forming a U-shape on the first resin (33).
And a second external lead B (35), which is sealed with a second resin (36). By adopting such a structure, a structure close to coaxial as a cross-sectional structure around the signal lead can be realized, so that the characteristic impedance of the first external lead can be easily matched and crosstalk between adjacent leads can be almost eliminated. can do.

【0021】[0021]

【発明の効果】以上説明したように、本発明の半導体装
置用モールドパッケージによれば、信号用リードのイン
ピーダンスを整合することができると共に外部導出リー
ドの数が増えてもコストが上昇することもないという長
所がある。さらに第2の外部導出リードの形状を工夫す
ることにより隣接リード間のクロストークをほとんど消
去できる効果を奏するものである。
As described above, according to the mold package for a semiconductor device of the present invention, the impedance of the signal leads can be matched and the cost can be increased even if the number of external leads is increased. There is an advantage that there is no. Further, by devising the shape of the second external lead, it is possible to substantially eliminate the crosstalk between adjacent leads.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の第1の実施例のモールドパッケージ
の構造を示す断面図
FIG. 1 is a sectional view showing a structure of a mold package according to a first embodiment of the present invention.

【図2】 [図1]のモールドパッケージの製法の工程
(a)(b)を示す図
FIG. 2 is a view showing steps (a) and (b) of the method for manufacturing a mold package of FIG. 1;

【図3】 [図1]のモールドパッケージの製法の工程
(c)(d)を示す図
FIG. 3 is a diagram showing steps (c) and (d) of the manufacturing method of the mold package of FIG.

【図4】 本発明の第2の実施例のモールドパッケージ
の第1の樹脂の形状を示す図
FIG. 4 is a diagram showing a shape of a first resin of a mold package according to a second embodiment of the present invention.

【図5】 本発明の第2の実施例の外部導出リードの形
状を示す図
FIG. 5 is a view showing a shape of an external lead-out according to a second embodiment of the present invention.

【図6】 (a)は、本発明の第2の実施例のモールド
パッケージの構造を示す上面図、(b)は、図6(a)
のX−X´断面図
6A is a top view showing the structure of the mold package of the second embodiment of the present invention, and FIG. 6B is the same as FIG. 6A.
XX ′ sectional view of

【図7】 従来の半導体装置用モールドパッケージの構
造を示す断面図
FIG. 7 is a sectional view showing the structure of a conventional semiconductor device mold package.

【図8】 従来例1のモールドパッケージの平面から見
た断面図
FIG. 8 is a sectional view of the mold package of Conventional Example 1 as seen from a plane.

【図9】 従来例2のモールドパッケージの断面図FIG. 9 is a cross-sectional view of a mold package of Conventional Example 2.

【図10】 従来例3のモールドパッケージの断面図FIG. 10 is a sectional view of a mold package of Conventional Example 3;

【符号の説明】[Explanation of symbols]

1 半導体素子 2,32 第1の外部導出リード 3,33 第1の樹脂 4 第2の外部導出リード 5,36 第2の樹脂 22 アイランド 23 金属細線 34 第2の外部導出リードA 35 第2の外部導出リードB 62,82,92 外部導出リード 63 樹脂 71 接地用リード 72 信号用リード 81 絶縁性接着用樹脂 83 接地層 91 金属シールド部材 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2, 32 First external lead 3, 33 First resin 4 Second external lead 5, 36 Second resin 22 Island 23 Fine metal wire 34 Second external lead A 35 Second Outer lead B 62, 82, 92 Outer lead 63 Resin 71 Ground lead 72 Signal lead 81 Insulating adhesive resin 83 Ground layer 91 Metal shield member

フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/31 Continuation of front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01L 23/31

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を樹脂により封止する半導体
装置用モールドパッケージにおいて、半導体素子及び該
半導体素子の電極と接続された第1の外部導出リードと
が第1の樹脂によりモールドされ、前記第1の樹脂上の
前記第1の外部導出リードが封入された部分に導電層を
形成するための金属層を有し、該金属層は第2の外部導
出リードをなすようにして第1の樹脂及び金属層を含む
部分が第2の樹脂によりモールドされていることを特徴
とする半導体装置用モールドパッケージ。
1. A semiconductor device mold package for sealing a semiconductor element with a resin, wherein the semiconductor element and a first external lead connected to an electrode of the semiconductor element are molded with a first resin, There is a metal layer for forming a conductive layer on a portion of the first resin in which the first external lead is enclosed, and the metal layer forms a second external lead so that the first resin is formed. And a mold package for a semiconductor device, wherein a portion including the metal layer is molded with the second resin.
【請求項2】 第1の外部導出リードが櫛状に第1の樹
脂によりモールドされ、第2の外部導出リードが同軸に
近い断面構造に形成されていることを特徴とする請求項
1に記載の半導体装置用モールドパッケージ。
2. The first external lead-out is molded in a comb shape with the first resin, and the second external lead-out is formed to have a cross-sectional structure close to a coaxial shape. Molded package for semiconductor devices.
JP6302769A 1994-11-11 1994-11-11 Mold package for semiconductor device Expired - Fee Related JP2655501B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6302769A JP2655501B2 (en) 1994-11-11 1994-11-11 Mold package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6302769A JP2655501B2 (en) 1994-11-11 1994-11-11 Mold package for semiconductor device

Publications (2)

Publication Number Publication Date
JPH08139265A true JPH08139265A (en) 1996-05-31
JP2655501B2 JP2655501B2 (en) 1997-09-24

Family

ID=17912917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6302769A Expired - Fee Related JP2655501B2 (en) 1994-11-11 1994-11-11 Mold package for semiconductor device

Country Status (1)

Country Link
JP (1) JP2655501B2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63147835U (en) * 1987-03-18 1988-09-29
JPH02208959A (en) * 1989-02-08 1990-08-20 Mitsubishi Electric Corp Semiconductor device
JPH03248455A (en) * 1990-02-26 1991-11-06 Nec Corp Lead frame

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63147835U (en) * 1987-03-18 1988-09-29
JPH02208959A (en) * 1989-02-08 1990-08-20 Mitsubishi Electric Corp Semiconductor device
JPH03248455A (en) * 1990-02-26 1991-11-06 Nec Corp Lead frame

Also Published As

Publication number Publication date
JP2655501B2 (en) 1997-09-24

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