JPH08130742A - Image decoding device - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the cost by reducing the memory required for the decoding process. [Structure] Inputted I and P pictures are stored in a memory 22. When decoding a B picture, the block necessary for this decoding is detected by the motion compensation circuit 38, and only the data of this block is read from the memory 22 and decoded. When decoding a B picture, the forward reference image is stored in the frame memory 11, and the backward reference image is stored in the block buffer 37. The reference image data of the block buffer 37 is sequentially updated according to the decoding process of the B picture. As a result, the block buffer 37 that stores pixel data of up to four blocks can be used as a memory that stores the backward reference image for decoding the B picture.

Description

Detailed Description of the Invention

[Object of the Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding apparatus for decoding coded data including bidirectional predictive coded data.

[0002]

2. Description of the Related Art In recent years, digital processing of images has become popular with the establishment of high-efficiency image coding technology. The high-efficiency coding technique is for coding image data at a low bit rate in order to improve the efficiency of digital transmission and recording. In this high efficiency coding,
Orthogonal transformation such as DCT (discrete cosine transformation) processing is performed in block units of m × n pixels. Orthogonal transformation is to transform an input sample value into an orthogonal component such as a spatial frequency component. This makes it possible to reduce spatial correlation components. The orthogonally transformed components are quantized to reduce the redundancy of the signal of the block.

Further, variable length coding such as Huffman coding is applied to the quantized output to further reduce the data amount. Huffman coding performs coding based on the result calculated from the statistical code amount of the quantized output, assigning short bits to data with a high appearance probability and long bits to data with a low appearance probability. The variable length coding to be assigned reduces the total amount of data.

Further, in a device for performing high efficiency coding, a hybrid system which is being studied by MPEG (Moving Picture experts group) and the like is predominant. In this method, in addition to intraframe compression for DCT processing an image within a frame, interframe compression for reducing redundancy in the time axis direction by utilizing correlation between frames is also adopted. Inter-frame compression further reduces the bit rate by obtaining the difference between the previous and next frames and encoding the difference value (prediction error) by using the property that general moving images are similar to each other. It is what makes me. In particular, motion-compensated interframe predictive coding that reduces the prediction error by predicting the motion of an image and obtaining the interframe difference is effective.

As described above, in the hybrid system, the image data of a predetermined frame and the reference image data of the frames before and after this frame are subjected to the intra-frame coding in which the image data of the predetermined frame is directly DCT processed and coded. Predictive coding in which only difference data is DCT processed and coded is adopted. The predictive coding method includes forward predictive coding for motion-compensating temporally forward reference image data to obtain a prediction error, and backward predictive coding for temporally motion-compensating backward-oriented reference image data to obtain a predictive error. There are predictive coding and bidirectional predictive coding using an average of either forward or backward or both directions in consideration of coding efficiency.

Since a frame coded by intra-frame coding (hereinafter referred to as I picture) is coded only by intra-frame information, it can be decoded only by single coded data. Therefore, in the MPEG standard, one I picture is inserted in a fixed cycle (for example, 12 frames) to prevent error propagation. In the MPEG standard, an inter-frame coded frame (hereinafter referred to as P picture) is obtained by forward predictive coding using this I picture. The P picture can also be obtained by performing forward predictive coding on the forward P picture. Also, a bidirectional predictive adaptive switching frame (hereinafter referred to as a B picture) is obtained by bidirectional predictive coding using either forward or backward I or P pictures in both directions.

FIG. 7 is an explanatory diagram for explaining the compression method of this system. 7A shows an input frame image, FIG. 7B shows encoded data, and FIG. 7C shows decoded data. Further, FIG. 8 is an explanatory diagram for explaining blocking.

The frame image of frame number 0 is intra-frame coded. Using this frame image as a reference image, the frame image of frame number 3 is forward predictively encoded. The arrow in FIG. 7B indicates the prediction direction of such encoding, and the frame image of frame number 6 is also subjected to forward predictive encoding using the frame image of frame number 3 ahead as a reference image. Further, the frame images with frame numbers 1 and 2 are bidirectionally predictively coded using the frame images with frame numbers 0 and 3 as reference images. The frame images with frame numbers 4 and 5 are bidirectionally predictively coded using the frame images with frame numbers 3 and 6 as reference images.

That is, as shown in FIG. 7B, first, the image data of frame number 0 is intra-coded to obtain an I picture. In this case, the image data of frame number 0 is framed by a memory or the like, and as shown in FIG. 8, it is divided into blocks of 8 pixels × 8 lines, and DCT processing is performed in block units. In the figure, ODD indicated by a solid line indicates a scan line of an odd field, and E indicated by a broken line.
VEN indicates a scan line of an even field. DCT
The DCT transform coefficient obtained by the processing is quantized by using a predetermined quantized coefficient, and then variable length coding is performed to obtain coded data.

For the frame image with the frame number 1 input next, bidirectional predictive coding using the frame images with the frame numbers 0 and 3 is performed. Therefore, until the frame image with the frame number 3 is coded, it is stored in the memory. Hold. Similarly, the frame image of frame number 2 is also encoded after the frame image of frame number 3 is encoded. For the frame image of frame number 3, forward prediction coding is performed using the frame image of frame number 0 as a reference image to obtain a P picture (FIG. 7B). That is, the image data of frame number 0 is motion-compensated using the motion vector, and the difference (prediction error) between the motion-compensated reference image data and the image data of the current frame (frame of frame number 3) is subjected to DCT processing. The variable length coding after quantizing the DCT transform coefficient is the same as the intraframe coding.

Next, the already encoded frame numbers 0, 3
I and P pictures of frame numbers 1 and 2
Frame images are sequentially bidirectionally predictively encoded. In this way, two B pictures are obtained as shown in FIG. Thereafter, similarly, as shown in FIG. 7B, the frame images of frame numbers 6, 4, 5, ... Are encoded in order to obtain P picture, B picture, B picture ,.

Thus, at the time of encoding, the encoding is performed in a frame order different from the actually input frame order. At the time of decoding, it is necessary to restore the decoding order of the encoded data and output the decoded data in the order of frame numbers 0, 1, 2, .... FIG. 9 is a block diagram showing such a conventional image decoding apparatus. 10 is an explanatory diagram for explaining framing, and FIG. 10A shows framing during non-interlaced scanning.
(B) shows framing during interlaced scanning.

Encoded data is supplied to the code buffer memory circuit 1. The coded data is variable-length coded in the coding order shown in FIG. 7B after the image data or the prediction error is DCT processed and quantized. The code buffer memory circuit 1 holds the input coded data, adjusts the decoding processing time and the output processing time, and outputs them to the variable length decoding circuit 2. The variable length decoding circuit 2 performs variable length decoding on the encoded data and outputs it to the inverse quantization circuit 3 and the buffer control circuit 7. The buffer control circuit 7 controls the code buffer memory circuit 1.

The output of the variable length decoding circuit 2 is an inverse quantization circuit 3
Inverse quantization by the inverse DCT circuit 4
The data is processed and returned to the data before the DCT processing on the encoding side. Now, it is assumed that an I picture which is encoded data of frame number 0 is input. In this case, the output of the inverse DCT circuit 4 is the restored image of frame number 0,
The output of the T circuit 4 is given to the frame memory 6 as it is.

The output of the inverse DCT circuit 4 is pixel data in block units, and the frame memory 6 holds pixel data for one frame. When performing non-interlaced display, as shown in FIG.
Outputs the output of the inverse DCT circuit 4 in frame order and outputs in raster order. Further, when performing interlaced display, as shown in FIG. 10B, the frame memory 6 divides the output of the inverse DCT circuit 4 into odd field data and even field data, and arranges each field. Output in raster order for each. The output of the frame memory 6 is output as decoded data via the switch 16 (see FIG. 7).
(C)). The restored image data of frame number 0 from the inverse DCT circuit 4 is also supplied to the frame memory 12 for decoding P and B pictures.

If the DCT block is divided into blocks after being framed, assuming that non-interlaced display is performed, it is not necessary to change the pixel array in the line direction, and therefore, as a memory for changing the output order. ,
It suffices if there is a capacity for holding data for 8 lines (1 block line). However, in order to enable the interlaced display, it is necessary to separately output the data into the odd field and the even field, so that more memory is required. For this reason, in general, a frame memory is often used as a memory for changing the display order to perform framing.

Next, the P picture of frame number 3 is decoded. In this case, the output of the inverse DCT circuit 4 is a prediction error. On the other hand, the motion vector extraction circuit 8 extracts the motion vector contained in the output of the variable length decoding circuit 2 and supplies it to the motion compensation circuit 10. The motion compensation circuit 10 extracts the restored image data of the I picture from the frame memory 12. Read and perform motion compensation using the motion vector. The output of the motion compensation circuit 10 is given to the adder 5 via the switch 15. The adder 5 uses the motion-compensated restored image data of frame number 0 and the inverse DC
The restored image data of frame number 3 is obtained by adding the prediction error from the T circuit 4. This data is stored in the frame memory 11
Supply to.

Next, the B picture of frame number 1 is decoded. Also in this case, the output of the inverse DCT circuit 4 is a prediction error. The motion vector extraction circuit 8 extracts the motion vector between the image of frame number 3 and the image of frame number 1 from the variable length decoded output and supplies it to the motion compensation circuit 9, which uses the motion vector. , The restored image data of frame number 3 is motion-compensated from the frame memory 11 and output to the adder 13. The adder 13 adds the outputs of the motion compensation circuits 9 and 10 according to the prediction mode at the time of encoding, and supplies the outputs to the adder 5 via the switch 15. The adder 5 adds the output of the switch 15 to the prediction error to obtain the restored image data of the B picture of frame number 1. This image data is given to the frame memory 6 to be framed, and then output via the switch 16 (FIG. 7C).

Next, the B picture of frame number 2 is decoded. Also in this case, the output of the inverse DCT circuit 4 and the output of the switch 15 are added to obtain the restored image data of the B picture of frame number 2. This image data is given to the frame memory 6 to be framed, and then output via the switch 16 (FIG. 7C). Next, as shown in FIG. 7C, the restored image data of frame number 3 stored in the frame memory 11 is output as decoded data in the display order via the switches 14 and 16.

After that, the same operation is repeated, and FIG.
The image data (decoded data) restored in the decoding order of is output. The decoding process and the output process are controlled in consideration of the memory overlap amount and the operating time in the system.

As described above, the P picture is decoded by using the reference image of the front frame, and the decoding requires a memory for one frame to hold the reference image.
Further, the B picture is decoded using the reference images of the front and rear frames, and a memory for two frames is required to hold these reference images. Furthermore, since the encoding process is performed in DCT block units, as described above, a memory for one frame is required to frame the output of the adder 5 to enable interlaced display or non-interlaced display. . In this case, the decoded data of the I and P pictures is stored in the frame memories 11 and 12 to be used as the reference image of the B picture, and the read from these frame memories 11 and 12 is controlled and output. The frame memories 11 and 12 can also be used for framing. However, since the decoded data of the B picture is not used for the reference image and is not stored in the frame memories 11 and 12, it is necessary to provide the frame memory 6 for framing.

[0022]

As described above, in the above-described conventional image decoding apparatus, a large number of memories are required to decode image coded data including B pictures, and the circuit scale is large. However, there is a problem in that the cost increases as the cost increases.

It is an object of the present invention to provide an image decoding apparatus capable of reducing the memory required for decoding image coded data including B pictures to reduce the circuit scale and cost. To do.

[Constitution of Invention]

According to a first aspect of the present invention, an image decoding device receives coded data including bidirectional predictive coded data using forward and backward reference images,
First storage means for storing the input encoded data,
First decoding means for decoding the input coded data or the coded data read from the first storage means in a predetermined block unit and outputting the decoded data; and the first decoding means. Second storage means capable of storing the decoded data from the device as reference image data, and detection means for detecting a block of the reference image necessary for decoding the predetermined block of the encoded data by the first decoding means. And reading the data of the block designated by the detection means from the first storage means and performing a decoding process using the reference image data stored in the second storage means, thereby performing the first decoding. Second decoding means for creating reference image data of encoded data to be decoded by the decoding means, and reference image data from the second decoding means are stored, and the second decoding means stores the reference image data. A third storage means which can be output as reference image data in the No. process, the first
And a fourth storage means for storing the decoded data for the bidirectionally predictive coded data from the decoding means, framed and output in a display order,

[0025]

In the present invention, the first decoding means stores the decoded data obtained by decoding the coded data in the second storage means as reference image data. When decoding bidirectional predictive coded data, the detection means detects a block of the reference image necessary for decoding, and the second decoding means reads the data of this block from the first storage means. Decoding is performed using the reference image data stored in the second storage means. For example, while storing this decoded data in the third storage means, the first decoding means is caused to decode both predictive decoded data in parallel with the decoding processing by the second decoding means. Thus, the bidirectional predictive encoded data can be decoded by storing the reference image data for up to 4 blocks in the third storage means.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an image decoding apparatus according to the present invention. In FIG. 1, the same components as those in FIG. 9 are designated by the same reference numerals. In the present embodiment, the encoded data is decoded and the decoded data is output in the display order of interlaced display.

The encoded data is the code buffer memory circuit 1
Supply to. This coded data is created by DCT processing, quantization processing, and variable length coding processing, and includes I-pictures by intra-frame processing, P-pictures using reference images of forward or backward frames, and bidirectional frames. It has a B picture using a reference image. The encoded data also includes information on the motion vector used when creating the P and B pictures. It should be noted that the DCT processing is performed on a block-by-block basis obtained by dividing the frame into blocks.

The code buffer memory circuit 1 holds the input coded data, and outputs it after matching the decoding processing time and the output processing time. In this embodiment,
The output of the code buffer memory circuit 1 is supplied to the terminal a of the switch 21, the memory 22, and the picture detection and position detection circuit 23. The picture detection and position detection circuit 23 detects the picture type of the input encoded data and outputs a detection signal to the buffer control circuit 24.

The buffer control circuit 24 controls the code buffer memory circuit 1 based on the detection signal. Further, the buffer control circuit 24 controls writing and reading of the memory 22 based on the detection signal, and also controls switching of the switch 21. That is, the buffer control circuit 24 stores the coded data of the I picture or P picture in the memory 22 when the detected signal indicates that the coded data of the I picture or the P picture is output from the code buffer memory circuit 1. , If it is indicated that the encoded data of the B picture is output, the switch 21 selects the terminal a and supplies the encoded data of the B picture as it is to the variable length decoding circuit 2. The memory 22 is a FIFO (fast-in fast-out) memory,
It has a capacity capable of storing encoded data of I and P pictures. The code amount of I and P pictures is sufficiently smaller than the data amount of pixel data for one frame, and
Need only have a capacity of about 1/4 of the frame memory that stores pixel data for one frame.

FIG. 2 is an explanatory diagram for explaining the storage area of the memory 22 in FIG.

As shown in FIG. 2, the memory 22 has a plurality of areas each having a bit length n, and each of these areas is designated by addresses a1, a2, ....
Encoded data is processed in blocks and memory
Data is written to 22 in block units. The encoded data is a variable length code, and the block lengths of the blocks are different from each other. In the memory 22, as shown in FIG. 2, the data of the first block (block 1) is sequentially arranged from the head of the address a1. For example, in FIG. 2, the data of the block 1 is written by b1 bits from the beginning of the address a1 and then the data of the block 2 is written from the beginning of the address a2 to b2
It indicates that bits are arranged.

In the present embodiment, the picture detection and position detection circuit 23 uses the encoded data of I and P pictures to
By detecting the block length and the block start position of each block, the memory position of the block stored in the memory 22 (hereinafter referred to as the start position) is detected and written in the memory 25.

FIG. 3 is an explanatory diagram for explaining the storage area of the memory 25 in FIG.

As shown in FIG. 3, the memory 25 has an address corresponding to each block, and each address has an address on the memory 22 of each block and its bit start position as shown in FIG. And remember. The picture detection and position detection circuit 23 supplies the number of the block of the input I and P pictures as an address to the memory 25, and at this address, the address and bit start position of the memory 22 where this block data is stored. Store the data. For example, FIG. 3 shows that the block data of the block 1 is stored from the beginning of the address a1 of the memory 22, and the block data of the block 2 is stored from the b1 bit of the address a1 of the memory 22.

The buffer control circuit 24 reads out the I and P pictures stored in the memory 22 at the same time as writing the encoded data of the I and P pictures from the code buffer memory circuit 1 and reads them through the terminal b of the switch 21. Variable length decoding circuit 2
To be supplied. Furthermore, the buffer control circuit
When the encoded data of the B picture is output from the code buffer memory circuit 1, the reference numeral 24 indicates the encoded data of the P picture stored in the memory 22 based on the start position information supplied from the memory 25. Is read out and output to the variable length decoding circuit 32.

The variable length decoding circuit 2 is supplied with the encoded data through the switch 21 and restores the data before the variable length encoding process on the encoding side by the variable length decoding process. The output of the variable length decoding circuit 2 is supplied to the inverse quantization circuit 3 and also to the motion vector extraction circuit 8 via the switch 36.
The motion vector extraction circuit 8 is also supplied with a variable length decoding output from a variable length decoding circuit 32 described later via a switch 36. The motion vector extraction circuit 8 has P, B
For the picture, the motion vector included in the variable length decoded output is extracted and output to the motion compensation circuit 9.

On the other hand, the inverse quantization circuit 3 inversely quantizes the input data and gives it to the inverse DCT circuit 4. The inverse DCT circuit 4 inversely DCT-processes the inverse quantized output and outputs it to the adder 5. .

The output of the switch 15 is also given to the adder 5.
The switch 15 gives 0 to the adder 5 when the output of the inverse DCT circuit 4 is based on an I picture, and when it is based on a P picture, a motion compensation circuit 9 described later.
Of the motion compensation circuit 9 and the block buffer 37 described later or the output of the adder 13 described later are given to the adder 5. The adder 5 restores the image by adding the output of the inverse DCT circuit 4 and the output of the switch 15, and outputs the image to the frame memories 6 and 11.

The frame memory 11 holds the coded data from the adder 5 based on the coded data of I and P pictures as a forward reference image, reads the held decoded data in display order, and switches it as restored image data. Output through 16. Further, the frame memory 6 holds the output of the adder 5 based on the decoded data of the B picture, frames it, reads the held decoded data in the display order, and outputs it as restored image data via the switch 16. ing. The switch 16 is switched in accordance with the output frame order of the image and outputs the restored image data of a series of frames as decoded data.

The frame memory 11 outputs the reference image data held at the decoding timing of the corresponding P and B pictures to the motion compensation circuit 9 via the switch 40. The motion compensation circuit 9 motion-compensates the reference image data from the frame memory 11 based on the motion vector from the motion vector extraction circuit 8 and outputs it. The output of the motion compensation circuit 9 is supplied to the switch 15 and also to the adders 13 and 35.

In this embodiment, there are two systems of decoding processing circuits. That is, the first decoding processing system having the variable length decoding circuit 2, the inverse quantization circuit 3, the inverse DCT circuit 4, and the adder 5, and the variable length decoding circuit 32 and the inverse quantization having the same configurations as these circuits, respectively. Circuit 33, inverse DCT circuit 34 and adder
And a second decoding processing system having 35. The motion vector extraction circuit 8 and the motion compensation circuit 9 are shared by the first decoding processing system and the second decoding processing system. The second decoding processing system is for creating a backward reference image necessary for the decoding processing of the first decoding processing system.

By the way, the inverse DCT process and the quantization process in the decoding are performed in block units as in the encoding.
That is, the reference image supplied from the switch 15 to the adder 5 is block data. Therefore, when decoding a given block, including the position corresponding to that block,
It suffices to have a memory for storing image data of blocks within the motion compensation range. Furthermore, if the motion correction amount and its direction are known, the range of the backward reference image that needs to be stored in the memory in the decoding of the first decoding processing system can be further reduced.

For this reason, in this embodiment, the block used as the backward reference image is determined based on the motion vector of the decoded block. That is, the motion vector decoded by the variable length decoding circuit 2 is given to the motion compensation circuit 38. The motion compensation circuit 38 detects a block number required as a reference image from the motion vector and stores it in the memory 25.
It is designed to be output as an address to. Memory 25
The information on the start position stored at the specified address is given to the memory 22, and the corresponding block data is output from the memory 22.

The variable length decoding circuit 32 performs variable length decoding on the encoded data of the P picture from the memory 22 and performs the inverse quantization circuit 33.
And also to the motion vector extraction circuit 8 via the switch 36. The inverse quantization circuit 33 inversely quantizes the input data, gives it to the inverse DCT circuit 34, and inverse DC
The T circuit 34 performs inverse DCT processing on the inverse quantized output and outputs it to the adder 35.

On the other hand, the forward reference image for the P picture read out from the memory 22 is already decoded and stored in the frame memory 11. As described above, the motion vector extraction circuit 8 and the motion compensation circuit 9 are also used in the second decoding processing system,
At the decoding processing timing by the second decoding processing system,
The motion compensation circuit 9 reads the reference image data from the frame memory 11, performs motion compensation based on the motion vector, and outputs it to the adder 35. That is, the motion compensation circuit 9 corrects the block position of the decoded block based on the motion vector,
By blocking the reference image at the corrected position,
The block data of the motion compensated reference image is obtained. The adder 35 adds the output of the inverse DCT circuit 34 and the output of the motion compensation circuit 9 to obtain P selected by the memory 25.
A restored image for a block of a picture is obtained in block units and is output to the block buffer 37 as block data of a backward reference image.

Depending on the motion vector, the motion-compensated block data spans the original four blocks. Therefore, the block buffer 37 may have a capacity capable of storing block data of 4 blocks. The block buffer 37 is a motion compensation circuit for the stored backward reference image data.
Blocking is performed based on the blocking position information from 38 and output to the adder 13 and the switch 15. The adder 13 includes a motion compensation circuit 9 and a block buffer 37 according to the prediction mode.
The outputs of are added and output to the switch 15.

The output of the frame memory 11 is the memory 39
Is also given to. The memory 39 stores the image data from the frame memory 11 as forward reference image data when the P picture is decoded by the first decoding processing system. As described above, the memory 39 has a capacity for storing reference image data in a predetermined range including the same block position as the output of the adder 5 in consideration of the fact that the block position is corrected by the motion vector. All you have to do is do it. The switch 40 selects the terminal b and outputs the input image data to the motion compensation circuit 9 only when the P picture is decoded by the first decoding processing system.

Next, the operation of the embodiment thus constructed will be described with reference to FIGS. 4 and 5. FIG. 4 is a timing chart for explaining the operation of the embodiment,
FIG. 4A shows the frame number of the input encoded data, FIG. 4B shows its picture type, and FIG.
4C shows the output of the code buffer memory circuit 1, and FIG.
4D shows input / output of the memory 22, FIG. 4E shows a backward reference image of the block buffer 37, FIG. 4F shows a reference image of the memory 39, and FIG. 4G shows a frame memory. 11
3 shows a forward reference image of FIG. FIG. 5 is an explanatory diagram for explaining the operation of the embodiment. FIG. 5A shows the reading from the frame memory 11 at the time of P picture decoding, and FIG. 5B shows the writing to the memory 39 in this case.

The encoded data is the code buffer memory circuit 1
Supply to. The encoded data has I, P, and B pictures, and is encoded by, for example, the prediction method of FIG. 7A, and is input in the frame order shown in FIG. 7B (FIG. 4A). It shall be. The code buffer memory circuit 1 holds the input coded data in consideration of the coding processing time and the output time and outputs it to the terminal a of the switch 21, the memory 22, and the picture detection and position detection circuit 23. First, FIG.
As shown in (a), the encoded data of the I picture of frame number 0 is input. The picture detection circuit 23 detects that it is an I picture and outputs a detection signal to the buffer control circuit 24.
Output to. As a result, the buffer control circuit 24 controls the code buffer memory circuit 1 and the memory 22, and at the timing shown in FIG.
The encoded data of the I picture of (0 frame) is read and written in the memory 22 (FIG. 4 (d)). In this embodiment,
At this point, the I picture is not decoded.

Next, as shown in FIG. 4A, the encoded data of the P picture of frame number 3 (3 frames) is input. This encoded data is read from the code buffer memory circuit 1 by the buffer control circuit 24 at the timing shown in FIG. 4C and written in the memory 22 (FIG. 4).
(D)). The memory 22 is a FIFO memory and is shown in FIG.
As shown in (d), the buffer control circuit 24 writes the coded data of the P picture of 3 frames and at the same time, reads the coded data of the I picture of 0 frame, and outputs it via the terminal b of the switch 21. Output to the variable length decoding circuit 2. On the other hand, the picture detection and position detection circuit 23 detects the block length of encoded data and the start position of the block, and writes it in the memory 25.

The variable length decoding circuit 2 variable length decodes the coded data of the I picture and outputs it to the inverse quantization circuit 3.
Further, the encoded data is inversely quantized by the inverse quantization circuit 3, inverse DCT processed by the inverse DCT circuit 4, restored to the data before DCT processing on the encoding side, and output to the adder 5. In this case, the output of the inverse DCT circuit 4 is a restored image of 0 frame. Note that these processes are performed in block units. The switch 15 gives 0 to the adder 5, and the adder 5 outputs the output of the inverse DCT circuit 4 as it is to the frame memory.
11 and store it as a forward reference image (see FIG. 4).
(G)). Further, the restored image data stored in the frame memory 11 is read in the order of display and output via the switch 16.

Next, as shown in FIG. 4A, the coded data of the B picture of frame number 1 (1 frame) is input. The buffer control circuit 24 sends the coded data to the code buffer memory circuit 1 at the timing shown in FIG.
From the switch 21 and is given to the variable length decoding circuit 2 constituting the first decoding processing system via the terminal a of the switch 21.

The variable length decoding circuit 2 variable length decodes the coded data of the B picture and outputs it to the motion compensation circuit 38. The motion compensation circuit 38 extracts a motion vector from the variable length decoded output and outputs the block indicated by the motion vector as an address of the memory 25. In this case, up to 4 blocks are designated as addresses for one decoded block.

The memory 25 outputs the information of the start position stored at the designated address to the memory 25. For example, assuming that the motion vector of the first coded block of the coded data of one frame specifies the adjacent third and m-th blocks of the reference image of three frames, the memory 25 stores, for example, in FIG. As shown, memory 22
Stored at bit b2 and after of address a2 of
The block data is designated and the block data is output, and the block data of the area storing the m-th block is output. The block data read from the memory 22 is given to the variable length decoding circuit 32.

In this way, the decoding process of the backward reference image of 3 frames by the second decoding processing system is performed slightly in parallel with the decoding process of the B picture of 1 frame by the first decoding processing system. To do. The variable length decoding circuit 32 performs variable length decoding of the input P picture encoded data,
Further, the inverse quantization circuit 33 and the inverse DCT circuit 34 are used to
The data before the T processing is restored and supplied to the adder 35. Also,
The motion vector extraction circuit 8 is supplied with a variable length decoding output via the switch 36, extracts a motion vector and supplies it to the motion compensation circuit 9. As shown in FIG. 4G, at this time, the frame memory 11 stores the restored image data of 0 frame which is the reference image of the P picture of 3 frames. The motion compensation circuit 9 reads 0 from the frame memory 11.
The frame reference image data is motion-compensated based on the motion vector and given to the adder 35. The adder 35 adds the motion-compensated reference image data to the prediction error from the inverse DCT circuit 34, restores the image of a predetermined block of 3 frames in block units, and supplies it to the block buffer 37 (FIG. 4).
(E)). Similarly, only the P picture block necessary for the decoding processing of the B picture decoding block is decoded and stored in the block buffer 37.

On the other hand, the output of the variable length decoding circuit 2 is returned to the data before the DCT processing by the inverse quantization circuit 3 and the inverse DCT circuit 4 and supplied to the adder 5. The motion vector extraction circuit 8 is supplied with a variable length decoding output via the switch 36, extracts a motion vector, and supplies it to the motion compensation circuit 9. The frame memory 11 stores the restored image data of 0 frame which is the forward reference image of the image of 1 frame (FIG. 4 (g)). Further, the backward reference image of the image of one frame is stored in the block buffer 37 (FIG. 4).
(E)).

The motion compensation circuit 9 corrects the blocking position of the restored image data in the frame memory 11 based on the motion vector, and switches the motion-compensated block data.
Output to 15 and adder 13. Also, the block buffer 37
Is the motion compensation circuit 38 for the stored backward reference image data.
Block based on the location information from
The motion compensated block data is added to the switch 15 and the adder 13
Give to.

The adder 13 adds the outputs of the motion compensation circuit 9 and the block buffer 37 and outputs the result to the switch 15. The switch 15 selects the output of the motion compensation circuit 9 when the prediction direction of the B picture of one frame is forward, selects the output of the block buffer 37 when it is backward, and selects the output of the block buffer 37 when it is backward. The output of the adder 13 is selected and output to the adder 5 as motion-compensated reference block data. In this way, the adder 5 adds the block data from the inverse DCT circuit 4 and the reference image data in block units from the switch 15 to restore one frame of image data in block units and outputs it to the frame memory 6. .

Thereafter, by repeating the same operation, the restored image data of one frame of B picture is output from the adder 5 in block units and stored in the memory 6. Memory 6
Frame the restored image data of B picture by
The data are read out in the order of display and output via the switch 16.

Next, as shown in FIG. 4A, the encoded data of the B picture of frame number 2 (2 frames) is input. The buffer control circuit 24 supplies the coded data of the B picture of two frames to the variable length decoding circuit 2 via the switch 21 at the timing shown in FIG. Also in this case, the motion compensation circuit 38 specifies the block of the backward reference image necessary for the decoding process of each block data of two frames in the memory 25 based on the motion vector. The memory 25 specifies the read position of the memory 22, and the memory 22 reads the block data from the specified position and supplies it to the variable length decoding circuit 32.

In this way, the decoding process of the P picture of 3 frames is performed prior to the decoding process of the predetermined block data of the B picture of 2 frames. Block buffer
When the backward reference image necessary for the decoding processing is stored in 37, the decoding processing of the B picture of 2 frames is performed in the first decoding processing system. The decoded data of two frames is read from the frame memory 6 in the order of display and output via the switch 16.

Next, as shown in FIG. 4A, the encoded data of the P picture of frame number 6 (6 frames) is input. The coded data is read from the code buffer memory circuit 1 and written in the memory 22 by the buffer control circuit 24 at the timing shown in FIG. The coded data of the 3-frame P-picture stored in the memory 22 is supplied to the variable length decoding circuit 2 via the terminal b of the switch 21. Then, the variable length decoding circuit 2, the inverse quantization circuit 3 and the inverse DCT circuit 4 restore the prediction error.

On the other hand, the frame memory 11 supplies the restored image data of 0 frame to the memory 39 as a reference image at a timing slightly before this decoding process. In this case,
Similar to the decoding process of the B picture, the restored image data of 0 frame is transferred to the memory 39 according to the position of the decoding block of the P picture of 3 frames. That is,
For example, by the timing when the prediction error of the block of the first block line of the P picture of 3 frames is output from the inverse DCT circuit 4, the image data in the motion compensation range on the upper side of the screen including the first block line is stored in the memory 39. Forward to. The motion compensation circuit 9 corrects the block position of the image data from the memory 39 based on the motion vector, and outputs the motion-compensated reference image block data to the adder 5 via the switch 15. The adder 5 adds the prediction error from the inverse DCT circuit 4 and the block data of the reference image to restore the image of 3 frames in block units, and supplies it to the frame memory 11.

Thus, as shown in FIG. 5A, the restored image data of 0 frame already stored in the frame memory 11 is sequentially updated by the restored image data of 3 frames. The shaded area in FIG. 5A indicates a block line in which writing is performed. With this update,
As shown in (b), the restored image data of 0 frame stored in the frame memory 11 is sequentially transferred to the memory 39.

Thereafter, the same operation is repeated to decode the P picture of 3 frames, and as shown in FIG. 4 (g), the restored picture data of 3 frames are input to the B pictures of the frame numbers 4 and 5 to be input next. Frame memory 11 as a reference image for
To be stored. The restored image data is read out in the order of display and output via the switch 16. After that, the same operation is repeated, and the decoded data in the display order is output from the switch 16.

Thus, in this embodiment, B, P
As a memory for a backward reference image necessary for decoding encoded data of a picture, a block buffer 37 for up to 4 blocks based on a motion compensation range is adopted, and a frame memory is used as a memory for a forward reference image. 11 and a small capacity memory 39 based on the motion compensation range,
The backward reference image is decoded corresponding to the P picture decoding process and stored in the block buffer 37, and the memory capacity can be reduced as compared with the case where a frame memory is used for the backward reference image. As a result, the circuit scale can be reduced and the cost can be reduced.

FIG. 6 is a block diagram showing another embodiment of the present invention. 6, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the embodiment of FIG. 1, two systems of decoding processing circuits are provided, but since the decoding processing circuits of each system have the same configuration, they can be shared by performing time division processing. In this embodiment, an increase in circuit scale is prevented by time division processing.

In the present embodiment, the variable length decoding circuit 32, the inverse quantization circuit 33, the inverse DCT circuit 34 and the adder 35 are deleted, and a buffer control circuit 51 is used instead of the buffer control circuit 24 for memory.
It differs from the embodiment of FIG. 1 in that the encoded data read from 22 is supplied to the variable length decoding circuit 2 via the terminal b of the switch 21. The buffer control circuit 51 controls the code buffer memory circuit 1 based on the detection signal. In addition, the buffer control circuit 51 causes the I picture or P depending on the detection signal.
When it is shown that the coded data of the picture is output from the code buffer memory circuit 1, it is indicated that these coded data are stored in the memory 22 and the coded data of the B picture is output. In this case, the switch 21 selects the terminal a and supplies the coded data of the B picture as it is to the variable length decoding circuit 2.

Further, the buffer control circuit 51 reads out the I and P pictures stored in the memory 22 at the same time as writing the encoded data of the I and P pictures from the code buffer memory circuit 1 and reads out the terminal b of the switch 21. Is supplied to the variable length decoding circuit 2 via.

In the present embodiment, the P and B picture decoding processing and the P reference picture decoding processing for the backward reference picture thereof are performed in a time division manner. For example, NTSC
Images typically have a sampling frequency of 1
It is set to 3.5 MHz. On the other hand, the current operating speed of the integrated circuit is sufficiently high, and even when the same circuit as the conventional one is used for the decoding processing in this embodiment, the time division processing can be sufficiently performed.

Next, the operation of the embodiment thus constructed will be described.

In this embodiment, the buffer control circuit 51
Control by frame memory 11 and block buffer 37
The write and read control of is different from the embodiment of FIG. It is assumed that the coded buffer memory circuit 1 receives the coded data shown in FIGS. 2 (a) and 2 (b). In this embodiment, reading from the code buffer memory circuit 1 is the same as in the embodiment of FIG. That is, the first input encoded data of the 0-frame I picture is the buffer control circuit 51.
The data is read from the code buffer memory circuit 1 at the timing shown in FIG. The buffer control circuit 51 writes this encoded data in the memory 22. Next, P of 3 frames
When the coded data of the picture is output from the code buffer memory circuit 1, the buffer control circuit 51 reads the coded data of the I picture from the memory 22 and writes the coded data of the P picture of 3 frames to the memory 22. Put in. Further, the picture detection and position detection circuit 23 supplies information indicating the start position of each block data to the memory 25 to store it.

The coded data of the I picture is given to the variable length decoding circuit 2 via the terminal a of the switch 21 and variable length decoding is performed. In this way, the restored image data of 0 frame is obtained from the inverse DCT circuit 4. This image data is stored in the frame memory 11 as forward reference image data, read out in the display order from the frame memory 11, and output from the switch 16.

Next, the buffer control circuit 51 causes the code buffer memory circuit 1 to output the encoded data of the B picture of one frame, and supplies it to the variable length decoding circuit 2 via the terminal a of the switch 21. The variable length decoding circuit 2 performs variable length decoding of the B picture, and the motion compensation circuit 38 detects the backward motion vector and specifies the block of the backward reference image necessary for decoding the B picture. The memory 25 gives information on the start position of the designated block to the memory 22, and reads the block data of the P picture of 3 frames from the memory 22. In this embodiment, the encoded data of the P picture from the memory 22 is supplied to the variable length decoding circuit 2 via the terminal b of the switch 21. In this way, P of 3 frames from the inverse DCT circuit 4
Get the prediction error of a picture. On the other hand, the motion compensation circuit 9 blocks the restored image data of 0 frame stored in the frame memory 11 at the blocking position based on the motion vector, and outputs it to the adder 5 via the switch 15. The adder 5 adds the output of the inverse DCT circuit 4 and the output of the switch 15 and outputs the restored image data of 3 frames in block units.

In this case, the restored image data of 3 frames from the adder 5 is sequentially written in the block buffer 37.
In this way, when a predetermined block of backward reference images of up to 4 blocks necessary for decoding one frame of B picture is written in the block buffer 37, the buffer control circuit 51 outputs the B picture from the encoding buffer memory circuit 1. Then, it is supplied to the variable length decoding circuit 2 via the terminal a of the switch 21. In this way, the prediction error of the first block of the first block line of one frame is obtained from the inverse DCT circuit 4. One frame of forward reference image data is stored in the frame memory 11, and necessary backward reference image data is stored in the block buffer 37. The motion compensation circuit 9 and the block buffer 37 are stored in the block buffer 37.
Outputs motion-compensated block data. The adder 5 receives the block data of the motion-compensated reference image from the switch 15 and adds it to the prediction error from the inverse DCT circuit 4 to obtain the restored image data of the first block. This image data is stored in the frame memory 6.

Next, the buffer control circuit 51 reads out the second block data of the B picture from the code buffer memory circuit 1 and supplies it to the variable length decoding circuit 2 for motion compensation circuit.
A block of P picture necessary for decoding this block data is detected by 38. The switch 21 selects the terminal b and reads the block data of the P picture from the memory 22. The decoded data of this block data is stored in the block buffer 37 and used as the backward reference image. Next, the buffer control circuit 51 causes the switch 21 to select the terminal a, reads the second block data of the B picture from the code buffer memory circuit 1, and supplies it to the variable length decoding circuit 2. At this time point, the forward reference image data is stored in the frame memory 11, the backward reference image data is stored in the block buffer 37, and the decoding process of the second block data is performed.

After that, the reading is switched between the code buffer memory circuit 1 and the memory 22 in units of one block, and the decoding processing of the B picture and the P picture which is the backward reference picture thereof is alternately performed. In this way, the B picture is decoded, and the restored image data is read from the frame memory 6 in the display order. After that, similarly, the B picture of 2 frames is also decoded.

When decoding P pictures of 6 frames, the reference image data of 3 frames stored in the frame memory 11 is read out and stored in the memory 39. In this way, the memory 39 is written to the extent necessary for decoding the block of the first block line of the P picture of 6 frames. Next, the P picture is decoded, and the decoded data is written in the frame memory 11 in block units. Simultaneously with this writing, the next data is read from the frame memory 11 and transferred to the memory 39. After that, the same operation is repeated to decode the P picture of 6 frames.

As described above, also in this embodiment, the same effect as that of the embodiment of FIG. 1 can be obtained. Further, by sharing the circuit, the circuit scale can be reduced as compared with the embodiment of FIG.

[0080]

As described above, according to the present invention, B
It is possible to reduce the memory required for decoding image coded data including a picture, reduce the circuit scale, and reduce the cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image decoding apparatus according to the present invention.

FIG. 2 is an explanatory diagram for explaining a storage area of a memory 22 in FIG.

FIG. 3 is an explanatory diagram for explaining a storage area of a memory 25 in FIG.

FIG. 4 is a timing chart for explaining the operation of the embodiment.

FIG. 5 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 6 is a block diagram showing another embodiment of the present invention.

FIG. 7 is an explanatory diagram illustrating a hybrid compression method.

FIG. 8 is an explanatory diagram for explaining blocking.

FIG. 9 is a block diagram showing a conventional image decoding device.

FIG. 10 is an explanatory diagram for explaining framing.

[Explanation of symbols]

1 ... Code buffer memory circuit, 6, 11 ... Frame memory, 21 ... Switch, 22, 25 ... Memory, 23 ... Picture detection and position detection circuit, 24 ... Buffer control circuit, 37 ... Block buffer, 38 ... Motion compensation circuit

Claims (7)

[Claims] 1. A first storage unit for inputting encoded data including bidirectional predictive encoded data using forward and backward reference images, and storing the input encoded data, and the input encoding. First decoding means for decoding data or coded data read from the first storage means in a predetermined block unit and outputting decoded data; and decoded data from the first decoding means. Second storage means capable of storing as reference image data, detection means for detecting a reference image block necessary for decoding the predetermined block of the encoded data by the first decoding means, and this detection means By reading the data of the designated block from the first storage means and performing a decoding process using the reference image data stored in the second storage means, the first decoding is performed. Storing a second decoding means for generating reference image data of the coded data which means for decoding the reference image data from the second decoding means,
Third storage means capable of outputting as reference image data in the decoding process of the first decoding means, and decoded data for the bidirectional predictive encoded data from the first decoding means is stored. And a fourth storage means for converting the data into frames and outputting them in display order. 2. The second and fourth storage means are constituted by a frame memory for storing one frame of pixel data, and the third storage means are constituted by a memory for storing four blocks of pixel data. The image decoding device according to claim 1, wherein 3. The detection unit detects a block of a reference image required for decoding, based on the motion vector detected in the decoding process of the first decoding unit. The image decoding device described. 4. The second decoding means, when the first decoding means performs decoding processing using reference image data stored in the third storage means, the second decoding means 1
2. The image decoding apparatus according to claim 1, wherein the decoding processing is performed in parallel with and before the processing of the decoding unit. 5. The third storage means stores the decoded data from the second decoding means in a backward reference image when the bidirectional predictive coded data is coded by the first decoding means. The image decoding apparatus according to claim 1, wherein the image decoding apparatus stores the data as data. 6. When the first decoding means encodes forward predictive encoded data of the encoded data,
At least reference image data within a range in which the decoding process of the first decoding unit is possible is transferred from the second storage unit, and a memory for storing the transferred decoded data as forward reference image data is added. Claim 1 characterized by the above-mentioned.
The image decoding device according to 1. 7. The second decoding means shares the same with the first decoding means, and performs the decoding processing of the first decoding means and the decoding processing of the second decoding means. The image decoding apparatus according to claim 1, wherein the first decoding means performs time division.