JPH0812861B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0812861B2 JPH0812861B2 JP62306378A JP30637887A JPH0812861B2 JP H0812861 B2 JPH0812861 B2 JP H0812861B2 JP 62306378 A JP62306378 A JP 62306378A JP 30637887 A JP30637887 A JP 30637887A JP H0812861 B2 JPH0812861 B2 JP H0812861B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode wiring
- layer
- barrier metal
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 title description 10
- 239000010410 layer Substances 0.000 claims description 46
- 230000004888 barrier function Effects 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 16
- 239000010931 gold Substances 0.000 claims description 14
- 239000011247 coating layer Substances 0.000 claims description 12
- 239000011347 resin Substances 0.000 claims description 12
- 229920005989 resin Polymers 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 238000007747 plating Methods 0.000 claims description 6
- 101000617550 Dictyostelium discoideum Presenilin-A Proteins 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 24
- 239000005360 phosphosilicate glass Substances 0.000 description 15
- 229920001721 polyimide Polymers 0.000 description 12
- 239000009719 polyimide resin Substances 0.000 description 12
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 10
- 239000010936 titanium Substances 0.000 description 9
- 239000000243 solution Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000008602 contraction Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】 〔概要〕 半導体装置のバンプ構造の製造方法に関し、 バンプ構造の下地膜のクラックの発生の防止並びに耐
湿性の向上を目的とし、 電極配線が形成された半導体表面にPSG膜及びSiN膜を
順次に積層した後、該PSG膜及びSiN膜に対して該電極配
線を臨む開口部を形成する第１の工程と、該第１の工程
を経た該SiN膜上を覆い、かつ、開口部を介して該電極
配線を臨むように樹脂コーティング層を形成する第２の
工程と、該樹脂コーティング層及び該開口部に臨む該電
極配線上にバリアメタル層を形成する第３の工程と、該
電極配線上の該バリアメタル層を介して金メッキによる
バンプを形成する第４の工程と、該バンプをマスクとし
て該バリアメタル層をエッチング除去する第５の工程
と、を含むように構成する。The present invention relates to a method for manufacturing a bump structure of a semiconductor device, and a PSG is formed on a semiconductor surface on which electrode wiring is formed for the purpose of preventing the occurrence of cracks in a base film of the bump structure and improving moisture resistance. A film and a SiN film are sequentially laminated, a first step of forming an opening facing the electrode wiring with respect to the PSG film and the SiN film, and covering the SiN film after the first step, And a second step of forming a resin coating layer so as to face the electrode wiring through the opening, and a third step of forming a barrier metal layer on the resin coating layer and the electrode wiring facing the opening. And a fourth step of forming bumps by gold plating on the electrode wiring via the barrier metal layer on the electrode wiring, and a fifth step of etching away the barrier metal layer using the bumps as a mask. Configure.
本発明は半導体装置の製造方法に係り、特に半導体装
置のバンプ構造の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a bump structure for a semiconductor device.
半導体チップの電極配線上に、金メッキによりバンプ
をウェーハ段階で形成するバンプ（TAB:Tape Automated
Bonding）工程においては、形成したバンプ構造の高信
頼性が必要とされる。Bumps (TAB: Tape Automated) that form bumps on the electrode wiring of a semiconductor chip by gold plating at the wafer stage
In the bonding process, high reliability of the formed bump structure is required.
従来のバンプ工程を経て製造された半導体装置の構造
は第５図（Ａ）に示す如く、基板１上に形成されたアル
ミニウム（Al）配線２上に、保護膜として膜厚１μｍ程
度の燐珪酸ガラス（PSG:Phospho Silicate Glass）膜３
と膜厚0.3μｍ程度の窒化シリコン（SiN）膜４とが順次
に積層され、そのPSG膜３とSiN膜４のAl配線２上の部分
に形成された開口部５に、バリアメタル層としてのチタ
ン（Ti）層６及びパラジウム層（Pd）７を介して金（A
u）製のバンプ８が形成されている。As shown in FIG. 5 (A), the structure of a semiconductor device manufactured through a conventional bumping process is such that phosphosilicate having a film thickness of about 1 μm is formed as a protective film on an aluminum (Al) wiring 2 formed on a substrate 1. Glass (PSG: Phospho Silicate Glass) film 3
And a silicon nitride (SiN) film 4 having a film thickness of about 0.3 μm are sequentially laminated, and a PSG film 3 and a SiN film 4 are provided with an opening 5 formed in a portion on the Al wiring 2 as a barrier metal layer. Through the titanium (Ti) layer 6 and the palladium layer (Pd) 7, gold (A
u) made of bumps 8 are formed.
かかるバンプ構造では、SiN膜４が耐湿性に優れてい
るので、PSG膜３のピンホールから製造工程で使用する
エッチング液が半導体基板１の表面に浸入し、それに起
因してAl配線２が断線することを防止することができ
る。In such a bump structure, since the SiN film 4 has excellent moisture resistance, the etching solution used in the manufacturing process penetrates into the surface of the semiconductor substrate 1 through the pinholes of the PSG film 3, causing the Al wiring 2 to be disconnected. Can be prevented.
また、上記のエッチング液によるAl配線２の断線を防
止する従来の他の製造方法としては、SiN膜４の代りに
樹脂コーティング層を設けた方法（特開昭58−50756号
公報や特開昭57−89244号公報など）が知られている。As another conventional manufacturing method for preventing the breakage of the Al wiring 2 due to the above etching solution, a method of providing a resin coating layer instead of the SiN film 4 (Japanese Patent Laid-Open No. 58-50756 and Japanese Patent Laid-Open No. 50756/1983). 57-89244, etc.) is known.
このようなバンプ構造製造後、工場においてその信頼
性を試験するために、従来は−15℃〜200℃の温度範囲
で200回程度繰り返し温度を周期的に変化させていた。
また、バンプ８の応力の緩和及び硬度低下のため、400
℃、30分のアニールも行なわれていた。After manufacturing such a bump structure, in order to test its reliability in a factory, conventionally, the temperature was cyclically changed about 200 times in a temperature range of -15 ° C to 200 ° C.
In addition, since the stress of the bump 8 is relaxed and the hardness is lowered, 400
Annealing for 30 minutes at ℃ was also performed.
しかるに、上記の特許公開公報記載の従来の製造方法
では、樹脂コーティング層の耐湿性が十分ではなかった
ため、十分に所期の効果を奏しているとはいえなかっ
た。However, in the conventional manufacturing method described in the above-mentioned patent publication, since the moisture resistance of the resin coating layer was not sufficient, it could not be said that the desired effect was sufficiently exerted.
これに対して、第５図（Ａ）に示したバンプ構造を製
造する従来方法は、樹脂コーティング層に比較してSiN
膜４がはるかに耐湿性に優れているので、エッチング液
によるAl配線２の断線を十分に防止することができる。On the other hand, the conventional method for manufacturing the bump structure shown in FIG.
Since the film 4 has much higher moisture resistance, it is possible to sufficiently prevent disconnection of the Al wiring 2 due to the etching solution.
しかし、その反面、前記した信頼性試験により、金製
のバンプ８が温度変化に追随して収縮するのに対し、Si
N膜４が剛性であるので、第５図（Ｂ）に９で示す如
く、バンプ８のエッジに対応した下地膜の部分にクラッ
クが入り易いという問題点があった。However, on the other hand, according to the above-mentioned reliability test, the gold bump 8 shrinks following the temperature change, whereas
Since the N film 4 is rigid, as shown by 9 in FIG. 5 (B), there is a problem that cracks are easily formed in the portion of the base film corresponding to the edge of the bump 8.
本発明は上記の点に鑑みてなされたもので、バンプ構
造の下地膜のクラックの発生の防止並びに耐湿性の向上
を可能にした半導体装置の製造方法を提供することを目
的とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing the occurrence of cracks in a base film having a bump structure and improving moisture resistance.
本発明の半導体装置の製造方法は、PSG膜及びSiN膜を
積層し、それらに電極配線を臨む開口部を形成する第１
の工程と、SiN膜上に樹脂コーティング層を形成する第
２の工程と、バリアメタル層を形成する第３の工程と、
金メッキによるバンプを形成する第４の工程と、バンプ
をマスクとしてバリアメタル層をエッチング除去する第
５の工程とを含む。A method of manufacturing a semiconductor device according to the present invention is a method of laminating a PSG film and a SiN film and forming an opening facing the electrode wiring therethrough.
Step, a second step of forming a resin coating layer on the SiN film, and a third step of forming a barrier metal layer,
It includes a fourth step of forming bumps by gold plating and a fifth step of etching away the barrier metal layer using the bumps as a mask.
上記の第１乃至第５の工程により半導体表面の電極配
線上に形成されたバンプ構造は、下地膜が電極配線上か
らPSG膜、SiN膜及び樹脂コーティング層の順で積層され
たものとなる。The bump structure formed on the electrode wiring on the semiconductor surface by the above first to fifth steps is such that the base film is laminated on the electrode wiring in the order of the PSG film, the SiN film and the resin coating layer.
樹脂コーティング層は弾力性があり、金製のバンプの
信頼性試験の際の大なる温度変化による収縮を吸収する
作用があり、そのバンプの収縮がSiN膜に伝達されるこ
とを防止することができる。The resin coating layer is elastic and has the function of absorbing the contraction due to a large temperature change during the reliability test of the gold bump, and it is possible to prevent the contraction of the bump from being transmitted to the SiN film. it can.
また、SiN膜がPSG膜上に形成されているので、PSG膜
にピンホールがあったり、耐湿性の不十分な樹脂コーテ
ィング層を使用しても、良好な耐湿性を得ることができ
る。Further, since the SiN film is formed on the PSG film, good moisture resistance can be obtained even if the PSG film has pinholes or a resin coating layer having insufficient moisture resistance is used.
第１図は本発明の第１実施例の各工程説明図を示す。
まず第１図（Ａ）に示す如く、Al製の電極配線12が約１
μｍの膜厚で形成された半導体基板11の表面上に、PSG
膜13とSiN膜14とを保護膜として順次に化学気相成長法
（CVD法）により積層する。SiN膜14の形成は、例えばシ
アン、ホスフィン、酸素よりなる混合ガス下でプラズマ
CVD法により行なえる。保護膜としてPSG膜13を使用する
のは、基板11と同じSiを主成分としているので、半導体
基板11との密着性が良好であることなどによる。また、
SiN膜14は耐湿性向上のために使用される。なお、PSG膜
13の膜厚は1.0μｍ程度、SiN膜14の膜厚は0.3μｍ程度
である。FIG. 1 is an explanatory view of each step of the first embodiment of the present invention.
First, as shown in FIG. 1 (A), the electrode wiring 12 made of Al is about 1
PSG is formed on the surface of the semiconductor substrate 11 having a film thickness of μm.
The film 13 and the SiN film 14 are sequentially laminated by the chemical vapor deposition method (CVD method) as a protective film. The SiN film 14 is formed, for example, by plasma under a mixed gas of cyan, phosphine and oxygen.
It can be done by the CVD method. The PSG film 13 is used as the protective film because it has the same Si as the main component as the substrate 11 as a main component and therefore has good adhesion to the semiconductor substrate 11. Also,
The SiN film 14 is used to improve moisture resistance. In addition, PSG film
The film thickness of 13 is about 1.0 μm, and the film thickness of the SiN film 14 is about 0.3 μm.
次に、第１図（Ｂ）に示す如く、上記のPSG膜13とSiN
膜14とに対して、電極配線12を臨む開口部15をエッチン
グにより形成する。以上が前記第１の工程に相当する。Next, as shown in FIG. 1 (B), the PSG film 13 and SiN
An opening 15 that faces the electrode wiring 12 is formed in the film 14 by etching. The above corresponds to the first step.
次に第１図（Ｃ）に示す如く、上記SiN膜14上にポリ
イミド系樹脂層16を例えば２μｍの厚さで塗布した後熱
処理し、更に電極配線12を臨む開口部17をエッチングに
より形成する（第２の工程）。Next, as shown in FIG. 1C, a polyimide resin layer 16 having a thickness of, for example, 2 μm is applied on the SiN film 14 and then heat-treated, and an opening 17 facing the electrode wiring 12 is formed by etching. (Second step).
次に第１図（Ｄ）に示す如く、後の工程で金メッキを
行なえるようにするため、ポリイミド系樹脂層16上と開
口部17内の電極配線12上とに夫々バリアメタル層18を蒸
着又はスパッタで形成する（第３の工程）。このバリア
メタル層18は膜厚3000Å程度のチタン層（Ti）（後述の
第２図の18a）と、Ti層とAu製のバンプとを接続するた
めの膜厚3000Å程度のパラジウム（Pd）層（後述の第２
図の18b）とよりなる。Next, as shown in FIG. 1 (D), a barrier metal layer 18 is vapor-deposited on the polyimide resin layer 16 and the electrode wiring 12 in the opening 17 so that gold plating can be performed in a later step. Alternatively, it is formed by sputtering (third step). The barrier metal layer 18 is a titanium layer (Ti) with a thickness of about 3000 Å (18a in Fig. 2 to be described later) and a palladium (Pd) layer with a thickness of about 3000 Å for connecting the Ti layer and the Au bump. (Second described below
18b) in the figure.
次に第１図（Ｅ）に示す如く、電極配線12上方の部分
を除いてバリアメタル層18上にフォトレジスト層19を形
成し、このフォトレジスト層19をマスクとして金メッキ
を施し、Au製のバンプ20を形成する（第４の工程）。Next, as shown in FIG. 1 (E), a photoresist layer 19 is formed on the barrier metal layer 18 except for the portion above the electrode wiring 12, and gold plating is performed using this photoresist layer 19 as a mask. The bumps 20 are formed (fourth step).
しかる後に、第１図（Ｆ）に示す如く、フォトレジス
ト層19を除去した後、バンプ20をマスクとしてエッチン
グ液を用いてバリアメタル層18を選択除去する（第５の
工程）。バリアメタル層18を形成するPd層のエッチング
にはエッチング液として例えば王水を用い、またTi層の
エッチングには例えばふっ酸（HF）を含んだ水溶液を用
いる。Thereafter, as shown in FIG. 1 (F), after removing the photoresist layer 19, the barrier metal layer 18 is selectively removed using an etching solution with the bumps 20 as a mask (fifth step). For example, aqua regia is used as an etching solution for etching the Pd layer forming the barrier metal layer 18, and an aqueous solution containing hydrofluoric acid (HF) is used for etching the Ti layer.
ここで、このウェットエッチングの際、SiN膜14によ
りAl製電極配線12へ上記のエッチング波が染み込んでし
まうことを防止することができる。Here, at the time of this wet etching, it is possible to prevent the above-mentioned etching wave from soaking into the Al-made electrode wiring 12 by the SiN film 14.
このようにして、本実施例によれば第２図に示す如き
バンプ構造の半導体装置を製造することができる。な
お、第２図中18aはTi層、18bはPd層である。Au製のバン
プ20とAlとAuのバリアメタル層であるTi層18aとは接着
できないので、Pd層18bが介在される。Thus, according to this embodiment, a semiconductor device having a bump structure as shown in FIG. 2 can be manufactured. In FIG. 2, 18a is a Ti layer and 18b is a Pd layer. Since the bump 20 made of Au and the Ti layer 18a which is a barrier metal layer of Al and Au cannot be adhered to each other, the Pd layer 18b is interposed.
本実施例によれば、信頼性試験の際の温度変化による
クラックの発生はポリイミド系樹脂層16により防止でき
ると共に、前記した特許公開公報記載のものに比べてSi
N膜14により良好な耐湿性が得られる。According to the present embodiment, the occurrence of cracks due to temperature changes during the reliability test can be prevented by the polyimide resin layer 16, and compared with the one described in the patent publication described above Si.
Good moisture resistance can be obtained by the N film 14.
しかし、本実施例では、第２図からわかるように、樹
脂コーティング層であるポリイミド系樹脂層16の一部が
電極配線12に接触しており、ポリイミド系樹脂層16を介
してエッチング液が電極配線12側に僅かに浸入する。However, in this embodiment, as can be seen from FIG. 2, a part of the polyimide resin layer 16 which is the resin coating layer is in contact with the electrode wiring 12, and the etching solution is applied to the electrode through the polyimide resin layer 16. It slightly penetrates the wiring 12 side.
本発明の第２実施例は、上記の第１実施例よりも更に
耐湿性を向上させたもので、次に第３図及び第４図と共
にその説明をする。第３図は本発明の第２実施例の要部
の工程説明図で、同図（Ａ），（Ｂ）は前記第２の工程
に相当し、同図（Ｃ）は前記第３の工程に相当し、それ
以外の各工程は第１実施例と同様である。また第３図
中、第１図と同一構成部分には同一符号を付し、その説
明を省略する。The second embodiment of the present invention has further improved moisture resistance as compared with the first embodiment described above, and will be described below with reference to FIGS. 3 and 4. 3 (A) and 3 (B) correspond to the second step, and FIG. 3 (C) shows the third step. The other steps are the same as those in the first embodiment. Further, in FIG. 3, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.
第３図（Ａ）に示す如く、開口部15を有するSiN膜14
上にポリイミド系樹脂層16が例えば２μｍの膜厚で塗布
された後熱処理される。次に第３図（Ｂ）に示す如くエ
ッチングにより開口部15内及び開口部15の上方のポリイ
ミド系樹脂層16を開口部15より大なる径範囲で除去する
ことにより、開口部15を再び形成すると共に、ポリイミ
ド系樹脂層16に開口部15より大なる径の開口部21を形成
する。As shown in FIG. 3 (A), a SiN film 14 having an opening 15 is formed.
The polyimide resin layer 16 is applied on top of it to a film thickness of, for example, 2 μm, and then heat-treated. Next, as shown in FIG. 3 (B), the polyimide resin layer 16 in the opening 15 and above the opening 15 is removed by etching in a diameter range larger than the opening 15 to form the opening 15 again. At the same time, the opening 21 having a diameter larger than that of the opening 15 is formed in the polyimide resin layer 16.
次に第３図（Ｃ）に示す如く、ポリイミド系樹脂層16
上と開口部15及び21内と電極配線12上に、開口部15及び
21を夫々埋め込まないよう、6000Å程度の膜厚のバリア
メタル層22を蒸着又はスパッタで形成する。Next, as shown in FIG. 3 (C), the polyimide resin layer 16
Above the openings 15 and 21 and above the electrode wiring 12, the openings 15 and
A barrier metal layer 22 having a film thickness of about 6000Å is formed by vapor deposition or sputtering so as not to embed each 21.
しかる後に、第１図（Ｅ），（Ｆ）に示した第4,第５
の工程を経ることにより、第４図に示す如きバンプ構造
を持つ半導体装置が製造される。ここで、第４図中、22
aはTi層、22bはPd層で、第３図（Ｃ）に示したバリアメ
タル層22を構成しており、各々の膜厚は3000Å程度であ
る。After that, the fourth and fifth parts shown in FIGS. 1 (E) and (F)
Through the steps of, a semiconductor device having a bump structure as shown in FIG. 4 is manufactured. Here, in FIG. 4, 22
a is a Ti layer and 22b is a Pd layer, which constitute the barrier metal layer 22 shown in FIG. 3 (C), and each film thickness is about 3000 Å.
本実施例によれば、第４図からわかるように、ポリイ
ミド系樹脂層16は直接に電極配線12に接触しないので、
耐湿性が不十分なポリイミド系樹脂層16を通してエッチ
ング液が電極配線12に浸入してしまうことは全くなく、
耐湿性を極めて向上することができる。According to this embodiment, as can be seen from FIG. 4, since the polyimide resin layer 16 does not directly contact the electrode wiring 12,
The etching solution never penetrates into the electrode wiring 12 through the polyimide resin layer 16 having insufficient moisture resistance,
The moisture resistance can be extremely improved.
上述の如く、本発明によれば、Au製のバンプの温度変
化に伴う収縮がSiN膜に伝達されることを樹脂コーティ
ング層によって防止できるため、温度変化によるバンプ
構造の下地膜のクラックの発生を未然に防止することが
でき、またSiN膜により良好な耐湿性を得ることができ
るため、エッチング液が電極配線に侵入して断線させて
しまうことを防止できる等の特長を有するものである。As described above, according to the present invention, since the resin coating layer can prevent the contraction due to the temperature change of the Au bump from being transferred to the SiN film, the occurrence of cracks in the underlying film of the bump structure due to the temperature change can be prevented. Since it can be prevented in advance and good moisture resistance can be obtained by the SiN film, it has features such as preventing the etchant from penetrating into the electrode wiring and breaking it.
第１図は本発明の第１実施例の各工程説明図、 第２図は本発明の第１実施例により製造された半導体装
置を示す図、 第３図は本発明の第２実施例の各工程説明図、 第４図は本発明の第２実施例により製造された半導体装
置を示す図、 第５図は従来の半導体装置の一例の構成図である。 図において、 11は半導体基板、 12はAl製電極配線、 13はPSG膜、 14はSiN膜、 15,17,21は開口部、 16はポリイミド系樹脂層、 18,22はバリアメタル層、 20はAu製のバンプ を示す。FIG. 1 is an explanatory view of each step of the first embodiment of the present invention, FIG. 2 is a view showing a semiconductor device manufactured by the first embodiment of the present invention, and FIG. 3 is a second embodiment of the present invention. FIG. 4 is a diagram showing each process, FIG. 4 is a diagram showing a semiconductor device manufactured according to the second embodiment of the present invention, and FIG. 5 is a configuration diagram of an example of a conventional semiconductor device. In the figure, 11 is a semiconductor substrate, 12 is an electrode wiring made of Al, 13 is a PSG film, 14 is a SiN film, 15, 17 and 21 are openings, 16 is a polyimide resin layer, 18, 22 is a barrier metal layer, 20 Indicates a bump made of Au.
Claims (1)
PSG膜（13）及びSiN膜（14）を順次に積層した後、該PS
G膜（13）及びSiN膜（14）に対して該電極配線（12）を
臨む開口部（15）を形成する第１の工程と、 該第１の工程を経た該SiN膜（14）上を覆い、かつ、開
口部（15,17）を介して該電極配線（12）を臨むように
樹脂コーティング層（16）を形成する第２の工程と、 該樹脂コーティング層（16）及び該開口部（15,17）に
臨む該電極配線（12）上にバリアメタル層（18,22）を
形成する第３の工程と、 該電極配線（12）上の該バリアメタル層（18,22）を介
して金メッキによるバンプ（20）を形成する第４の工程
と、 該バンプ（20）をマスクとして該バリアメタル層（18,2
2）をエッチング除去する第５の工程と、 を含むことを特徴とする半導体装置の製造方法。1. A semiconductor surface on which electrode wiring (12) is formed
After sequentially stacking the PSG film (13) and the SiN film (14), the PS
A first step of forming an opening (15) facing the electrode wiring (12) on the G film (13) and the SiN film (14), and on the SiN film (14) that has undergone the first step And a second step of forming a resin coating layer (16) so as to cover the electrode wiring (12) through the openings (15, 17), and the resin coating layer (16) and the opening. Third step of forming a barrier metal layer (18, 22) on the electrode wiring (12) facing the portion (15, 17), and the barrier metal layer (18, 22) on the electrode wiring (12) A fourth step of forming a bump (20) by gold plating through the barrier metal layer (18, 2) using the bump (20) as a mask.
A fifth step of etching away 2), and a method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62306378A JPH0812861B2 (en) | 1987-12-03 | 1987-12-03 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62306378A JPH0812861B2 (en) | 1987-12-03 | 1987-12-03 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01146342A JPH01146342A (en) | 1989-06-08 |
| JPH0812861B2 true JPH0812861B2 (en) | 1996-02-07 |
Family
ID=17956315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62306378A Expired - Fee Related JPH0812861B2 (en) | 1987-12-03 | 1987-12-03 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0812861B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3794403B2 (en) | 2003-10-09 | 2006-07-05 | セイコーエプソン株式会社 | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5850756A (en) * | 1981-09-19 | 1983-03-25 | Ricoh Elemex Corp | Forming method for bump |
| JPS61241932A (en) * | 1985-04-19 | 1986-10-28 | Hitachi Ltd | Semiconductor device and its manufacture |
-
1987
- 1987-12-03 JP JP62306378A patent/JPH0812861B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01146342A (en) | 1989-06-08 |
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