JPH08124303A - Bit rate detection circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] An object of the present invention is to provide a bit rate detection circuit capable of detecting accurate bit rate information even for a signal in which intersymbol interference occurs. The rate detection unit 5 selects an integer value n from the output values of the cycle detection circuit 2 that measures the inversion cycle of the digitally modulated reproduction signal, and selects n from the output values of the cycle detection circuit 2.
Calculate one part. The control unit 6 corrects the output of the cycle detection circuit 2 by n and outputs it as a bit rate detection output 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit rate detecting circuit used in a digital tape recorder or the like.

[0002]

2. Description of the Related Art In recent years, devices for recording and reproducing digital signals have been used in a wide variety of fields such as floppy disks and hard disks for computers, compact disks for recording and reproducing PCM signals, and digital tape recorders. These devices use a clock extraction circuit for identifying and reproducing a signal reproduced from a recording medium as digital data.

Such a clock extraction circuit normally operates normally within a range of ± several percent of a presumed center frequency, and when the frequency of the reproduced signal is further deviated, the data is extracted. Cannot be played. Even in such a case, in order to read the data normally, the processing of detecting the bit rate information from the reproduced signal and moving the center frequency of the clock extraction circuit in accordance with it is performed.

FIG. 5 is a block diagram of a conventional bit rate detecting circuit. In FIG. 5, 1 is an input terminal to which a reproduction signal is input, 7 is a bit rate detection output, 12
Is a band pass filter, and 13 is a period detection circuit. The operation of the conventional bit rate detection circuit configured as described above will be described with reference to the drawings.

When the reproduction signal is input to the input terminal 1, the bandpass filter 12 extracts only the signal of a specific frequency contained in the input signal. Taking a digital tape recorder (hereinafter abbreviated as DAT) used for audio as an example, in the recorded signal, a signal near 130 kHz for servo is included in addition to a signal for normal audio data. Band pass filter 12
And the cycle of this signal is detected by the cycle detection circuit 13. Based on the detected period information, in this case 72
The bit rate information is calculated by doubling and output as the bit rate detection output 7.

[0006]

However, in the above-mentioned conventional configuration, it is possible to detect when a signal of a specific frequency is recorded in the recording signal, but it cannot be used when it is not. Therefore, it is considered to detect the bit rate information from the recorded audio signal.

Taking DAT as an example, a signal to be recorded / reproduced on / from a tape is recorded according to a modulation rule of 8-10 modulation. This modulated recording signal has a bit rate of 9.4.
Inversion interval is 1 / 9.4M = 106n for MBPS
S is 1T, and 4 times the length from 1T 4T = 425
It is composed of a combination of nS.

FIG. 6 shows an example of a signal waveform created by the above-mentioned modulation rule. In FIG. 6, 14 is a reference clock waveform, 15 is an example of a modulated signal waveform, 16 is an example of a reproduced signal waveform when the waveform of the modulated waveform 15 is recorded and reproduced, and 17 is for determining the reproduced waveform 16. Is a determination threshold value of. The modulation waveform 15 is formed by irregularly combining signals having a length of 1T to 4T. When recording such a modulated signal on a recording medium such as a tape, usually, in order to increase the recording density,
Since the data is recorded in the very narrow band, a slightly distorted reproduced waveform such as 16 can be obtained due to the influence of the band limitation and the waveform distortion. A closer look at the reproduced waveform 16 and the modulated waveform 15 reveals that even if the reproduced waveform 16 is judged to be 0 or 1 by the judgment threshold value 17, the position is slightly deviated. As a result, the time of each inversion interval varies.

The graph 18 shown in FIG. 7 is a measurement of the appearance probability of the inversion interval of the 8-10 modulated recording / reproducing signal. Peaks of the appearance probability occur at each of 1T to 4T. Therefore, these peaks are measured, and the part corresponding to 1T is used as it is, the time interval of 2T is halved, 3T is ⅓, and 4T is ¼.
If it is used, the same period information can be obtained, and the bit rate can be detected based on this information.

However, when such a modulated signal is used for bit rate detection, a large error occurs when the reproduced waveform is distorted due to the non-linearity of the recording / reproducing system, intersymbol interference between signals and the like. May occur. Intersymbol interference causes a difference in the length of 1T after 3T and the length of 1T when 1T continues. As a result, the distribution of the inversion interval deviates from the distribution of the accurate period, and 1T is 1
If it becomes 0% longer, the measured bit rate information will be shifted by 10%, and if a signal having such a large error is added as the center frequency information to the clock extraction circuit, the reproduction of the signal will be reproduced. There is a problem that it may not be possible.

The present invention solves the above-mentioned problems of the prior art, and even for a signal in which intersymbol interference occurs,
An object of the present invention is to provide a bit rate detection circuit that can detect accurate bit rate information.

[0012]

In order to achieve this object, a bit rate detecting circuit of the present invention comprises a cycle detecting section for measuring an inversion cycle of a reproduced signal which is digitally modulated,
A rate detection unit that selects an integer value n from the output of the cycle detection unit and calculates 1 / n of the output value of the cycle detection unit, and a control unit that corrects and outputs the output of the cycle detection unit by n,
The output of the control unit is configured to be a bit rate output.

[0013]

According to the present invention, the bit rate information is detected on the basis of a plurality of pieces of period information with the above configuration, so that accurate information can be obtained even when intersymbol interference occurs.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a bit rate detection circuit according to the first embodiment of the present invention. FIG.
1, 1 is an input terminal, 2 is a period detection circuit, 3 is a detection window circuit for determining the period, 4 is a divider for calculating 1/2,
Reference numeral 5 is a rate detection unit, 6 is a control unit, 61 and 62 are correction circuits, 63 is a selection circuit, and 7 is a bit rate detection output.

A reproduction signal such as the reproduction waveform 16 shown in FIG. 6 is input to the input terminal 1. In the cycle detection circuit 2, the reproduction signal is discriminated to be 0 or 1 with an appropriate threshold value and each duration is measured. The measured time information becomes data having a distribution like the graph 18 in FIG. 7. The output of the cycle detection circuit 2 is input to the rate detection unit 5.

The rate detection section 5 is composed of a detection window circuit 3 and a divider 4, and the output of the cycle detection circuit 2 is first discriminated by the detection window circuit 3 as a signal from 1T to 4T. . The input time data of the detection window circuit 3 is 106 nS.
If it is near 1T, if it is near 212nS, it is 2T. In the case of 1T, the output of the detection window circuit 3 is unchanged, and in the case of 2T, it is halved by the divider 4 and output to the control unit 6. Although only 1T and 2T are used here and the others are not used, it is also possible to use all information, and in this case, n is used.
The data of T is divided by n and output.

The control unit 6 inputs the data determined to be 1T by the rate detection unit 5 to the correction circuit 61 and creates 0.9 times the data, for example. Similarly, for the data determined to be 2T by the rate detection unit 5, the correction circuit 62
To input 1.1 times the data. The data thus corrected is selected by the selection circuit 63 for the current bit rate information and is output as the bit rate detection output 7. If high speed response is not required, the correction circuit 6
The outputs of 1 and 62 may be averaged and output to the bit rate detection output 7. As the output format of the bit rate detection output 7, period information may be output, or frequency information which is the reciprocal thereof may be output.

As described above, according to this embodiment, it is possible to provide a bit rate detecting circuit capable of detecting accurate bit rate information even for a signal in which intersymbol interference is occurring. it can.

Next, FIG. 2 is a block diagram of a bit rate detecting circuit in the second embodiment of the present invention. In FIG. 2, reference numeral 106 is a control unit, 64 is a gate circuit, and 65 is a selective averaging circuit. Others are the same as those in FIG.

A reproduction signal of 8-10 modulation when a normal audio signal is recorded has an appearance probability of 1T as shown schematically in the graph 18 of FIG.
May have characteristics of 60%, 2T is 35%, and other 5%. And the inversion interval of 1T is 5
%, The 2T inversion interval tends to be measured as short as 3%. Utilizing this appearance probability, 1T,
It is possible to correct the measurement result of the inversion interval of 2T.

The signal detected as 1T by the rate detector 5 is measured 5% longer than it actually is. The signal detected as 2T is measured 3% shorter. Therefore, even if these measurement results are averaged as they are, 1T with high appearance probability
The result is that the average value moves to the side, and in this case, it moves to the side that is about 2% longer.

On the other hand, considering the correction of the appearance probability,
If the gate 64 is added and the detection result on the 1T side is used, for example, every other time, the result of the above averaging is 0.7% longer, and a more accurate average is obtained. The value is obtained. The feature of this circuit is that the inversion interval information can be corrected as a result by using the appearance probability of the reproduced signal, and it is possible to obtain accurate bit rate information with a very simple circuit. is there. Therefore, by changing the number of adoptions according to the deviation width of the measured value of the inversion interval of the reproduction signal and the occurrence probability of the signal of each length, the characteristics of the recording and reproduction system can be improved when other modulation methods are used. The present invention can be applied to different cases.

Next, FIG. 3 is a block diagram of a bit rate detecting circuit in the third embodiment of the present invention. In FIG. 3, 205 is a rate detection unit, 30 is a detection window circuit, and 20
6 is a control unit, 66 is a selection storage circuit, and the others are the same as those in FIG.

When external vibration or shock is applied to the playback device, the moving speed of the recording medium changes, and the signal frequency input to the input terminal 1 may be a value far from the normal value. In such a case, if the bit rate detection circuit cannot follow accurately, it becomes impossible to read the recorded data. When the value obtained as the output of the cycle detection circuit 2 is 150 nS or 70 nS at 1T, a detection window corresponding to this shifted cycle is required. Generally, the speed fluctuation of the recording medium is detected by some sensor,
It may be possible to use the information for correction of the detection window, but this is not desirable because an additional circuit such as a sensor is required for that purpose. Therefore, consider a bit rate detection circuit that can cope with large fluctuations.

The inversion interval information measured by the cycle detection circuit 2 is input to the rate detection unit 205. Rate detector 2
Reference numeral 05 is composed of a detection window circuit 30 capable of changing its detection threshold value under the control of the outside, and a division circuit 4. The output of the rate detector 205 is the controller 2
Then, the bit rate detection output 7 is obtained from the control unit 206. The bit rate detection output 7 thus obtained is also connected to the detection window circuit 30 and used to control the detection threshold value.

In the normal reproduction state, since the bit rate information indicating the standard 1 × state is output to the bit rate detection output 7, the operation is the same as in the case of FIG.

When the frequency of the reproduced signal starts to shift due to some factor, bit rate information following the input signal is output to the bit rate detection output 7. According to this information, the detection window circuit 30 shortens the time threshold value for detecting each T in proportion to the frequency fluctuation when the input frequency becomes high. As a result, for example, a 2T signal is converted to 3
It is possible to prevent making a mistake with T.

When the control unit 206 has an averaging circuit as shown by 106 in FIG. 2, a relatively large detection delay occurs in the bit rate detection output 7, and it becomes impossible to follow a rapid change in the input signal. . Therefore, when high-speed response is required, it is necessary to shorten the response time of the control unit 206 as much as possible. Therefore, the selective storage circuit 66 holds the previous cycle detection result and uses the output as the bit rate detection output 7 to enable a very high-speed response.

Next, FIG. 4 is a block diagram of a bit rate detecting circuit in the fourth embodiment of the present invention. In FIG. 4, reference numeral 306 is a control unit, 67 is a range limiting circuit, and 68 is an averaging circuit. The other parts are the same as those in FIG.

The range limiting circuit 67 is provided so that the detected bit rate does not deviate significantly from the normal value.

When only one inversion interval is observed,
When the signal of 3T is shortened by 25% and the signal of 2T is 2
It is indistinguishable from a signal that is 5% longer. Therefore, it is very dangerous to generate the bit rate detection output 7 that is largely deviated from the normal value, and it may be a basis for causing the determination error such as 3T and 2T described above.
Therefore, in the range limiting circuit 67, when the measured cycle information is, for example, about ± 20% or more of the normal value, the maximum value within the range is set as a value relatively close to the normal value and the rate detection unit is set. Output to 205. This operation is important for stable operation of the bit rate detection circuit.

The averaging circuit 68 is equivalent to a low-pass filter for reducing the noise component of the bit rate detection output to be output to the outside, and the very fast fluctuation of the reproduction signal period causes
This is effective for preventing the bit rate output from fluctuating.

In FIG. 4, the signal not passing through the range limiting circuit 67 is output to the outside as the bit rate detection output 7, but it goes without saying that the output of the range limiting circuit 67 may be used. .

As a practical circuit, the cycle detection circuit 2 counts cycles with a high-speed clock, and the count value represents the duration. If the counted value corresponds to 1T at 50, for example, the detection window circuit determines 1T if the counted value is between 40 and 60, and 8
From 0 to 120, 2T is determined. In addition to this, if the information that the bit rate detection output is 1.1 times the frequency is output, the time threshold for the 1T determination is 36 to 5
Change during 5. Similarly, the detection window of 2T is changed from 72 to 11
Change between 0. As a result, accurate cycle information can be obtained, and the operating range of the bit rate detection circuit can be expanded.

[0035]

As described above, according to the present invention, accurate bit rate information can be detected even from a distorted reproduced signal, and even when the bit rate fluctuates greatly, it is possible to accurately follow it. It becomes possible to play,
Very useful for practical purposes.

[Brief description of drawings]

FIG. 1 is a block diagram of a bit rate detection circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a bit rate detection circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a bit rate detection circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a bit rate detection circuit according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a conventional bit rate detection circuit.

FIG. 6 is a schematic explanatory diagram of recording / reproducing waveforms.

FIG. 7 is a graph showing the probability of occurrence of inversion intervals.

[Explanation of symbols]

 1 Input Terminal 2 Period Detection Circuit 3,30 Detection Window Circuit 4 Divider 5,205 Rate Detection Unit 6,106,206,306 Control Unit 7 Bit Rate Detection Output 12 Band Pass Filter 13 Period Detection Circuit 14 Clock Waveform 15 Modulation Waveform 16 Reproduced waveform 17 Judgment threshold 18 Appearance probability 61,62 Correction circuit 63 Selection circuit 64 Gate 65 Selection averaging circuit 66 Selection storage circuit 67 Range limiting circuit 68 Averaging circuit

Claims (5)

[Claims] 1. A cycle detecting section for measuring an inversion cycle of a digitally modulated reproduction signal, and an integer value n is selected from an output of the cycle detecting section to obtain 1 / n of an output value of the cycle detecting section. A bit rate detection circuit comprising a rate detection unit for calculation and a control unit for correcting and outputting the output of the cycle detection unit by the n. 2. A reproduced signal which is 8-10 modulated,
The control unit corrects the measured value shortly for n = 1, and n = 2
The bit rate detection circuit according to claim 1, wherein the bit rate is corrected for a long time. 3. A reproduced signal which is 8-10 modulated,
The control unit thins out and adopts the measured value for n = 1.
The bit rate detection circuit according to claim 1, which is adopted as it is for = 2. 4. The bit rate detection circuit according to claim 1, wherein the rate detection unit changes a reference value for selecting n based on the detected bit rate information. 5. The bit rate detection circuit according to claim 1, wherein the control unit includes a circuit for limiting a range of detection output.