JPH08115920A - Semiconductor device, and its manufacture - Google Patents

Abstract

PURPOSE: To prevent the diffusion of dopant to an insulating film around an emitter, and dispense with the reformation of an insulating film around the emitter, and further, facilitate the removal of the needless part of a base electrode film. CONSTITUTION: A collector layer 2, a base layer 3, an emitter layer 4, a first WSi film 5, and an Al film 6, a second WSi film 7 are made in order on a semiconductor substrate, and then each layer 4-7 is partially etched anisotropically to form a groove, and this groove is stopped with a second insulating film 9. Then, using a resist over in size than an insulating film 9 as a mask, only each layer 4-7 outside the insulating film 9 is removed, and a solid-phase diffusion source is made all over the surface. Furthermore, with the thermally flagged resist as a mask, a solid-phase diffusion source is removed partially, and a processed solid-phase diffusion source 14 is made. After a third insulating film 15 is made all over the surface, a high-carrier concentration area 16 is made by heat treatment. After that, the third insulating film 15 and the solid-phase diffusion source 14 are removed, and a base electrode film is made all over the surface, and a needless part is removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically, a process of increasing the carrier concentration in a base electrode contact portion by a diffusion method using a solid phase diffusion source. And a semiconductor device having such a structure. In particular, the present invention is suitable as a technology for bipolar transistors.

[0002]

42 to 54 are sectional views showing steps in a conventional method for manufacturing a semiconductor device. In these figures, 1P is a semiconductor substrate, 2P is a collector layer, 3P is a base layer, 4P is an emitter layer, 5P is a first WSi film, 8P is a first resist, 11P is a solid phase diffusion source, and 16P is diffusion. A high carrier concentration region formed by, 17P is a base electrode film, 18P is a fourth resist, 20P is a first insulating film, 21P is a second WSi film,
23P is a first side wall, 24P is a first side wall after the dopant is diffused, 25P is a second side wall, and 26 is a first WSi film whose surface is roughened by ion milling.

Each manufacturing process will be described below with reference to the drawings. First, the collector layer 2 is formed on the upper surface of the semiconductor substrate 1.
P, base layer 3P, emitter layer 4P, first WSi film 5
P, the first insulating film 20P, and the second WSi film 21P are sequentially formed (FIG. 42).

Next, after patterning the first resist 8P (FIG. 43), the second WSi film 21P, the first insulating film 20P, and the first resist 8P after the patterning are used as a mask. The WSi film 5P is dry-etched using a gas containing SF ₆ and CHF ₃ , for example (FIG. 44). Further, using the first resist 8P as a mask, the emitter layer 4P is etched by, for example, dry etching with Cl ₂ gas or wet etching with tartaric acid to expose a part of the upper surface of the base layer 3P (FIG. 4).
5).

Next, an insulating film is formed on the entire surface, and first sidewalls 23P are formed by anisotropic etching (FIG. 46).

Further, after the solid phase diffusion source 11P is formed on the entire surface (FIG. 47), heat treatment is performed to form the high carrier concentration region 16P in the base layer 3P. At this time, since the diffusion of the dopant from the solid-phase diffusion source 11P proceeds isotropically, the dopant diffuses into the first sidewall 23P and immediately below it (FIG. 48).

Next, the solid-phase diffusion source 11P and the first sidewall 24P in which the dopant is diffused are removed by wet etching using HF, for example (FIG. 49). At this time, the first insulating film 20P and the second WSi film 21P are also removed.

Further, after forming the second sidewall 25P (FIG. 50), the base electrode film 17P is formed on the entire surface (FIG. 51).

Next, the required portion of the base electrode film 17P is removed by the resist patterning and heat treatment to form the fourth resist 1.
It is covered with 8P (FIG. 52), and unnecessary portions of the base electrode film 17P are removed by ion milling using Ar ions (FIG. 53). At this time, the surface of the first WSi film 5P is etched by the ions.

Thereafter, the fourth resist 18P is removed (FIG. 54), and thereafter, a semiconductor device is manufactured through predetermined steps.

[0011]

As described above, in the conventional semiconductor device and the manufacturing method thereof, the insulating film (sidewall) itself formed around the emitter layer is used as the mask of the solid phase diffusion source. The dopant also diffuses into the insulating film. Therefore, in terms of reliability, it was necessary to remove the insulating film after the diffusion of the dopant and then form the insulating film again around the emitter layer.

Further, since the side surface of the insulating film is a curved surface, the unnecessary portion is likely to remain when the unnecessary portion of the base electrode is removed, and the remaining portion causes a short circuit between the emitter electrode and the base electrode. There is also a problem that

The present invention has been made in order to solve the above problems, and self-aligns a high carrier concentration without diffusing a dopant into the insulating film covering the periphery of the emitter layer. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which enables formation of a region, and also allows easy removal of an unnecessary portion of a base electrode, and a semiconductor device manufactured by the manufacturing method.

[0014]

The invention according to claim 1 is
A method of manufacturing a semiconductor device, comprising: a first step of sequentially forming a collector layer and a base layer on a semiconductor substrate; and a step of sequentially forming an emitter layer and an emitter electrode film on a part of an upper surface of the base layer. 2 steps, a third step of forming a plate-shaped insulating film whose side surface is perpendicular to the upper surface of the base layer on the peripheral surface of the emitter layer and the emitter electrode film, and exposure after the third step A fourth step of forming a solid phase diffusion source containing a dopant on the entire surface, and a fifth step of coating a necessary portion of the solid phase diffusion source formed on the upper surface of the base layer with a resist, After etching the solid phase diffusion source using the resist as a mask, the resist is removed.
And a seventh step of forming a new insulating film on the entire surface exposed by the sixth step, a high carrier concentration region is formed in the base layer by heat treatment, and then the new insulating film and the solid film are formed. An eighth step of sequentially removing the phase diffusion source.

The invention according to claim 2 is the method for manufacturing a semiconductor device according to claim 1, wherein the base electrode film is formed on the entire surface exposed by the eighth step, and the base electrode is formed. A tenth step of covering a necessary portion of the film formed on the upper surface of the base layer with a new resist, and an eleventh step of etching an unnecessary portion of the base electrode film using the new resist as a mask; Further equipped.

The invention according to claim 3 is the method for manufacturing a semiconductor device according to claim 2, wherein the fifth step is a portion of the solid phase diffusion source formed only on the upper surface of the base layer. A step of forming a resist pattern on the upper surface of the substrate, and a step of reflowing the resist pattern by a first heat treatment to form the resist that covers the necessary portion, and the tenth step includes the step of forming the base electrode film. And a step of forming a new resist pattern on the upper surface of the necessary portion therein, and a step of reflowing the resist pattern by a second heat treatment to form the resist covering the necessary portion.

The invention according to claim 4 is the method for manufacturing a semiconductor device according to any one of claims 1 to 3.
The second step includes a step of sequentially forming the emitter layer and the emitter electrode film on the entire upper surface of the base layer, and a step above the upper surface of the emitter electrode film and perpendicular to the upper surface of the base layer. A step of forming a first resist having two openings provided with side surfaces, and the emitter electrode film and the emitter layer are sequentially anisotropically etched using the first resist as a mask to form the base layer. A step of forming two trench portions having side surfaces perpendicular to the upper surface, the third step includes a step of filling the two trench portions with the insulating film, and a step of removing the first resist. Then, a step of forming a second resist covering the upper surface of the insulating film above the upper surface of the emitter electrode film,
Wet etching the emitter electrode film and the emitter layer sequentially using the second resist as a mask.

The invention according to claim 5 is the method for manufacturing a semiconductor device according to claim 4, wherein the trench portion in the second step is formed by exposing a part of an upper surface of the base layer. It is formed by anisotropically etching the emitter layer.

The invention according to claim 6 is the method of manufacturing a semiconductor device according to claim 4, wherein the anisotropic etching of the emitter layer in the trench portion forming step of the second step is completely performed. This is achieved by leaving the emitter layer by a depleting thickness.

The invention according to claim 7 is the method for manufacturing a semiconductor device according to claim 3, wherein in the second step, the emitter layer and the emitter electrode film are sequentially formed on the entire upper surface of the base layer. And a step of sequentially forming a first insulating film and an uppermost layer film on the entire upper surface of the emitter electrode film, and forming a first resist on a part of the upper surface of the uppermost layer film. And a step of anisotropically etching the uppermost layer film, the first insulating film, the emitter electrode film, and the emitter layer in sequence using the first resist as a mask to form a part of the upper surface of the base layer. And a step of forming a second insulating film on the entire surface exposed by the second step, and a step of exposing the uppermost layer film and the upper surface of the base layer in the third step. The second insulating film is anisotropically etched. Removing the uppermost layer film, the first insulating film, the emitter electrode film, and forming sidewalls as the insulating film on each side surface of the emitter layer. , A step of removing the new insulating film together with the uppermost layer film, and a step of removing the solid phase diffusion source.

According to an eighth aspect of the present invention, in a semiconductor device, a collector layer, a base layer, an emitter layer and an emitter which are all manufactured by the method for manufacturing a semiconductor device according to any one of the second to seventh aspects. An electrode film, a plate-shaped insulating film formed on both peripheral surfaces of the emitter layer and the emitter electrode film, and having a side surface perpendicular to the upper surface of the base layer,
A base electrode film sandwiching the insulating film and a high carrier concentration region formed in the base layer, which is a lower portion of the base electrode film, are provided.

According to a ninth aspect of the present invention, in a semiconductor device having a high carrier concentration region formed below a base electrode contact portion by a diffusion method using a solid phase diffusion source,
It has a plate-shaped insulating film formed on the peripheral surface of the emitter layer and having a side surface perpendicular to the upper surface of the semiconductor substrate, and the high carrier concentration region is formed in self-alignment with the emitter layer. .

According to a tenth aspect of the present invention, in the semiconductor device according to the ninth aspect, the depleted emitter layer is provided immediately below the insulating film.

[0024]

In the invention according to claim 1, the solid phase diffusion source is formed in the exposed surface on the upper surface of the emitter electrode film, the exposed surface of the insulating film and the exposed surface of the upper surface of the base layer by the fourth step. Then, in the fifth step, a resist is formed on the required portion of the solid phase diffusion source. As a result, the solid phase diffusion source formed on the upper surface of the emitter electrode film and on the upper surface / side surface of the insulating film is exposed as an unnecessary portion, and the unnecessary portion is removed by the etching in the sixth step. Therefore, a groove or a gap is formed between the insulating film and the necessary portion of the solid phase diffusion source. Then, the groove portion is filled with a new insulating film formed in the seventh step. Therefore, the solid phase diffusion source on the upper surface of the base layer is isolated from the insulating film around the emitter layer by the new insulating film.

Therefore, when heat treatment is applied in the eighth step, the dopant isotropically diffuses from the solid phase diffusion source,
The diffusion of the dopant extends into the base layer below the solid phase diffusion source, the new insulating film, and the base layer below the new insulating film. However, the dopant does not diffuse into the insulating film due to the inclusion of the new insulating film. This allows
A high carrier concentration region is formed in the base layer in a self-aligned manner.

In the invention according to claim 2, the upper surface of the base layer, the insulating film, and the upper surface of the emitter electrode film are exposed in the eighth step, and in the ninth step, the base electrode film is exposed on these exposed surfaces. Is formed. However, since the side surface of the insulating film is perpendicular to the base layer, the base electrode film is formed only on the upper surface of the base layer, the upper surface of the insulating film, and the upper surface of the emitter electrode film. Of these, the base electrode film formed on the upper surface of the insulating film and the upper surface of the emitter electrode film becomes an unnecessary portion. Therefore, in the tenth step, a new resist is formed only on the upper surface of the base electrode film formed on the upper surface of the base layer.
Therefore, by the etching in the eleventh step, only the unnecessary portion of the base electrode film not covered with the new resist is etched, and the necessary portion remains without being etched due to the presence of the new resist.

In the invention according to claim 3, in the fifth step, a resist pattern is formed on a part of the upper surface of the portion of the solid phase diffusion source corresponding to the upper surface of the base layer. At this time, a gap is formed between the resist pattern and the solid phase diffusion source formed on the side surface of the insulating film. In the heat treatment of the next sixth step, this gap is filled with the resist pattern which is melted and becomes a fluid state, and the resist completely covers the necessary portion of the solid phase diffusion source. Also in the tenth step, a gap is created between the new resist pattern and the insulating film, and the gap is filled with the melted portion of the new resist pattern by the heat treatment, so that the new resist is a necessary portion of the base electrode film. Completely covered.

In the invention according to claim 4, since the side surface of the opening of the first resist is perpendicular to the upper surface of the base layer, the emitter electrode film and the emitter electrode film are formed by anisotropic etching using the first resist as a mask. The emitter layer is etched in a direction perpendicular to the top surface of the base layer. As a result, the side surface of the formed trench portion is also perpendicular to the upper surface of the base layer. After that, since the trench portion is filled with the insulating film, the side surface of the insulating film is also perpendicular to the upper surface of the base layer, and its shape becomes a plate shape. Then, the second resist covers the upper surfaces of the two insulating films and the upper surface of the emitter electrode film sandwiched between the two insulating films, and the side surface of each insulating film is wet-etched using the second resist as a mask. The emitter electrode film and the emitter layer on the side surface side that does not face one of the insulating films are removed.

In the invention according to claim 5, the emitter layer comprises:
Etching is performed until a part of the upper surface of the base layer is exposed. As a result, a part of the upper surface of the base layer forms the bottom surface of the trench portion, so that the insulating film filling the trench portion is formed perpendicularly to the upper surface of the base layer.

According to the sixth aspect of the invention, the anisotropic etching of the emitter layer is completed when the emitter layer is located above the upper surface of the base layer by the thickness of depletion. As a result, an insulating film is formed on the remaining part of the depleted emitter layer.

In the invention according to claim 7, the uppermost layer film, the first insulating film, the emitter electrode film and the emitter layer are etched in a direction perpendicular to the upper surface of the base layer by anisotropic etching in the second step. To be done. Therefore, the exposed side surface of each of these layers is perpendicular to the upper surface of the base layer. Then, by the third step, a second insulating film is formed on these side surfaces, the upper surface of the uppermost layer film and the upper surface of the base layer. Therefore, when anisotropic etching is performed to remove the second insulating film on each upper surface of the uppermost layer film and the base layer, the uppermost layer film, the first insulating film, the emitter electrode film, and each side surface of the emitter layer are removed. The second insulating film remains. The remaining second insulating film has a curved side surface shape at the tip portion corresponding to the side surface of the uppermost layer film, but the side surface shapes of the other portions are perpendicular to the upper surface of the base layer. There is.

In the invention according to claim 8, the insulating film formed on the surface around the emitter layer is positioned perpendicular to the upper surface of the base layer. Further, the high carrier concentration region is formed in the base layer in a self-aligned manner at a position apart from the insulating film.

In the invention according to claim 9, the high carrier concentration region is formed in a self-aligned manner, and a plate-like insulating film is formed on the peripheral surface of the emitter layer so as to be perpendicular to the semiconductor substrate. . Therefore, in forming the base electrode contact portion, an unnecessary film is not formed on the side surface of the insulating film, and the unnecessary film formed on the upper surface of the insulating film can be removed.

According to the tenth aspect of the invention, the depleted portion of the emitter layer remains below the insulating film.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor device according to the present invention is one in which the side surface of the insulating film on the peripheral surface of the emitter is vertical. Furthermore,
In the method of manufacturing a semiconductor device according to the present invention, the solid phase diffusion source is isolated from the insulating film around the emitter in a self-aligning manner for a certain period of time to prevent the diffusion of the dopant into the insulating film. Examples 1 to 3 of the method for manufacturing such a semiconductor device will be described below.

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings. 1 to 19 are step views showing a manufacturing process of a semiconductor device as a first embodiment, for example, a heterojunction bipolar transistor (hereinafter referred to as HBT), and FIG. 20 shows the manufacturing process. It is sectional drawing which shows the structure of the obtained semiconductor device as a 1st Example. In these figures, 1 is a semiconductor substrate (eg GaAs substrate), 2 is a collector layer (eg n-type GaAs), 3 is a base layer (eg p-type GaAs), 4
Is an emitter layer (for example, n-type AlGaAs), 5 is a first WSi film (also referred to as an emitter electrode film), 6 is an Al film, and 7
Is a second WSi film, 8 is a first resist, 9 is a second insulating film, 10 is a second resist, 11 is a solid phase diffusion source, 12
Is a third resist, 13 is a thermal sag resist, 14 is a processed solid phase diffusion source, 15 is a third insulating film, 16 is a high carrier concentration region, 17 is a base electrode film, 17a is a base electrode film 17 Unnecessary portion, 17A is a base electrode contact portion, 18 is a fourth resist that has been thermally sagged, 19 is a collector electrode, and 27 and 28 are trench portions.

Next, the semiconductor device of the first embodiment and its manufacturing process will be described. First, the collector layer 2, the base layer 3, the emitter layer 4, the first WSi film 5, the Al film 6, and the second WSi film 7 are sequentially formed on the upper surface of the semiconductor substrate 1 (FIG. 1).

Next, the first resist 8 which forms two openings on the upper surface of the second WSi film 7 is patterned (FIG. 2). After that, the second WSi film 7, the Al film 6, the first WSi film 5 and the emitter layer 4 are sequentially etched using the first resist 8 as a mask. In this case, the second WS
The i film 7 and the first WSi film 5 were dry-etched using SF ₆ gas, and the Al film 6 and the emitter layer 4 were dry-etched using Cl ₂ gas. , Anisotropically etch. This allows
A trench portion 27 having vertical side surfaces is formed (FIG. 3,
(Fig. 4). At the stage of FIG. 4, the bottom surface of the trench portion 27 corresponds to a part of the top surface of the base layer 3. Then, the first resist 8 is removed by ashing.

Next, the trench portion 27 is completely covered with the second insulating film 9 (eg, SiO film) by CVD growth + etchback or application of organic silicon oxide film liquid (eg, SOG) + etchback. ) To embed (FIG. 5). Then, a second resist 10 oversized from the second insulating film 9 is further formed on both upper surfaces of the second WSi film 7 and the second insulating film 9 by resist coating and patterning (FIG. 6). .

Next, using the second resist 10 as a mask, unnecessary portions of the second WSi film 7, the Al film 6, the first WSi film 5 and the emitter layer 4, that is, two insulating films are formed. The respective films 4 to 7 other than the portion sandwiched by 9 are removed by isotropic etching. At this time, etching is performed using an etchant that does not easily give anisotropy. For example, regarding the first and second WSi films 7 and 5, NH ₄ OH + H ₂ O
₂ is etched using HCl for the Al film 6 and tartaric acid for the emitter layer 4 as etchants. Instead of wet etching, the above etching may be performed by plasma etching (RIE or the like) under the condition that anisotropy is unlikely to occur.

After the etching is completed, the second resist 10 is formed.
Is removed by ashing (FIG. 7). As a result, the upper surface of the base layer 3 is exposed except a part thereof, and the emitter layer 4 and the films 5 to 5 formed on the upper surface are exposed only on the upper surface of the part.
7 side surface (peripheral surface) and emitter layer 4 side surface (peripheral surface)
The insulating film 9 that covers is left. The side surface of the insulating film 9 is perpendicular to the upper surface of the base layer 3 or the semiconductor substrate 1 and has a plate shape.

Next, a solid phase diffusion source 11 is formed on the entire exposed surfaces of the base layer 3, the second insulating film 9 and the second WSi film 7 (FIG. 8). Here, as the solid phase diffusion source 11, for example, a ZnO film can be used.

Further, a third resist 12 is formed by patterning on a part of the upper surface of the part formed on the upper surface of the base layer 3 in the solid phase diffusion source 11 (FIG. 9). Then, heat treatment is performed to reflow the third resist 12 so that the third resist 12 is thermally sagged (FIG. 10).
As a result, the third resist 12 is melted, and the melted portion causes the third resist 12 and the solid phase diffusion source 1 to melt.
The gap that was created between 1 and 1 is filled. Therefore, since such a method is used, the formation of the third resist 12 in FIG. 9 can be roughly performed.

Then, the unnecessary portion of the solid phase diffusion source 11 is removed by etching using the resist 13 which has undergone thermal sag as a mask (FIG. 11). Here, Z is used as the solid phase diffusion source 11.
When nO is used, the unnecessary portion of the solid phase diffusion source 11 can be partially removed by wet etching using an acid or alkali solution. As a result, the trench 28
Is formed, and the solid-phase diffusion source 11 in FIG. 10 remains as a processed diffusion source 14 (hereinafter, simply referred to as the solid-phase diffusion source 14). Then, after removing the resist 13, a third insulating film 15 (a film of a different type from the second insulating film 9), for example, a SiN film is formed on the entire surface exposed at this stage (FIG. 12). ).

Next, heat treatment is performed. As a result, the dopant diffuses isotropically from the solid-phase diffusion source 14. that time,
Since the second insulating film 9 is separated from the solid-phase diffusion source 14 by the third insulating film 15, the dopant diffused in the third insulating film 15 is stopped from moving, and as a result, the second insulating film 9 is separated.
As a result, a high carrier concentration region 16 is formed in the base layer 3 immediately below the solid phase diffusion source 14 and the third insulating film 15 (FIG. 13). The portion of the high carrier concentration region 16 that is formed immediately below the third insulating film 15 is formed by the diffusion of the diffused substance into the base layer 3 to the portion.

After that, the third insulating film 15 and the solid phase diffusion source 14 are sequentially removed (FIGS. 14 and 15). At that time,
The second WSi film 7 is removed together with the third insulating film 15, and the Al film 6 is also removed together with the solid phase diffusion source 11.
That is, for example, if the second insulating film 9 is a SiO film and the third insulating film 15 is a SiN film, the third insulating film 15 and the second WSi film 7 are selectively etched by, for example, RIE.
And can be removed at the same time. Also, acid or alkaline solutions,
For example, HCl can be used to remove the solid phase diffusion source 14 and the Al film 6 at the same time.

Further, the base electrode film 17 is formed on the entire surface exposed at this stage (FIG. 16). 17a formed at this time is an unnecessary portion. Then, the fourth resist 18 is patterned to form the base electrode film 17 (necessary part).
After being formed on the upper surface of the substrate (not shown), thermal sag (reflow) is performed to cover necessary portions of the base electrode film 17 with the fourth resist 18 (FIG. 17). Therefore, also in this step, there is an advantage that the fourth resist 18 can be roughly patterned.

Next, the unnecessary portion 17a of the base electrode film 17 is etched and removed by ion milling using Ar ions, for example. At this time, since the side surface of the second insulating film 9 is vertical, the unnecessary portion 17a can be easily removed, and even if there is a remaining portion, it is unlikely to cause a short circuit (FIG. 19). Further, the fourth resist 18 is removed (FIG. 19).

After that, a semiconductor device is manufactured through predetermined steps. The sectional structure of the obtained semiconductor device as the first embodiment is shown in FIG. The required portion of the base electrode film 17 functions as the base electrode contact portion 17A in this semiconductor device.

In the first embodiment, GaAs / AlGaA is used.
The s-based HBT has been explained, but InP, InGaA
No problem occurs when the technique of Example 1 is applied not only to InP-based HBTs using s, InP, etc., but also to HBTs using other compound semiconductors.

Example 2 FIG. 21 is a sectional view showing the structure of a semiconductor device as a second example. In the figure, the second insulating film 9A and the emitter layer 4A correspond to 9 and 4 of the first embodiment, respectively.

Regarding this method of manufacturing a semiconductor device, in the step of etching the emitter layer 3 shown in FIG. 4, the emitter layer 4A is left by a thickness to be completely depleted.
The other steps are achieved by making them the same as those in the first embodiment. Therefore, the insulating film 9A formed on the peripheral surface of the emitter layer 4A is formed on the upper surface of the stepped end of the emitter layer 4A.

Also in the second embodiment, the same effect as in the first embodiment can be obtained. In addition, in the second embodiment, since the depletion layer is formed at the entire interface between the base layer 3 and the emitter layer 4A, the recombination current at the interface can be suppressed. That is, with this configuration, it is possible to easily realize the recombination current suppression.

(Embodiment 3) FIGS. 22 to 41 are sectional views showing a semiconductor device and its manufacturing method as a third embodiment of the invention. In these figures, 1 to 19 are equivalent to those of the first embodiment, 20 is the first insulating film, 21 is the second WSi film (corresponding to the uppermost layer film), and 22 is the second insulating film. , 23 are sidewalls, and 29 is a trench portion.

The manufacturing process of the semiconductor device of the third embodiment will be described below with reference to the drawings. First, the semiconductor substrate 1
A collector layer 2, a base layer 3, an emitter layer 4, a first WSi film 5 (emitter electrode film), a first insulating film 20, and a second WSi film 21 are formed on the upper surface of (for example, a GaAs substrate).
The layers are sequentially formed (FIG. 22).

Then, the first resist 8 is formed on the upper surface of the second WSi film 21 by patterning the resist (FIG. 23), and then the second resist 8 is used as a mask to form the second WSi film. 21, first insulating film 20, first W
The Si film 5 is sequentially dry-etched under anisotropic conditions (FIG. 24). Further, using the first resist 8 as a mask, anisotropic etching is continued to etch the emitter layer 4 (FIG. 25). Then, the first resist 8 is removed by ashing (FIG. 26).

Next, the second insulating film 22 (for example, SiO 2
A film) is formed on the entire exposed surface (FIG. 27), and sidewalls 23 made of the second insulating film 22 are formed on the side surfaces of the layers 4, 5, 20, 21 by anisotropic etching (FIG. 2).
8). The sidewall 23 has a curved tip portion formed on the side surface of the second WSi film 21, but has a substantially plate-like shape as a whole, and the side surface has the base layer 3 or the semiconductor substrate 1. Perpendicular to the upper surface of.

Further, the solid phase diffusion source 11 is formed on the entire surface of the exposed base layer 3, side wall 23 and second WSi film 21.
(For example, a ZnO film) is formed (FIG. 29), the third resist 12 is patterned (FIG. 30), heat treatment is performed, and the third resist 12 is reflowed (heat sagging) to be melted. Then, the gap between the third resist 12 and the solid phase diffusion source 11 is filled (FIG. 31). Therefore, the third resist 12
The patterning of 1 does not require high precision and can be roughly performed.

Next, the solid-phase diffusion source 11 is removed by using the resist 13 that has undergone thermal sag as a mask to form a trench 29 (FIG. 32). If ZnO is used as an example of the solid phase diffusion source 11, this removal is realized by wet etching with an acid or alkali solution. As a result, the processed solid phase diffusion source 14 is formed on a part of the upper surface of the base layer 3. Further, the resist 13 which has been thermally sagged is removed by an ashing process, and then a third insulating film 15 is formed on the entire exposed surface (FIG. 33).

Next, a high carrier concentration region 16 is formed by heat treatment (FIG. 34). Also at this time, the dopant diffuses isotropically from the solid phase diffusion source 14, but the movement of the dopant diffused in the third insulating film 15 is stopped, and the dopant in the base layer 3 directly below the solid phase diffusion source 14 is stopped. Then, the dopant is diffused into the base layer 3 directly below the third insulating film 15 to form the high carrier concentration region 16. After that, the third insulating film 15 is removed (FIG. 35).
The first, second, and third insulating films (20, 23) and 15 are different kinds of insulating films (for example, the former is a SiO film and the latter is a SiN film).
The second WSi film 21 is simultaneously removed when the third insulating film 15 is removed. Furthermore, the solid phase diffusion source 1
4 is also removed (FIG. 36).

After that, the semiconductor device of the third embodiment is manufactured by performing the same steps as those of the conventional example shown in FIG. In this case, since the upper surface of the first WSi film 5 is covered with the Al film 6, the first WSi film 5 is formed as in the conventional technique.
The surface of the i film 5 is not roughened by ions.

As described above, according to each of the embodiments of the present invention, since the side surface of the insulating film around the emitter layer is made vertical, the unnecessary portion of the base electrode can be easily removed.

Further, since the diffusion source is formed so as to be separated from the insulating film around the emitter layer in a self-aligned manner, there is no diffusion of the dopant into the insulating film, and the insulating film is not regenerated as in the prior art. There is no need to perform formation, and a highly reliable semiconductor device can be manufactured.

[0064]

According to the first aspect of the invention, the high carrier concentration region is formed in the base layer in a self-aligning manner without diffusing the dopant into the insulating film covering the periphery of the emitter layer. You can Therefore, unlike the prior art, it is not necessary to newly form an insulating film around the emitter layer after forming the high carrier concentration region, and a highly reliable semiconductor device can be manufactured.

According to the second aspect of the present invention, when the base electrode film is formed, it is possible to prevent an unnecessary base electrode film from being formed on the side surface of the insulating film around the emitter layer. The unnecessary part of can be easily removed. Further, there is an effect that the emitter electrode film is not damaged when the base electrode film is formed.

According to the third aspect of the invention, firstly, the required portion of the solid phase diffusion source can be completely covered, and as a result, only the required portion is left and the other portions are removed. You can Therefore, the solid phase diffusion source can be isolated from the insulating film in a self-aligned manner. Secondly, it is possible to completely cover only the required portion of the base electrode film, and as a result, it is possible to reliably remove only the unnecessary portion without etching the required portion.

According to the invention of claim 4, an insulating film having a rectangular cross section can be formed perpendicularly to the peripheral surface of the emitter layer, and an unnecessary base electrode film is formed on the side surface of the insulating film. Can be prevented. Therefore, the unnecessary base electrode film can be removed by anisotropic etching.

According to the invention of claim 5, an insulating film having vertical side surfaces can be formed on the upper surface of the base layer along the peripheral surface of the emitter layer, and an unnecessary base electrode film is anisotropically formed. It becomes possible to remove it by the characteristic etching.

According to the invention of claim 6, a depletion region can be formed below the insulating film.

According to the invention of claim 7, since the side surfaces of the emitter layer, the emitter electrode film, the first insulating film and the uppermost layer are formed perpendicular to the upper surface of the base layer, An insulating film perpendicular to the upper surface of the base layer can be formed around the emitter layer except for the portion corresponding to the side surface of the uppermost layer film. Therefore, the unnecessary portion of the base electrode film can be easily removed. Moreover, since the first insulating film is formed on the upper surface of the emitter electrode film, there is an effect that the emitter electrode film is not damaged when the base electrode film is formed.

According to the invention of claim 8, a semiconductor device capable of preventing the diffusion of the dopant into the insulating film around the emitter layer at the time of forming the high carrier concentration region and removing the unnecessary portion at the time of forming the base electrode film. There is an effect that can be realized.

According to the invention of claim 9, the high carrier concentration region formed in a self-aligned manner without diffusing the dopant into the insulating film around the emitter layer and the base electrode film having no unnecessary portion are provided. There is an effect that a semiconductor device having the same can be realized.

According to the invention of claim 10, there is an effect that a semiconductor device having a depletion region under the insulating film can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device as a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing a semiconductor device as the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device as the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the method of manufacturing a semiconductor device as the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing a semiconductor device as the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the method of manufacturing a semiconductor device as the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device as the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the method of manufacturing a semiconductor device as the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the method of manufacturing a semiconductor device as the first embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 11 is a cross-sectional view showing the method of manufacturing the semiconductor device as the first embodiment of the invention.

FIG. 12 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 13 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 14 is a cross-sectional view showing the method of manufacturing a semiconductor device as the first embodiment of the present invention.

FIG. 15 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the invention.

FIG. 16 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 17 is a cross-sectional view showing the method of manufacturing the semiconductor device as the first embodiment of the present invention.

FIG. 18 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 19 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 20 is a sectional view showing a structure of a semiconductor device as a first embodiment.

FIG. 21 is a sectional view showing a structure of a semiconductor device as a second embodiment of the present invention.

FIG. 22 is a cross-sectional view showing the method of manufacturing a semiconductor device as the third embodiment of the present invention.

FIG. 23 is a cross-sectional view showing the method of manufacturing the semiconductor device as the third embodiment of the present invention.

FIG. 24 is a cross-sectional view showing the method of manufacturing the semiconductor device as the third embodiment of the present invention.

FIG. 25 is a cross-sectional view showing the method of manufacturing a semiconductor device as the third embodiment of the present invention.

FIG. 26 is a cross-sectional view showing the method of manufacturing the semiconductor device as the third embodiment of the present invention.

FIG. 27 is a cross-sectional view showing the method of manufacturing a semiconductor device as the third embodiment of the present invention.

FIG. 28 is a cross-sectional view showing the method of manufacturing the semiconductor device as the third embodiment of the present invention.

FIG. 29 is a cross-sectional view showing the method of manufacturing the semiconductor device as the third embodiment of the present invention.

FIG. 30 is a cross-sectional view showing the method of manufacturing the semiconductor device as the third embodiment of the present invention.

FIG. 31 is a cross-sectional view showing the method of manufacturing a semiconductor device as the third embodiment of the present invention.

FIG. 32 is a cross-sectional view showing the method of manufacturing a semiconductor device as the third embodiment of the present invention.

FIG. 33 is a cross-sectional view showing the method of manufacturing a semiconductor device as the third embodiment of the present invention.

FIG. 34 is a cross-sectional view showing the method of manufacturing the semiconductor device as the third embodiment of the present invention.

FIG. 35 is a cross-sectional view showing the method of manufacturing the semiconductor device as the third embodiment of the present invention.

FIG. 36 is a cross-sectional view showing the method of manufacturing the semiconductor device as the third embodiment of the present invention.

FIG. 37 is a cross-sectional view showing the method of manufacturing the semiconductor device as the third embodiment of the present invention.

FIG. 38 is a cross-sectional view showing the method of manufacturing the semiconductor device as the third embodiment of the present invention.

FIG. 39 is a cross-sectional view showing the method of manufacturing the semiconductor device as the third embodiment of the present invention.

FIG. 40 is a cross-sectional view showing the method of manufacturing a semiconductor device as the third embodiment of the present invention.

FIG. 41 is a cross-sectional view showing the structure of a semiconductor device as a third embodiment.

FIG. 42 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 43 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 44 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 45 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 46 is a sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 47 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 48 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 49 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 50 is a sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 51 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 52 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 53 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 54 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

1 semiconductor substrate, 2 collector layer, 3 base layer, 4
Emitter layer, 5 1st WSi film, 6 Al film, 7 2nd WSi film, 8 1st resist, 9 2nd insulating film, 10 2nd resist, 11 solid phase diffusion source, 12
Third resist 13 Thermally dripped resist, 14 Processed diffusion source,
15 third insulating film, 16 high carrier concentration region, 17
Base electrode film, 18 fourth resist, 19 collector electrode, 20 first insulating film, 21 second WSi film (uppermost layer film), 22 second insulating film, 23 first sidewall, 24 dopant Diffused first side wall, 25 Second side wall, 26 First WSi film whose surface is roughened by milling.

Claims (10)

[Claims] 1. A first step of sequentially forming a collector layer and a base layer on a semiconductor substrate, and a second step of sequentially forming an emitter layer and an emitter electrode film on a part of an upper surface of the base layer, On the surface around the emitter layer and the emitter electrode film,
Third step of forming a plate-shaped insulating film whose side surface is perpendicular to the upper surface of the base layer, and fourth step of forming a solid-phase diffusion source containing a dopant on the entire exposed surface after the third step. A fifth step of covering a necessary portion of the solid phase diffusion source formed on the upper surface of the base layer with a resist, and removing the resist after etching the solid phase diffusion source using the resist as a mask And a seventh step of forming a new insulating film on the entire surface exposed by the sixth step, and a high carrier concentration region is formed in the base layer by heat treatment, and then the new insulating film is formed. And an eighth step of sequentially removing the solid phase diffusion source, the method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a base electrode film is formed on the entire surface exposed by the eighth process, and the base is formed in the base electrode film. A semiconductor device further comprising: a tenth step of covering a necessary portion formed on the upper surface of the layer with a new resist; and an eleventh step of etching an unnecessary portion of the base electrode film using the new resist as a mask. Production method. 3. The method of manufacturing a semiconductor device according to claim 2, wherein in the fifth step, a resist pattern is formed on an upper surface of a portion of the solid phase diffusion source formed only on the upper surface of the base layer. A step of forming, and a step of reflowing the resist pattern by a first heat treatment to form the resist that covers the necessary portion, the tenth step includes a step of forming the necessary portion of the base electrode film. A method of manufacturing a semiconductor device, comprising: a step of forming a new resist pattern on an upper surface; and a step of reflowing the resist pattern by a second heat treatment to form the resist covering the necessary portion. 4. The method of manufacturing a semiconductor device according to claim 1, wherein in the second step, the emitter layer and the emitter electrode film are formed on the entire upper surface of the base layer. And a step of forming a first resist having two openings above the upper surface of the emitter electrode film, the opening having side surfaces perpendicular to the upper surface of the base layer, A step of anisotropically etching the emitter electrode film and the emitter layer sequentially using a resist as a mask to form two trench portions having side surfaces perpendicular to the upper surface of the base layer; The third step is a step of filling the two trench portions with the insulating film, removing the first resist, and then applying a second resist covering the upper surface of the insulating film above the upper surface of the emitter electrode film. A step of forming, and a step of sequentially wet-etching and the emitter electrode layer and the emitter layer using the second resist as a mask, a method of manufacturing a semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 4, wherein in the trench portion in the second step, the emitter layer is anisotropic until a part of an upper surface of the base layer is exposed. A method of manufacturing a semiconductor device, which is formed by etching. 6. The method for manufacturing a semiconductor device according to claim 4, wherein the anisotropic etching of the emitter layer in the trench forming step of the second step is performed only by a thickness that completely depletes the emitter layer. A method for manufacturing a semiconductor device, which is achieved by leaving the emitter layer. 7. The method of manufacturing a semiconductor device according to claim 3, wherein the second step sequentially forms the emitter layer and the emitter electrode film on the entire upper surface of the base layer, A step of sequentially forming a first insulating film and a top layer film on the entire top surface of the emitter electrode film; a step of forming a first resist on a part of the top surface of the top layer film; Anisotropically etching the uppermost layer film, the first insulating film, the emitter electrode film, and the emitter layer sequentially using the resist as a mask to expose a part of the upper surface of the base layer. The third step includes the step of forming a second insulating film on the entire surface exposed by the second step, and the second insulating film formed on the upper surfaces of the uppermost layer film and the base layer. Is removed by anisotropic etching, An upper layer film, the first insulating film, the emitter electrode film, and a step of forming a sidewall as the insulating film on each side surface of the emitter layer, the eighth step, And a step of removing the solid phase diffusion source together with the uppermost layer film, and a method of manufacturing a semiconductor device. 8. A collector layer, a base layer, an emitter layer, an emitter electrode film, the emitter layer and an emitter electrode film, which are manufactured by the method for manufacturing a semiconductor device according to claim 2. A plate-shaped insulating film formed on both peripheral surfaces of the base layer and having a side surface perpendicular to the upper surface of the base layer, a base electrode film sandwiching the insulating film, and a base electrode layer under the base electrode film. A semiconductor device having a formed high carrier concentration region. 9. A semiconductor device having a high carrier concentration region formed below a base electrode contact portion by a diffusion method using a solid phase diffusion source, wherein the semiconductor device is formed on a peripheral surface of an emitter layer and is formed on an upper surface of a semiconductor substrate. And a plate-shaped insulating film having vertical side surfaces, and the high carrier concentration region is formed in self-alignment with the emitter layer. 10. The semiconductor device according to claim 9, further comprising the depleted emitter layer immediately below the insulating film.