JPH08115216A - A computer using a storage device with an address addition function - Google Patents

Abstract

PURPOSE: To prevent a pipeline stall from occurring even in the case of requiring data read out of a 4 memory by a loading instruction in an instruction immediately after the instruction by providing a storage device with an addition function. CONSTITUTION: For the read address and write address of a data storage device 220, inputted two addresses, that are an index X and a base B, are inputted, the address obtained as the result of adding the inputted two addresses is used and the data are read out or written. Thus, a pipeline stage is constituted of three stages of ID, EX and WB. In an EX stage, two pieces of the data set in a register 205 are used as the address in the loading instruction for accessing the memory or the like and the data are read out of the data storage device 220 and set in the register 305. Then, in a WB stage, since the result of the loading instruction is set in the register 305, even in the case of using it in the instruction immediately after, the pipe line stall does not occur.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer having a storage device.

[0002]

2. Description of the Related Art Regarding the conventional technology relating to the pipeline of a computer, reference is made to Morgan Kau.
f. Lmann Hennes issued by fmann Publishers
sy) et al. “Computer Organization and Design the Hardware / Software Interface (COMPUTER ORGANIZATION AND DESIGN THE H
ARDWARE / SOFTWARE INTERFACE) Chapter 6 (364-45)
Explain with reference to (1).

FIG. 7 shows a typical example of the stage configuration of a pipeline used in a conventional computer system.
In this figure, 100, 200, 300 and 400 are pipeline registers (hereinafter simply referred to as registers),
As a result, four pipeline stages ID, EX, M
It is divided into EM and WB.

At the ID stage, an instruction is set in the register 100, and the content (data) of the register is read from the register file 110 according to the register number indicated by the content of the instruction and set in the register 200.

At the EX stage, the ALU 210 performs an operation according to the contents of the data and the instruction set in the register 200, and the operation result is set in the register 300.
Further, in the case of an instruction that does not perform an operation and does not access a memory (such as an inter-register copy instruction), the data in the register 200 is set in the register 300 as it is.

In the MEM stage, the data set in the register 300 is used as an address in a load instruction for accessing the memory, the data is read from the data memory 310 and sent to the register 400, and the memory is accessed. In the case of calculation instructions that do not occur, the data set in the register 300 is directly stored in the register 400.
Sent to Thus, the data is set in the register 400.

In the WB stage, the register 40
The data set to 0 is the multiplexer (MUX) 4
It is selected in 10 and written in the register file 110.

As an example of the operation of the pipeline shown in FIG. 7, a timing chart is shown in FIG. In FIG.
As an instruction sequence, Add r4 r5 r6 (contents of register 5 and register 6
Add the contents of, and store the result in register 4) Load r2 r7 r8 (add the contents of register 7 and the contents of register 8 and load the data from the memory location pointed to by the resulting address, Store in register 2) Add r1 r2 r3 (contents of register 2 and register 3
Is added and the result is stored in the register 1).

In FIG. 7, ◯ shown in the drawing indicates which stage each instruction is being processed at each time. Since the first instruction and the second instruction have no data dependency, all stages are processed one cycle at a time. However, the third instruction requires the data loaded by the second instruction at the EX stage (that is, there is a data dependency), but the second instruction can obtain the data at the end of the MEM stage. Since it is time, the EX stage of the third instruction must be processed after waiting for the end of the MEM stage of the second instruction.

Further, FIG. 8 shows a pipeline for reading an instruction (herein referred to as a target instruction) at a branch destination of the branch instruction. In the ID stage, the register contents (data) are read from the register file 110 and set in the register 200 according to the register number indicated by the contents of the branch instruction. In the EX stage, the ALU 210 performs addition using the data set in the register 200, and the addition result is set in the register 300. In the MEM stage, the data set in the register 300 is used as an address for reading the target instruction from the memory, the target instruction is read from the instruction memory 320, and the read instruction is written in the register 100.
The next instruction will be executed. However, if a branch instruction branches only when a certain condition is satisfied, either the target instruction or the next instruction that continues at the address of the branch instruction (simply the next instruction) is determined according to the result of the determination of the condition. To be selected.

However, although the next instruction is also read from the instruction memory 320, it is assumed here that it is read from the instruction memory 320 prior to the execution of the branch instruction. This is because the read width of the instruction memory 320 is twice or more the length of one instruction, and 2 times per one read.
This is possible by reading out more than one instruction. This is the method used by many of today's computers.

As an example of the operation of the pipeline shown in FIG. 8, a timing chart is shown in FIG. In FIG. 13, as an instruction sequence, Add r4 r5 r6 (contents of register 5 and register 6
Branch r7 r8 (According to the condition, the contents of register 7 and the contents of register 8 are added, and the instruction at the memory position pointed to by the resulting address is added. Add r1 r2 r3 (register 2 contents and register 3
Is added and the result is stored in the register 1). All the stages of the first instruction and the second instruction are processed by shifting by one cycle. However, although the third instruction is the instruction read by the second instruction, the instruction can be obtained by the second instruction at the end of the MEM stage, so the ID stage of the third instruction is It must be processed after waiting for the end of the MEM stage of the second instruction.

By the way, the memory shown in FIG. 7 and FIG.
It is a memory that, when an address is input, reads data from the portion indicated by the address, or writes data in the portion indicated by the address. But,
In many cases, the memory shown in FIGS. 7 and 8 is a cache storage device. The cache storage device is composed of a plurality of memories such as an address conversion buffer, a directory, and a data array.

As an example, FIG. 15 shows the memory 31 of FIG.
It is assumed that 0 is a cache memory device and its internal memory is shown. Here, the cache memory device comprises a data array 311, a selection circuit 311, a directory 313, and a hit detection circuit 314 (there may be an address translation buffer depending on the case). An entry including an address of data stored in the data array is stored in the directory, and an operation for reading data from the cache storage device will be described below.

Data is read from the data array, and the entry corresponding to the data is read from the directory 313. In the hit detection circuit 314, the directory
Based on the entry read from 313 and the read address set in the pipeline register 300, it is checked whether or not there is desired data in the data read from the data array 311. As a result, if there is desired data, the selection circuit 312 selects the desired data from the data read from the data array 311 and sets the data in the pipeline register 400. If there is no desired data, the data is transferred from the main storage device to the data array 311.

In the pipeline configuration shown in FIG. 15, the MEM stage is often the largest when the delays of the respective stages are compared. In the MEM stage, the directory 313 is estimated as estimated from FIG.
In many cases, the route for reading is the largest delay. Therefore, in some cases, the MEM stage may be divided into two stages in order to speed up the machine cycle. However, by doing this, if the subsequent instruction uses the result of the above load instruction as an operand,
Subsequent instructions are delayed by one more stage.

Next, the conventional technique relating to the circuit configuration of the data memory 310 and the instruction memory 320 is described in 8.5 Random Access of "Principle of CMOS VLSI Design from the System Viewpoint" translated by Takashi Tomizawa and Yasuo Matsuyama, published by Maruzen Co. Description will be made with reference to the memory (sections 306 to 325).

Data memory 310 and instruction memory 320
FIG. 9 shows a typical example of the circuit configuration of FIG. As the memory here, a memory is considered in which, when an address is input, data is read from a portion indicated by the address, or data is written in a portion indicated by the address. The memory is composed of a row decoder 500, a memory array 600, a column decoder 700, and a multiplexer 800. The arrows between them indicate the direction in which signals travel, and the numbers given to the arrows indicate the number of signals.

First, the read operation will be described. The read address is first divided into upper, middle and lower three addresses, and only the middle is used for reading. The middle of the read address is further divided into upper and lower two, one of which is a row address and the other is a column address. These addresses are decoded by the row decoder 500 and the column decoder 700, respectively. That is, by decoding the M row address, only one signal of the "2 to the Mth power" becomes 1 and the other signals become 0.

In the memory array, memory cells for storing a 1-bit signal are arranged in a lattice form in the vertical (column direction) and the horizontal (row direction) "2 M powers" x "2 N power". Among the input signals from the row decoder 500, one row indicated by the signal 1 is read out, and the multiplexer 80
Output to 0. On the other hand, the column decoder 700 also performs the same decoding as the row decoder 500, and the multiplexer 800 outputs one row “N of 2” of the output of the memory array 600.
Among the "squared" signals, one column of "2 to the Kth power" signals are selected and output as read data.

Next, the write operation will be described. Similar to the read address, the middle of the write address becomes the row address and the column address, and the row decoder 50
It is decoded by the 0 and column decoder 700. The write data is input to the multiplexer 800, and the output signal “2 of N” is output from the multiplexer 800 to the memory array 600.
The output signal “2 (N−
K) square ”, one column“ 2 ”corresponding to the signal that is 1 in the book
Data is added to the "Kth power of" signals, and the other signals are in a high impedance state. Then, the data placed in only one column of the output signal from the multiplexer 800 to the memory array 600 corresponds to one row of the output signals of the row decoder 500 that corresponds to the signal that is 1, "2 to the Nth power".
Of the memory cells, data is written in "2 to the power of K" memory cells in one column.

By the way, the output of the row decoder 500 is 2
No more than one signal should be one. Otherwise, the data stored in the memory array may be destroyed. However, in the actual operation, since a different address is input to the memory every cycle, if the result of decoding the address input in the previous cycle and the result of decoding the address input in the relevant cycle are different, , The output of the row decoder 500 changes. For this reason,
There is a certain transition time, and during this period, two or more of the output signals can be 1, but if this transition time is less than a certain value, data destruction can be prevented. Therefore, in the design of the memory, this transition time should be set to a short time such that the data in the memory cell 600 is not destroyed.

Further, in the write operation, among the signals output from the multiplexer 800 to the memory array 600, the data is put only in the column to be written, and the other signals are set to high impedance. Therefore, the column decoder 70 is used.
At a zero output signal transition time, data can be corrupted because another column does not go high impedance.
Therefore, like the row decoder 500, the column decoder 7
It is also possible to make the transition time of the 00 output signal as short as possible so that the data is not destroyed. Also, during the transition time of the output signal of the column decoder 700, the memory array 600 is
For example, by setting all the signal lines to which write data is input to high impedance to the column decoder 700
It is also possible to remove the design constraint of the transition time of the output signal of the.

[0024]

In the pipeline described in the prior art, the stage in which the result of the load instruction is obtained is delayed by one cycle as compared with the stage in which the result of the operation instruction is obtained. Therefore, when the data read from the memory by the load instruction is required by the instruction immediately after the instruction, pipeline stall occurs and the performance deteriorates. Further, when executing a branch instruction, a considerable number of cycles are required until the target instruction is read out, which also deteriorates the performance.

Alternatively, in many processors, the delay of the route for reading the directory of the cache storage device is slow and the machine cycle becomes slow, or the performance of the system is degraded by dividing the stage.

Further, if the addition in the ALU 210 and the access to the data memory 310 or the instruction memory 320 in the pipeline are performed in one cycle, the delay increases and the machine cycle time increases, so that the performance deteriorates. Further, when the random access memory shown in FIG. 9 is used as the memory, the row decoder 500 cannot achieve the design constraint of the transition time of the output signal, which is a particular problem.

An object of the present invention is to improve the pipeline structure so that the stage where the result of the operation instruction is obtained and the stage where the result of the load instruction are obtained are the same, and the data read from the memory by the load instruction is stored in the instruction. The need to have a pipeline stall even if required by the instruction immediately after is. Another object of the present invention is to reduce the number of cycles required to read a target instruction when executing a branch instruction.

[0028]

According to the present invention, there is provided a storage device for inputting two pieces of data output from a pipeline register and accessing an address obtained as a result of adding them. A computer is provided which is characterized in that the read data is set in a pipeline register. Further, according to the present invention, the storage device has a storage device for accessing two addresses output from the pipeline register and accessing an address obtained as a result of adding the two data, and the instruction read from the storage device has a pipeline. A computer is provided that is set in the line register.

Alternatively, there is provided a computer having a directory of a cache storage device for inputting two pieces of data output from the pipeline register and accessing an address obtained as a result of adding them.

Further, according to the present invention, two row decoders for decoding two row addresses are provided, and a barrel shifter for shifting the output signal of one row decoder by the output signal of the other row decoder is provided. Then, a computer having a memory device is provided, which has a memory array having a signal line for inputting / outputting data, in which a row to be accessed is controlled by using an output signal of the barrel shifter as an input signal. Further, by activating one of the row address signal lines, the switches of all the memory cells in one row corresponding to the row address and the one row corresponding to the address obtained by adding 1 to the row address, Only the switch of the memory cell whose column address is 0 is turned on, and the computer having the memory device having the memory cell connected to the data input / output signal line is provided.

[0031]

According to the present invention, the address addition and the access to the storage device can be performed in one cycle, so that the pipeline stages in the access to the memory can be reduced and the load instruction can be the same as the operation instruction. The result can be obtained in the cycle of, and the pipeline stall can be avoided when the result is required by the subsequent instruction, and the performance of the computer can be improved.
Further, the target instruction in the branch instruction can be read at high speed, and the performance of the computer can be improved.

Alternatively, by using the directory of the cache storage device for inputting the two data output from the pipeline register and accessing the address obtained as a result of adding them, without increasing the pipeline stages, Read from the directory,
The hit detection circuit can be divided into two stages, a high-speed machine cycle can be realized without increasing the pipeline stages, and the performance of the computer can be improved.

Further, according to the present invention, the address addition can be speeded up because the address addition is row-decoded in the memory device and then the shift operation is performed to perform the addition. In addition, in address addition, since the memory array can be accessed without waiting for the carry of the carry to the most significant bit of the row address having the largest delay, the access from the address addition to the memory can be speeded up. As a result, it is possible to access the memory from the address addition in one cycle without increasing the machine cycle, and it is possible to satisfy the constraint of the transition time which is a problem in designing the memory device.

[0034]

EXAMPLE A first example will be described with reference to FIG. In the data storage device 220 used in the present invention, the read address and the write address are the addresses obtained as a result of adding the two input addresses, that is, the index X and the base B, and adding the two input addresses. , Use this to read or write data. As a result, a pipeline equivalent to the pipeline described in the related art (FIG. 7) becomes as shown in FIG. That is, the pipeline stage is composed of three stages of ID, EX, and WB.

In the ID stage, an instruction is set in the register 105, and the register content (data) is transferred from the register 110 according to the register number indicated by the instruction content.
Is read out and set in the register 205.

In the EX stage, the ALU 210 performs an operation according to the data set in the register 200 and the content of the instruction, and the operation result is set in the register 305.

On the other hand, the two pieces of data set in the register 200 are used as addresses in a load instruction for accessing the memory, and the data storage device 220 is used.
The data is read from and is set in the register 305. Further, in the case of an instruction that does not perform an operation and does not perform a memory access (such as an inter-register copy instruction), the data in the register 205 is set in the register 305 as it is.

Then, in the WB stage, the register 30
The data set to 5 is selected by the multiplexer 330 and written in the register 110. here,
Since the result of the load instruction is also set in the register 305, pipeline stall does not occur even if the instruction is used immediately thereafter.

FIG. 10 shows a timing chart as an example of the operation of the pipeline shown in FIG. In FIG. 10, as an instruction sequence, Add r4 r5 r6 (contents of register 5 and register 6
Add the contents of, and store the result in register 4) Load r2 r7 r8 (add the contents of register 7 and the contents of register 8 and load the data from the memory location pointed to by the resulting address, Store in register 2) Add r1 r2 r3 (contents of register 2 and register 3
Is added and the result is stored in the register 1). Since the first instruction and the second instruction have no data dependency, all stages are processed one cycle at a time. The third instruction needs the data loaded by the second instruction at the EX stage (that is, there is a data dependency), but the second instruction can obtain the data.
Since it is the end time of the EX stage, the E of the third instruction
The X stage can be executed at the same time as the MEM stage of the second instruction, without the need for the pipeline stall described in the prior art.

Depending on the instruction set, address addition may be performed by adding three addresses, that is, X, B and displacement (D). In this case, since the three addresses can be converted into two addresses by passing the so-called carry save adder, the data storage device 220 can be used in the same manner as above. Since the carry-save adder has only about two gates, the effect on the delay caused by passing through the carry-save adder is small. Therefore, in the pipeline configuration shown in FIG. 1, it is not necessary to add a new stage. Alternatively, the conversion of three addresses into two addresses by the carry save adder may be performed in the ID stage or the EX stage.

Next, a second embodiment will be described with reference to FIG. Here, like the memory used in the first embodiment, an instruction storage device that inputs two addresses B and X and reads an instruction by the address obtained as a result of adding the two input addresses 230 is used. As a result, a pipeline equivalent to the pipeline described in the related art becomes as shown in FIG. That is, as in the first embodiment, the pipeline stage is composed of three stages of ID, EX and WB.

The execution by a branch instruction, which is a feature of this embodiment, will be described below.

At the ID stage, the register contents (data) are read from the register 110 and set in the register 205 according to the register number indicated by the contents of the branch instruction.

In the EX stage, the two pieces of data set in the register 205 are used as addresses for reading the target instruction from the memory, and the instruction storage device 230 is used.
The target instruction is read from, and the read instruction is written in the register 105 and becomes the next executed instruction. Therefore, the pipeline stage required to access the target instruction can be shortened by eliminating one stage of address addition.

As an example of the operation of the pipeline shown in FIG. 2, a timing chart is shown in FIG. In FIG.
As an instruction sequence, Add r4 r5 r6 (contents of register 5 and register 6
Branch r7 r8 (According to the condition, the contents of register 7 and the contents of register 8 are added, and the instruction at the memory position pointed to by the resulting address is added. Add r1 r2 r3 (register 2 contents and register 3
Is added and the result is stored in the register 1). All the stages of the first instruction and the second instruction are processed by shifting by one cycle. However, although the third instruction is the instruction read by the second instruction, the instruction can be obtained by the second instruction at the end of the EX stage, so the ID stage of the third instruction is It must be processed after waiting for the EX stage of the second instruction to finish. But,
Compared with the prior art, the execution of the ID stage of the third instruction can be advanced by one cycle.

In the first and second embodiments, although the register 105 is shown in FIGS. 1 and 2, the register in which the instruction is set, the circuit for reading the data from the register, and the multiplexer 330 are used in this embodiment. In the example, it is used for the convenience of the pipeline structure and does not limit the present invention. A feature of the present invention is that there is no pipeline register between the registers 205 and 305, that is, there is no pipeline register on the access from the address addition to the storage device.

Basically, the storage devices 220 and 230 used in the first and second embodiments described above, when an address is input, read data from the portion indicated by the address or the portion indicated by the address. It is a memory for writing data to. By the way, even for a storage device including a plurality of memories such as the cache storage device described in the related art, a storage device similar to the storage devices 220 and 230 is used for each memory to configure the cache storage device. It is possible to use such a cache memory device for the memory devices 220 and 230 in the first and second embodiments without changing the pipeline configuration.

Another concept is to replace some of some of the memories in the cache storage device with the storage device of the present invention, but to replace some of them. An example thereof is shown below as a third embodiment.

The third embodiment will be described with reference to FIG. Here, in the memory in the cache storage device, the directory 213 inputs two addresses B and X,
The storage device reads out data by the address obtained as a result of adding the two input addresses. As a result, a pipeline equivalent to the pipeline of FIG. 15 described in the related art becomes as shown in FIG. That is, the pipeline stage has the same I
It consists of four stages: D, EX, MEM, and WB.

At the ID stage, an instruction is set in the register 106, and the register content (data) is transferred from the register 110 according to the register number indicated by the instruction content.
Is read out and set in the register 206.

In the EX stage, the ALU 210 performs an operation according to the data set in the register 206 and the content of the instruction, and the operation result is set in the register 306.
On the other hand, the two pieces of data set in the register 206 are used as addresses in a load instruction or the like for accessing the memory, and an entry is read from the directory 213 and set in the register 306.

At the MEM stage, the addition result of the ALU 210 set in the register 306 is used as an address to access the data array 311, and the data is read,
On the other hand, the hit detection circuit determines whether or not the desired data exists in the data read from the data array 311 by the entry or the like input to the selection circuit 312 and read from the directory 213 set in the register 306. If it exists, the selection circuit 312 selects the desired data and sets it in the register 406.

In the WB stage, the register 40
The data set in 6 is selected by the multiplexer 410 and written in the register 110.

With the configuration shown in FIG. 14, the read from the directory and the hit detection circuit can be divided into two stages without increasing the pipeline stages, and a high-speed machine cycle can be achieved without increasing the pipeline stages. It can be realized and the performance of the computer can be improved.

Further, many computers have an address translation buffer in the cache storage device. Input two addresses B and X into the address conversion buffer, and input 2
By using a storage device that reads out data according to the address obtained as a result of adding the addresses
It can be made accessible on the X stage.

Next, an example of a method of configuring the data storage device 220 and the instruction storage device 230 will be described with reference to FIG.

First, the read operation will be described.
When the address B and the address X are input as the read address, the middle positions are divided into the row address and the column address. Different from the memory described in the conventional technique, the higher address of the divided addresses must be the row address and the lower address must be the column address. The two row addresses are respectively decoded by the row decoder 500, and the barrel shifter 510 outputs a signal obtained by shifting one output signal by the value indicated by the other row address. This output signal matches the output signal obtained as a result of decoding by the row decoder after adding exactly two row addresses. Then, by this output signal, among the rows of the memory array 610, "2 to the Nth power" of memory cells in the row indicated by "sum of row addresses" and "value obtained by adding 1 to the sum of row addresses".
The output of one column of "2 to the power of K" memory cells whose column address is 0 is selected by the multiplexer 810.
Output to

On the other hand, the carry look-ahead circuit 720 generates a carry (carry to the least significant bit of the column address) when the lower order of the two addresses B and X is added. Is the adder 710
Is input to

In the adder 710, the column addresses of the addresses B and X and the carry input from the carry look-ahead circuit 720 are added. Therefore, the adder 710
Outputs the column address and the carry (carry to the least significant bit of the row address) obtained as a result of adding the lower part from the column addresses of the address B and the address X. The carry in the output of the adder 710 is the multiplexer 81.
Among the input signals from the memory array, which are input to 0, of the “2 N powers” of the first column of the “2 N powers” of the row indicated by the “row address sum”, A selection is made between the output signal and the output signals of "2 K power" memory cells in one column in which the column address of the row indicated by "the address obtained by adding 1 to the sum of row addresses" is 0. That is, when the carry is 0, the former is selected, and when the carry is 1, the latter is selected. Then, for output signals other than the output signals of the “2 K power” memory cells in the first column of the “2 N power” of the row indicated by the “row address sum”, the multiplexer 810 is left as it is. It is output through.

Thus, the multiplexer 810 outputs "N of 2".
It outputs the signal of the "square" book. Then, the output signal of the adder 710 is decoded by the column decoder 700, and in the multiplexer 800, among the “2 N powers” of the output signal of the multiplexer 810, the corresponding “2 K power” signals of one column are output. It is selected and this is output as read data.

The write operation will be described. What is different from reading is a portion relating to the multiplexers 800 and 810 and the memory array 610. That is, the write data is input to the multiplexer 800, and the multiplexer 800 outputs “1 to the Nth power” of the output signals to the multiplexer 810, which corresponds to one of the output signals of the column decoder. Write data is put on the output signal of "2 to the power of K", and the other parts are set to high impedance. Then, from the multiplexer 810 to the memory array 6
Of the output signal “2 to the Nth power + 2 to the Kth power” to 10, the write data is loaded only on the signal line input to the memory cell designated by the write address, and the other signal lines become high impedance.

A problem in the write operation is the transition time of the output signal from the multiplexer 810 to the memory array 610. This transition time is caused by the delay of the column decoder and the delay of the output signals of the adder 710 and the carry look-ahead circuit 720, but it does not cause a problem when the number of bits of the column address and the lower address is small. However, when the number of bits is large and the transition time becomes a problem, the multiplexer 810 is used during the time of the delay of the adder 710 and the carry look-ahead circuit 720, as in the method described in the related art.
From the memory array 610 to the high impedance.

By the way, although the barrel shifter is used in the example of FIG. 3, if the number of output signal lines of the row decoder is large, the barrel shifter may have a large area when configured on an LSI.

As a means for solving the problem, it is possible to consider a method of adding row addresses in advance and then decoding, as shown in FIG. This can reduce the area (delay may be worse).
Also in this configuration, since the addition of the row address can access the memory array without waiting for the carry from the lower bit of the row address, the delay is faster than the address addition and the transition time The constraint can be removed.

Further, based on the configuration of FIG. 4, the following can be done. That is, in the pipeline of FIG. 1 and FIG. 2, the addresses X and B are set in the register 200, but before being set in the register 200, the adder 7
11, the row address is added (that is, the address is partially added), the result is set in the register 200, and the output of the register 200 is directly input to the row decoder 500 in the next cycle.

What is important here is that when the storage device is accessed after the address addition is partially performed in this way, the storage device accessed by two addresses, which is a feature of the present invention, is partially used. That is, it can be regarded as a special case in which the value is fixed to 0 (the accompanying circuit such as an input signal can be removed because the value is fixed). In other words, the present invention does not separate the stages of address addition and memory access from the stage as in the past, except that one cycle is used for memory access from address addition. It is characterized in that it is possible to divide the stage at an appropriate place.

Next, an example of a method of constructing the memory array 610 and the multiplexer 810 will be described with reference to FIG.
The memory array 610 includes a memory cell 611 that stores a 1-bit signal and a switch 612. Switch 61
Reference numeral 2 turns on / off the connection between the memory cell 611 and the “signal connecting the memory array 610 and the multiplexer 810” (herein referred to as “bit line”). ON / OFF of the switch 612 is controlled by a “signal connecting the memory array 610 and the row decoder 500” (herein referred to as a “word line”), and is ON when the signal is 1,
If 0, it is turned off. The number given to each word line is a row address, and the number given to each memory cell is an address (here, “row address × 8 + column address” is an address). Further, the number given to the bit line between the multiplexers 810 and 800 is the column address, and between the memory array 610 and the multiplexer 810, there are two bit lines corresponding to the column address 0. In order to do so, it is set to 0-1, 0-2.

The feature of the configuration of the memory array 610 and the multiplexer 810 is the column address 0 portion.
For example, in the read operation, if the signal on the word line 0 is 1, then on the bit line from the memory array 610 to the multiplexer 810, from the left in the figure, memory cells 0, 8 and Numbers 1, 2, 3, ... 7 are read. Then, the multiplexer 810
When the carry is 0, the memory cell number 0 is output to the bit line 0. When the carry is 1, the memory cell number 8 is output to the bit line 0. Bit lines 1-7 only pass through multiplexer 810 as shown.

Here, a problem is that the line connecting the memory cell No. 0 and the bit line 0-1 is long. This can increase access time. One method for solving this will be described with reference to FIG. 6 is different from FIG. 5 in that the memory array 610 is different.
This is the method of arranging the "rows" in That is, from the bottom of the figure,
The row address is arranged every other row, and in the range of 0 to the maximum value of the row address, the upper end of the memory array 610 is reached per address of half the maximum value. To place. By doing so, the line connecting the column address and the bit line can be crossed for at most one row.

The row address and the column address correspond to the upper address and the lower address, respectively, but in the memory array shown in FIGS. 5 and 6, the address is associated in 1-bit units. On the other hand, in a general computer today, an address is associated with a byte unit. Such a byte-addressed memory array is shown in FIG.
Alternatively, it is obvious that it can be realized by using eight memory arrays shown in FIG. At this time, the word lines can be shared.

The applications of the memory array 610 and the multiplexer 810 shown in FIGS. 5 and 6 are not limited to the storage device shown in FIG. 3 or 4. The memory array 610 and the multiplexer 810 shown in FIGS. 5 and 6 are characterized in that the carry generation delay is improved in the access from the address addition to the storage device, and the address as shown in FIGS. This is because it is not limited to the fact that there is no register on the route of access from the addition to the storage device.

Further, according to the present invention, for a memory cell having a column address of 0, the memory cell corresponding to the row address and the memory cell corresponding to the row address obtained as a result of adding 1 to the row address are respectively bit-wise. By connecting to a line, activation of a row address and generation of a carry for address addition can be performed in parallel. This makes it possible to improve the delay in the generation of the carry in the access to the storage device from the address addition. Therefore, as shown in FIGS. 5 and 6, in addition to the configuration in which the memory cell corresponding to the column address 0 is connected to the two bit lines via the switch, for example, for each of the two bit lines, A configuration in which a memory cell is provided (doubled) can also be considered, and the present invention is applied to FIGS.
The configuration is not limited to that shown in FIG.

[0073]

According to the present invention, the pipeline structure is improved so that the stage where the result of the operation instruction is obtained and the stage where the result of the load instruction is obtained are the same, and the data read from the memory by the load instruction is It is possible to eliminate the need for pipeline stalls to occur if the instruction immediately following that instruction requires it. Further, it is possible to reduce the number of cycles required to read the target instruction when executing the branch instruction. These can improve the performance of the computer system.

Further, the delay of the memory access from the address addition can be speeded up.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a configuration of a storage device used in an embodiment of the present invention.

FIG. 4 is a block diagram showing another example of the configuration of the storage device used in the embodiment of the present invention.

FIG. 5 is an explanatory diagram showing an example of a configuration of a memory array and a multiplexer used in an embodiment of the present invention.

FIG. 6 is an explanatory diagram showing another example of the configurations of the memory array and the multiplexer used in the embodiment of the present invention.

FIG. 7 is an explanatory diagram of a pipeline relating to execution of an arithmetic instruction and a load instruction in the conventional technique.

FIG. 8 is an explanatory diagram of a pipeline regarding reading of a target instruction in a branch instruction in the conventional technique.

FIG. 9 is a block diagram of a memory according to a conventional technique.

FIG. 10 is a timing chart when an instruction sequence including a load instruction of the present invention is executed.

FIG. 11 is a timing chart when an instruction sequence including a branch instruction of the present invention is executed.

FIG. 12 is a timing chart when an instruction sequence including a load instruction according to the related art is executed.

FIG. 13 is a timing chart when an instruction sequence including a branch instruction of the related art is executed.

FIG. 14 is an explanatory diagram of the third embodiment of the present invention.

FIG. 15 is an explanatory diagram of a pipeline when a cache storage device according to the related art is used.

[Explanation of symbols]

330, 410 ... Multiplexer, 611 ... Memory cell, 612 ... Switch, 613 ... Inverter.

Claims (14)

[Claims] 1. According to a result of decoding an instruction to be executed,
In a pipeline computer that accesses a data storage device by using a value obtained as a result of adding two data as an address, a value obtained as a result of inputting the two data output from the pipeline register and adding them A computer having a data storage device which is characterized in that there is no pipeline register on the route from accessing as an address to reading or writing data. 2. Depending on the result of decoding the instruction to be executed,
In a pipeline computer that accesses an instruction storage device by using a value obtained as a result of adding two data as an address, input a plurality of data output from a pipeline register, and give an address to a value obtained as a result of adding them. A computer having an instruction storage device, which is characterized in that there is no pipeline register on the route from which access is made as described above to read or write an instruction. 3. The register file according to claim 1,
A first pipeline register in which an instruction to be executed is set, and a second pipe in which the data read from the register file is set according to the result of decoding the output data of the first pipeline register. Input two data of the output of the second pipeline register of a pipeline computer having a line register and a third pipeline register in which the data read from the data storage device is set, A computer having a data storage device that does not have a pipeline register on the route from the value obtained as a result of adding as an address to access and reading or writing of data. 4. The register file according to claim 2,
A first pipeline register in which an instruction to be executed is set, and a second pipe in which the data read from the register file is set according to the result of decoding the output data of the first pipeline register. A pipeline register in which an instruction read from an instruction storage device is set in the first pipeline register, and input two data of the output of the second pipeline register. , A computer having an instruction storage device that has no pipeline register on the route from accessing the value obtained by adding them as an address and reading or writing the instruction. 5. The register file according to claim 1,
The data read from the register file is set in accordance with the adder, the first pipeline register in which the instruction to be executed is set, and the result of decoding the output data of the first pipeline register. Data in a second pipeline register, a third pipeline register that sets an output result of the adder that performs an operation using the data set in the second pipeline register as an operand, and data in a data cache storage device A fourth pipeline register in which data read from the array is set, wherein the data cache storage device stores the data, and the data array stores each of the data stored in the data array. Read from the directory that stores the entry containing the address information and the directory Of a pipeline calculator having a hit detection circuit that detects that desired data exists in the data read from the data array from the entry, and a selection circuit that selects the desired data from the output data of the data array, There is no pipeline register on the route from the input of the two data of the output of the second pipeline register, the access of the value obtained as a result of adding them, and the reading or writing of the data. calculator. 6. The register file according to claim 2,
The data read from the register file is set in accordance with the adder, the first pipeline register in which the instruction to be executed is set, and the result of decoding the output data of the first pipeline register. A second pipeline register; and a third pipeline register for setting an output result of the adder that performs an operation with the data set in the second pipeline register as an operand, and the first pipeline register An instruction read from the instruction cache storage device is set in the pipeline register, and the instruction cache storage device includes an instruction array for storing the instruction and an entry including address information of each of the instructions stored in the instruction array. The desired command from the directory storing the Of the output of the second pipeline register of the pipeline computer having a hit detection circuit for detecting the presence in the instruction read from the ray and a selection circuit for selecting a desired instruction from the output instruction of the instruction array. A computer that does not have a pipeline register on the route from inputting two data, accessing the value obtained as a result of adding them as an address, and reading or writing an instruction. 7. Depending on the result of decoding the instruction to be executed,
A pipeline computer in which a data storage device is accessed with a value obtained as a result of addition of three or more pieces of data as an address and three or more pieces of addition data are converted into two pieces of addition data using a carry save adder Data storage characterized by the fact that there is no pipeline register on the route from inputting the two data of the output of the register and accessing the value obtained as the result of adding them as an address and reading or writing the data A calculator with a device. 8. Depending on the result of decoding the instruction to be executed,
A pipeline computer in which a value obtained as a result of addition of three or more pieces of data is used as an address to access an instruction storage device and three or more pieces of added data are converted into two pieces of added data by using a carry save adder. Instruction storage characterized by the fact that there is no pipeline register on the route from inputting two data of register outputs, accessing the value obtained as a result of adding them as an address, and reading or writing an instruction A calculator with a device. 9. A word line to which an address is input, a memory cell which is associated with each address and stores 1-bit information, a switch controlled by the word line, and a memory cell and the switch. A second bit line controlled by the word line, and a memory cell corresponding to the address when the address is input by the word line. A first bit line is connected, a memory cell corresponding to an address obtained as a result of adding 1 to the address input from the address input line, and a memory array connected to the second bit line; A bit line, and a multiplexer connecting any one of the first bit line and the second bit line to the third bit line. That computer. 10. The address input signal line according to claim 1, 2, 7, 8 or 9, to which two addresses are input from the outside of the storage device, and the upper half of the middle of the two addresses. A first row decoder and a second row decoder for decoding, a barrel shifter in which the output signal of the first row decoder is shifted by the output signal of the second row decoder, and a word to which the output signal of the barrel shifter is input. Line and a memory array having first and second bit lines for inputting and outputting data, a carry lookahead circuit for generating a carry when the lower order of two addresses are added, and an output of the carry lookahead circuit And an adder for adding the lower half of the middle two of the addresses, and one of the first bit line and the second bit line of the memory array and the second bit line depending on the carry of the output of the adder. The first multiplexer for controlling the connection between the multiplexer and the third bit line for inputting / outputting data, the column decoder for decoding the output signal of the adder, and the input / output of data with the outside of the storage device are performed. A computer having a fourth bit line and having a second multiplexer for controlling connection between the third bit line and the fourth bit line by an output signal of the column decoder. 11. The address input line according to claim 1, 2, 7, 8 or 9, to which two addresses are input from the outside of the storage device, and the upper half of the middle of the two addresses are added. A first adder, a row decoder that decodes the output signal of the first adder, and a word line to which the output signal of the row decoder is input and first and second bit lines that input / output data. And a carry look-ahead circuit for generating a carry when the lower order of the two addresses are added, an output of the carry look-ahead circuit, and a lower order of the middle two addresses. A second adder, and a third input / output unit for inputting / outputting data to / from either the first bit line or the second bit line of the memory array or the second multiplexer by the carry of the output of the second adder. Controls connection with bit line The third multiplexer, the column decoder that decodes the output signal of the adder, and the fourth bit line that inputs and outputs data to and from the outside of the storage device. A second multiplexer that controls the connection with the four bit lines by the output signal of the column decoder. 12. A word line to which a decoded signal of a row address is input, a plurality of memory cells for storing a 1-bit signal, and a first bit line for inputting / outputting data. , A switch for controlling connection between the memory cell and an input / output signal by the word line, and a plurality of the memory cells are assembled to form a row memory cell, and each of the row memory cells has a row. An address is associated with each memory cell of each row memory cell, and each memory cell of each row memory cell is associated with a column address, and the first bit lines are the same in number as the number of memory cells in one row memory cell. Signal lines of all row memory cells and corresponding to the same column address of all row memory cells are respectively connected through the switches, and one of the word lines is activated to activate the memory cells. The switches connected to all the memory cells of one row memory cell of the address corresponding to the word line are turned on, and one second memory cell is connected to each of the first bit lines. Of one row memory cell corresponding to the address obtained by adding 1 to the address corresponding to the activated word line, and is connected to the memory cell whose column address is 0. Switch is turned on and has a memory array connected to the second bit line and a third bit line, and the first bit line and the second bit line whose column address corresponds to 0.
And a multiplexer that is connected to the third bit line and passes through the first bit line corresponding to a non-zero column address. 13. The memory array according to claim 12, wherein a memory array storing a large number of bits is composed of a large number of row memory cells, and memory cells storing a 1-bit signal are arranged in a straight line in each of the row memory cells. A group of straight lines having the same number of rows as the row memory cells in the memory array and arranged in parallel on a plane, one for each straight line.
In the memory array configured by arranging the row memory cells of one book, one row of each row memory cell is arranged in a certain direction in the order of row addresses corresponding to each of the row memory cells. Every other row memory cell is arranged on a straight line every other line, and if there is no straight line in a fixed direction, the row memory cells are not arranged yet in a direction obtained by rotating the fixed direction by 180 degrees, that is, in the reverse direction. If they are arranged on a straight line, and if there is no straight line in the inversion direction, then the row memory cells are arranged on the straight line which has not been arranged yet in the direction obtained by rotating the inversion direction by 180 degrees, that is, the original fixed direction. By doing so, between the row memory cell corresponding to the minimum row address and the row memory cell corresponding to the maximum row address,
Only one row memory cell is arranged at most, and only one row memory cell is arranged between two row memory cells corresponding to two consecutive row addresses. A computer having a memory array. 14. A computer having a memory array configured by using a plurality of the memory arrays according to claim 12 or 13.