JPH08114655A - Method and device for inspecting electrical characteristics of semiconductor device - Google Patents

Abstract

(57) [Summary] [Purpose] To realize parallel inspection while suppressing increase in inspection time and defect rate. In an inspection device 20 for inspecting a response signal output timing of an IC card, a response signal memory 35 for storing response signals from each DUT 1 and an expected value memory 35 by calling each response signal stored in the memory. A comparison unit 36 for comparing with a preset expected value is provided. The response signal of each DUT 1, 1 ... Is measured in parallel, and the response signal measured for each DUT is stored in the memory 3
It will be remembered in 3. After the elapse of the set time, each response signal stored in the memory 33 is called and compared with the expected value of the memory 35. As a result, the quality of the output timing of each response signal is determined. [Effect] The allowable range of the response signal measurement time can be set to a large range, and a decrease in the defective rate can be avoided. Since the determination work is performed later, the extension of the inspection time can be prevented. Multiple DUTs
Since the response signal output timing can be inspected in parallel, the inspection time can be shortened as compared with the case of serial execution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for inspecting electrical characteristics of a semiconductor device, and more particularly to a technique for inspecting a response signal of the semiconductor device, for example, for inspecting an asynchronous response timing device such as an IC card or an ASIC. Regarding what is valid to use.

[0002]

2. Description of the Related Art For example, an IC of a logic device (logical device; hereinafter referred to as logic) product of a semiconductor device.
In cards, ASICs, and the like (hereinafter sometimes referred to as asynchronous response timing devices), the output timing of the response signal tends to differ greatly among the devices in many cases.

Therefore, conventionally, when the electrical characteristic inspection of such an asynchronous response timing device is carried out by a general-purpose logic IC tester, the inspection of the output timing of the response signal is executed for each device (serially). Has been done. This is because if the output timings of the response signals greatly differ from device to device, the output timings of the response signals cannot be simultaneously (parallelly) compared and determined depending on the same strobe signal. The inspection of the response signal output timing for each output pin in each asynchronous response timing device is also performed for each pin (serially). This is because when the response signal output timing of multiple output pins is tried to be inspected at the same time (in parallel), the test pattern becomes complicated and the application
This is because it takes a long time to develop the program.

An example of a tester for random logic is "Electronic Material 1" issued by Kogyo Kogyo Kenkyukai Co., Ltd.
November, 984 issue, separate volume, issued November 20, 1984
There are P157 to P164.

[0005]

However, if the inspection of the response signal output timing is performed serially for each device and also for each pin as described above, the response signal output timing inspection time The IC tester for logic cannot be used for the inspection of other important electrical characteristic items due to the extension of the inspection time, so that the IC tester for logic is extremely expensive. There is a problem in that it cannot be fully utilized.

Therefore, it is conceivable to execute a so-called parallel inspection also for the inspection of the response signal output timing in the asynchronous response timing device. However, in order to realize this, there are the following problems in eliminating the mutual variation between the response signal timings. (1) It is essentially impossible to cancel the response signal timing on the asynchronous response timing device side. (2) When the control signal is set so as to absorb the variation in response signal timing by the maximum delay time,
Even if the parallel inspection is executed, the inspection time will be long after all. (3) When the control signal is set so that the variation in response signal timing is absorbed by the minimum delay time,
The defective rate becomes high and the yield is unduly reduced.

An object of the present invention is to provide a technique for inspecting electrical characteristics of a semiconductor device which can realize parallel inspection while suppressing an increase in inspection time and defective rate.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The typical ones of the inventions disclosed in the present application will be outlined below.

That is, in a semiconductor device electrical characteristic inspection apparatus for inspecting a response signal of a semiconductor device, a memory for storing a response signal from the semiconductor device and a response signal stored in the memory are called and preset. And a comparison means for performing the inspection by comparing with the expected value.

[0011]

In the above-mentioned means, for example, when response signals of the same kind are measured in parallel for a plurality of semiconductor devices, the response signals measured for each semiconductor device are stored in the memory at any time. Then, for example, after a preset allowable delay time has elapsed, each response signal stored in the memory is called and compared with a preset expected value. By this comparison, for example, the quality of the output timing of each response signal is determined.

According to the above-mentioned means, since the response signal from the semiconductor device is temporarily stored in the memory, it is possible to set a large allowable range for the response signal measurement time. Therefore, it is possible to avoid the occurrence of a situation in which the defective rate is lowered by setting the allowable range narrow. On the other hand, since the actual determination work is executed after the measurement, even if the allowable range of the measurement time is set relatively wide, the time of the entire inspection work is not affected.

For example, when response signals of the same kind are measured in parallel for a plurality of semiconductor devices, the output timings of the response signals for the plurality of semiconductor devices can be inspected at the same time. Compared with the case where the response signal inspection work for the device is performed serially, the inspection time as a whole can be significantly shortened.

[0014]

1 is a block diagram showing a response signal inspection apparatus for an IC card according to an embodiment of the present invention. FIG. 2 is an explanatory diagram for explaining the operation.

In this embodiment, the semiconductor device electrical characteristic inspection apparatus according to the present invention is configured as an IC card response signal inspection apparatus for inspecting the output timing of the response signal of the IC card. An IC card (hereinafter also referred to as a DUT) as an inspection target is a kind of microcomputer equipped with logic and is an example of an asynchronous response timing device.

In this embodiment, the IC card response signal inspection method is used to inspect the output timing of the logic response signal for the IC card which is the DUT. First, when the method for inspecting the electrical characteristics of an IC card is carried out, a large number of IC cards (DUT) 1 to be inspected are removably attached to a testing board (not shown) via each contact. . The DUTs 1 mounted on the testing board are electrically connected to the response signal inspection device 20 of the IC card in parallel via the connector group.

On the other hand, the response signal inspection device 20 for an IC card according to the present embodiment is substantially configured as a part of a logic IC tester (not shown), and includes a central processing unit (CPU) 21 and a main unit. Memory 22, logic pattern generator 23, timing generator 24,
Pattern formatter 25, driver 26, sampling signal generator 27, start setting section 28, end setting section 2
9, an H comparator 30, an L comparator 31, a latch circuit 32, a response signal memory 33, an address controller 34, an expected value memory 35, and a comparison unit 36.

The CPU 21 is a CPU of a logic IC tester
It is constructed by computer hardware and software, and together with the operation of each component (not shown) of the tester, the response signal inspection device 20 for the IC card
The operation of each of the components can be centrally controlled. The main memory 22 is a memory of the logic IC tester, stores an algorithm of the CPU 21, testing information, and the like, and the stored data is configured to be called by the CPU 21 at an arbitrary and high speed.

The logic pattern generator 23 is CP
It is configured to generate a testing signal to be actually used based on the testing information stored in advance in the main memory 22 of the U21 and send it to the pattern formatter 25. The timing generator 24 is a generator that specifies the rising and falling timings of the waveform in order to generate the pulse signal from the logic pattern generator 23 into a pattern signal having a pulse width by the pattern formatter 25. The pattern formatter 25 is necessary to test the function of the DUT 1,
It is a circuit that generates a pattern signal to be supplied to each input pin of the DUT 1. In the present embodiment, the pattern formatter 25 will generate a pattern signal for obtaining a desired response signal from the DUT 1.

The driver 26 is an interface portion on the input side with the DUT 1 and supplies the signal from the pattern formatter 25 to the input pin of the DUT 1. In this embodiment, a plurality of drivers 26 (only a part of which are shown) are provided, and the command signals from the pattern formatter 25 are respectively supplied to designated input pins of a plurality of DUTs 1. Has become.

The sampling signal generator 27 is a DU
It is for generating a sampling signal necessary for storing the response signal from T1 in the memory 33, and based on the timing signal from the timing generator 24, it is constant as shown in FIG. Is configured to generate a sampling signal having a pulse width of. The start period setting unit 28 is a setting unit for instructing the generation start time of the sampling signal, and the end period setting unit 29 is a setting unit for instructing the generation end time of the sampling signal. The start command of the start setting unit 28 and the end setting unit 29
And the end command of (3) define the sampling period of the response signal. During this sampling period, when the output timing of the response signal is inspected, variations in the output timing of the response signal from the DUT1 are detected by a plurality of DUT1s.
Is set within the shortest period that can be absorbed over the entire period, without increasing the testing time excessively and capable of suppressing the increase of the defective rate of testing most efficiently. For example, the start time is the time when the response signal output timing is the earliest among the past data regarding the same type of DUT, and the end time is the time when the response signal output timing is the latest. The sampling period is different from the permissible time T described later.

The H-comparator 30 and the L-comparator 31 are interfaces on the output side with the DUT 1.
It receives a response signal from the output pin of the designated DUT 1. The H-comparator 30 and the L-comparator 31 form a pair, and a plurality of pairs are provided in the present embodiment, and each pair is electrically connected to a designated output pin of each DUT 1. In each DUT 1, the output pin to which the pair of comparators 30 and 31 is connected corresponds to the input pin to which the driver 26 is connected, and outputs a response signal corresponding to the input signal.

The latch circuit 32 is a set of H comparators 3.
A pair is formed corresponding to the 0 and L comparators 31, and a plurality of sets are provided corresponding to the pair of comparators. In each set, the output terminal of the H comparator 30 is connected to the D terminal of one latch circuit 32, and the output terminal of the L comparator 31 is connected to the D terminal of the other latch circuit 32. Further, the sampling signal generator 2 is connected to the clock (C) terminals of both latch circuits 32, 32.
The seven output terminals are connected to each other to supply the sampling signal. Both latch circuits 32, 3
The Q terminals of 2 are connected to the response signal memory 33 for each set.

The response signal memory 33 is adapted to sequentially store the response signals transmitted from the latch circuits 32, 32 of each set, for each set under the address control of the address controller 34. That is, the response signal memory 33 is configured to store the response signals from each DUT 1 separately.

The expected value memory 35 is a signal (expected value) that the DUT 1 itself should output in response to a command signal generated by the pattern formatter 25 and input to the DUT 1.
Is memorized. The expected value signal is generated in advance in response to the signal to the logic pattern generator 23 based on the testing information stored in the main memory 22 of the CPU 21, and stored in the expected value memory 35. By the way, the expected value memory 35 and the response signal memory 33 are the main memory 22.
Can also be shared.

The comparison unit 36 sequentially calls each response signal stored in the response signal memory 33 to obtain the expected value memory 3
By comparing with the expected value stored in 5, the output timing error is obtained for each response signal, and each error is within the range of the tolerance (allowable time T, see FIG. 2A). It is configured to respectively determine whether or not. That is, the comparison unit 36 has an error tolerance (allowable time T).
If it is within the range, it is determined to be good, and if it is out of the range, it is determined to be defective. By the way, the comparison unit 36 is a CP
It can be built by sharing the U21 logic circuit,
It can also be programmed as software.

Next, the operation of the response signal inspection device for an IC card according to the above configuration will be described, and the response signal inspection method for an IC card according to one embodiment of the present invention will be described with reference to FIG.

When the response signal inspection method for an IC card is carried out, a large number of IC cards as DUTs are electrically connected to the testing board via each contact. The DUTs 1 mounted on the testing board are connected to the response signal inspection device 20 of the IC card in parallel with each other.

After the DUT 1 group is connected, the testing signal generated by the pattern formatter 25 according to the instruction of the CPU 21 is input to each DUT 1 in parallel via the driver 26.

Each of the DUTs 1, 1 ... Operates in response to the input signal and outputs a predetermined response signal in parallel. For example, if the input signal is "Is the RAM operation normal?", The DUT 1 outputs a response signal of "RAM operation is normal." Each DUT 1, 1
The response signals output in parallel from ...
The waveforms are respectively shaped by the H comparator 30 and the L comparator 31 of each set corresponding to 1, and the latch circuit 3 of each set corresponding to the comparators 30 and 31 of each set.
It is applied to the D terminals of 2, 32, respectively.

Each latch circuit 32 corresponds to the sampling signal from the sampling signal generator 27 and corresponds to FIG.
As shown in (e), each set of comparators 3
The signals from 0 and 31 are sampled for each point, and the state for each point is input to the response signal memory 33 in parallel. The inputs to the response signal memory 33 can be simultaneously executed by the latch circuits 32 of each set, so that the parallel processing is executed.

The response signal memory 33 sequentially stores the state of each point transmitted in parallel from each set of latch circuits 32. At this time, the response signal memory 33
Is controlled by the address controller 34,
The state of the points from one set of the latch circuits 32 is divided and stored as continuous time series (signal waveform). Here, since each set of latch circuits 32 corresponds to each DUT 1, 1 ..., The signal waveforms (time series in which sampling points are continuous) stored in each section of the response signal memory 33 are each DUT 1 Of the response signal. That is, the response signal memory 33 stores each DUT 1,
The response signals from 1 ... are stored for later identification.

Then, the start setting unit 28 and the end setting unit 29
When the sampling period preliminarily defined by and has elapsed, the operation of storing the response signal of each DUT 1 in the response signal memory 33 is terminated. In this state, the storage of the response signal is completed for all DUT1s. By any chance
The DUT 1 in which the storage of the response signal has not been completed is determined to be defective because the delay degree of the response timing is too large. However, since the sampling period is sufficiently long, it is possible to prevent the defect rate from becoming unreasonably high.

After the sampling period has elapsed or a preset period has elapsed, the comparison unit 36 sequentially calls each response signal stored in the response signal memory 33 to obtain the expected value stored in the expected value memory 35. Compare with. By this comparison, the output timing error of each response signal is obtained, and it is determined whether or not each error is within the allowable time (tolerance). That is, the comparison unit 36 determines that the error is good when the error is within the allowable time, and determines that the error is outside the error time.

For example, as shown in FIG.
(A) is an expected value signal, the allowable time (tolerance) of output timing is T, (b) is a response signal sent from the first DUT, (c) is a response signal sent from the second DUT Is assumed. Since the response timing of the signal in (b) is within the range of the allowable time T in (a), the first D
The comparison unit 36 determines that the UT is “good”. On the other hand, since the response timing of the signal of (c) is not within the range of the allowable time T of (a), the comparison unit 36 determines the second DUT to be “defective”.

When it is determined as "defective" as in the second DUT, the fact is transmitted to the CPU 21 by the comparison unit 36. The CPU 21 excludes the second DUT from the inspection target. By this exclusion, for example, the work time of the inspection for other inspection items is shortened.

On the other hand, in the comparison unit 36, while the inspection work for the output timing of the response signal is being executed, the CPU 21 causes each DUT 1 to simultaneously perform the inspection work for the other inspection items. The other inspection items also include the inspection of the output timing of the response signal to the pin different from the inspected pin of each DUT 1.

According to the above-mentioned embodiment, the following effects can be obtained. (1) Since the response signal inspection can be simultaneously (parallel) performed on a plurality of DUTs, the workability of the response signal inspection can be significantly improved.

(2) Since the response signal from the DUT is temporarily stored in the response signal memory, the allowable range for the response signal measurement time can be set large, so that the allowable range is set narrow. By doing so, it is possible to avoid the occurrence of a situation in which the defective rate decreases, and on the other hand, since the actual comparison and determination work is performed after measurement, even if the allowable range of measurement time is set relatively wide. , The time of the inspection work as a whole is not affected.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the sampling signal is not limited to being generated by using the timing generator, but a dedicated oscillator or clock circuit may be used.

The means for storing the response signal from each DUT in the response signal memory is not limited to the configuration using the H comparator, the L comparator, the latch circuit, and the address controller, but other configurations may be used. May be.

The response signal inspection device for an IC card is not limited to being incorporated in a logic IC tester, but can be incorporated in a wafer prober or an auto handler.

In the above description, the case where the invention made by the present inventor is mainly applied to the response signal inspection technology of the IC card which is the field of application which is the background has been described, but the invention is not limited thereto and the ASIC is not limited thereto. It can be applied to general logic such as. In particular, the invention is
Asynchronous response timing, in which the output timing of the response signal greatly varies between individual devices (individual products). It is possible to obtain excellent effects when used for the output timing inspection of the response signal of a device.

In the above-described embodiment, the case of inspecting the output timing of the response signal has been described, but the present invention is not limited to this, and it can be applied to the pass / fail judgment of the response signal itself, and other general electrical characteristic inspections for semiconductor devices. You can

In the above embodiment, the case of parallel inspection for a plurality of DUTs has been described, but the present invention can be applied to the case of parallel inspection for each pin in each DUT. Further, it goes without saying that the present invention can be applied to serial inspection for individual pins of individual DUTs.

[0047]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

After the response signal from the semiconductor device is temporarily stored in the memory, the stored response signal is called to perform a substantial inspection work, thereby setting a large allowable range for the measurement time of the response signal. can do. As a result, it is possible to avoid the occurrence of a situation in which the defective rate is lowered by setting the allowable range of the response signal measurement time narrow. On the other hand, since the substantial inspection work is executed after the measurement, even if the allowable range of the measurement time is set relatively wide, the time of the entire inspection work is not affected.

As a result, the response signals of a plurality of semiconductor devices or a plurality of pins can be obtained by measuring the response signals of the same kind in parallel for a plurality of semiconductor devices or a plurality of pins in each semiconductor device. Since the inspection can be performed in parallel, the time required for the entire inspection operation can be significantly reduced as compared with the case where the response signal inspection operation is serially performed on a plurality of semiconductor devices or a plurality of pins.

[Brief description of drawings]

FIG. 1 is a block diagram showing an IC card response signal inspection apparatus according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining its operation.

[Explanation of symbols]

1 ... DUT (semiconductor device), 20 ... IC card response signal inspection device, 21 ... CPU, 22 ... Main memory, 23
... logic pattern generator, 24 ... timing generator, 25 ... pattern formatter, 26 ... driver, 27 ... sampling signal generator, 28 ... start setting section, 29 ... end setting section, 30 ... H comparator, 3
1 ... L comparator, 32 ... Latch circuit, 33 ... Response signal memory, 34 ... Address controller, 35 ... Expected value memory, 36 ... Comparison section.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideaki Mayuzumi 3-3, Fujihashi, Ome-shi, Tokyo 2 Hitachi Hitachi Electronics Co., Ltd.

Claims (3)

[Claims] 1. A method of inspecting an electrical characteristic of a semiconductor device for inspecting a response signal of the semiconductor device, wherein a response signal from the semiconductor device is stored in a memory.
After that, the response signal stored in the memory is called and compared with a preset expected value, and the inspection is executed. 2. The electrical characteristic of the semiconductor device according to claim 1, wherein a plurality of response signals of the same type are measured in parallel, and the measured response signals are respectively stored in a memory at any time. Inspection methods. 3. An electrical characteristic inspection device for a semiconductor device, which inspects a response signal of a semiconductor device, wherein a memory for storing a response signal from the semiconductor device and a response signal stored in the memory are called and preset. An electrical characteristic inspection apparatus for a semiconductor device, comprising: a comparison unit that executes an inspection by comparing with an expected value.