JPH0811069Y2 - Motor control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a motor control device, and more particularly to a motor control device capable of stably varying the rotation speed of a motor.

[Conventional technology]

For example, the DAT capstan motor requires that one motor rotate accurately at a wide variety of speeds. Therefore, a motor control device including a digital PLL and a motor controller is used to control the speed of the motor. ing.

Specifically, as shown in FIG. 4, a frequency generator 12 is first coupled to the motor 10 and an FG signal having a frequency k times the motor rotation frequency is output (where k is a predetermined integer).

This FG signal is amplified and waveform-shaped by the FG amplifier / waveform shaping circuit 14 and is output to the detection signal input terminal SIG of the motor control IC 16 as a rotation pulse generated k times in accordance with one rotation of the motor 10.

Further, the output of the variable frequency reference frequency signal generator 18 is input to the reference signal input terminal REF of the motor control IC 16.

The motor control IC 16 includes a phase comparator 20, LPF22, VCO
24, a digital PLL in which a frequency divider 26 is loop-connected is included.

The output of the reference frequency signal generator 18 is input to the phase comparator 20 as a reference signal. When the frequency of the reference signal is F _ref and the frequency division ratio of the frequency divider 26 is N, the VCO 24 outputs F
pulses locked _ref to N Tei multiplied by the frequency N · F _ref is output (where N is a predetermined integer).

Further, the motor control IC 16 is provided with a measuring device 28, and the measuring device 28 counts the cycle of the rotation pulse by using the output of the VCO 24 as a clock to obtain the difference from the predetermined set value P.

For example, when N = P = 2560, the target rotation speed value ω ₀ of the motor 10 is 2πF _ref / k, and the clock pulse during one cycle of the rotation pulse is matched so that the cycle of the rotation pulse matches the cycle of the reference frequency signal. If the number is greater than 2560, motor 10
The error component is output from the measuring device 28 on the assumption that the number of rotations is slower than a predetermined value. On the contrary, if the clock coefficient value for one cycle of the rotation pulse is less than 2560, it is determined that the rotation speed of the motor 10 is faster than the predetermined value, and the error component is output from the measuring instrument 28.

This error data is converted into an analog error signal by the D / A converter 30, and then output from the output terminal OUT of the motor control IC 16 to the outside.

The error signal is compensated by the compensating circuit 32 to have an optimum gain and phase, and then sent to the driving circuit 34. The drive circuit 34 drives the motor 10 according to the output of the compensating circuit 32 to match the rotation speed with the target value.

Here, the signal frequency F _ref of the reference frequency signal generator 18 is switched by the system control circuit 36 as needed, and the output frequency of the VCO 24 changes accordingly and the rotational speed target determined by 2πF _ref / k The value ω ₀ is changed and set, and the control system works to variably control the rotational speed of the motor 10 to this new target value.

[Problems to be solved by the invention]

However, in the above-mentioned conventional technology, when changing the set speed of the motor 10, the reference frequency signal generator 18 is variably set and controlled, and the frequency of the reference frequency signal is changed.
When the frequency is changed abruptly, the motor control system cannot follow this frequency change, and the drive voltage that is step-responsive to the motor is applied and the rotation speed does not change smoothly, or overshoot occurs. In some cases, an unstable rotation state may occur.

In view of the problems of the prior art, the present invention has an object to provide a motor control device capable of stably varying a motor speed.

[Means for solving problems]

In the motor control device according to the present invention, a reference frequency signal generating means for generating a variable frequency reference frequency signal and a PLL loop filter are included, and the reference frequency signal generated by the reference frequency signal generating means is
PLL means that obtains a clock output with double frequency, speed detection means that generates a pulse of a frequency proportional to the rotation speed of the motor, and the cycle of the output pulse of the speed detection means by using the clock output from the PLL means An upper limit of the control band of the PLL loop filter is provided, which comprises a measuring means for measuring and obtaining a difference from a predetermined set value, and a controlling means for controlling the motor so that the difference obtained by the measuring means becomes zero. Is set so as not to exceed the upper limit of the control band of the motor control system including the motor, the speed detecting means, the measuring means, and the controlling means.

〔Example〕

One embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram of a motor control device according to the present invention.

First, the frequency generator 12 is coupled to the motor 10 to output an FG signal having a frequency k times the motor rotation frequency (however,
k is a predetermined integer value).

FG amplifier / waveform shaping circuit on the output side of frequency generator 12
14 is connected, where the FG signal is amplified and the waveform is shaped, and output as k rotation pulses generated in accordance with one rotation of the motor 10.

The output side of the FG amplifier / waveform shaping circuit 14 is connected to a variable frequency divider 15 capable of varying the frequency division rate by external control. If the frequency division ratio of this variable frequency divider 15 is n, the rotation pulse The frequency is divided into 1 / n and the divided rotation pulse is output (where n is an externally set integer value).

The output side of the variable frequency divider 15 is connected to the detection signal input terminal SIG of the motor control IC 16.

The output side of the reference frequency signal generator 18 whose frequency can be varied by external control is also connected to the reference signal input terminal REF of the motor control IC 16.

In the motor control IC 16, the reference signal input terminal REF is connected to one input side of the phase comparator 20. The output side of this phase comparator 20 is connected to VCO24 via LPF22,
The output side of the VCO 24 is connected to the other input side of the phase comparator 20 via the frequency divider 26 to form a digital PLL.

The phase comparator 20 detects the phase difference between the reference frequency signal output by the reference frequency signal generator 18 and the output of the frequency divider 26. The low frequency band of this phase difference signal is filtered by the LPF 22 as a loop filter and is input to the VCO 24 as a frequency control voltage.

The VCO 24 oscillates at a frequency according to the frequency control voltage.
The oscillation signal is frequency-divided by the frequency divider 26 at a predetermined frequency division ratio N and then sent to the phase comparator 20 (where N is a predetermined integer value).

Therefore, when the digital PLL is locked, the VCO24
The frequency of the reference frequency signal which When F _ref oscillates at a frequency of N Tei multiplied by N · F _ref, and outputs an oscillation signal as a clock signal.

The output side of VCO24 and the detection signal input terminal SIG are for motor control
It is connected to a measuring device 28 provided in the IC 16, and the measuring device 28 counts the period of the frequency division rotation pulse using the VCO 24 output as a clock to obtain the difference from a predetermined set value P.

For example, when N = P = 2560, the target rotation speed value ω ₀ of the motor 10 is 2πnF _ref / k, and one cycle of the divided rotation pulse is matched to match the cycle of the divided rotation pulse with the cycle of the reference frequency signal. If the clock count value is greater than 2560, it is determined that the rotation speed of the motor 10 is slower than a predetermined value, and the error is output from the measuring device 28.

Conversely, the clock count value for one cycle of the divided rotation pulse is 25
If it is less than 60, it is determined that the rotation speed of the motor 10 is faster than a predetermined value, and the error is output from the measuring device 28.

A D / A converter 30 is connected to the output side of the measuring instrument 28, which converts the speed error data sent from the measuring instrument 28 into an analog value and outputs it as a speed error signal from the output terminal OUT of the motor control IC 16 to the outside. Output.

The compensating circuit 32 is connected to the output terminal OUT of the motor control IC 16, and the speed error signal is compensated for the optimum gain and phase here.

A drive circuit 34 is connected to the output side of the compensating circuit 32, and drives the motor 10 according to the output of the compensating circuit 32 to match the rotation speed with a target value.

Here, the system control circuit 36A is connected to the variable frequency divider 15 and the reference frequency signal generator 18, and the frequency division ratio n and the frequency F _{ref of the} reference frequency signal are controlled by the control circuit 36A.
It can be switched as necessary, and accordingly, the frequency division ratio of the variable frequency divider 15 changes, the VCO24 output frequency changes, and the rotation speed target value ω _{0 of the} motor 10 is changed and set. In addition, the rotation speed of the motor 10 is variably controlled to this new target value by the action of the control system.

The control band of the LPF22 of the digital PLL includes the motor 10, the frequency generator 12, the FG amplifier / waveform shaping circuit 14, the variable frequency divider 15, the measuring instrument 28, the D / A converter 30, the compensation circuit 32, and the drive circuit 34. The upper limit of the control band of the LPF 22 is lower than the upper limit of the control band of the motor control system because the upper limit of the control band of the LPF 22 is narrower than the control band of the motor control system to be connected. (See Figure 2). In other words, the response speed of the digital PLL is set slower than the response speed of the motor control system.

 Next, the operation of the above embodiment will be described.

 The motor 10 will be described here as a DC motor.

Now, when the rotation speed of the motor 10 is ω (rad / sec) and the number of FG pulse signals output by the frequency generator 12 per rotation of the motor 10 is k (puls / rev.), The FG amplifier / The frequency of the output pulse of the waveform shaping circuit 12 is ωk / 2π (H
z).

Therefore, assuming that the frequency division ratio of the variable frequency divider 15 is n (n is an externally set integer), the output frequency of the variable frequency divider 15 is ωk / 2.
It becomes πn (Hz).

On the other hand, the frequency of the signal output from the reference frequency signal generator 18 is set to F _ref (Hz, F _ref is an externally set value), and the frequency divider
When the division ratio of 26 is N (N is a predetermined integer), the frequency of the clock output by the VCO 24 is NF _ref (Hz).

Assuming that the set value of the measuring device 28 is P, the motor control system of FIG. 1 has a cycle of the output pulse of the variable frequency divider 15 of 2πn / ωk.
Since control is performed so that (s) coincides with P / NF _ref , 2πn / ωk = P / NF _ref (1) holds in the stable state.

Therefore, the rotation speed of the motor is expressed by ω = (2πn / k) · (NF _ref / P) (2).

That is, the motor is proportional to the frequency F _ref of the reference frequency signal.
It can be seen that the rotation speed of 10 changes. Further, the rotation speed of the motor 10 can be changed by changing the division ratio n of the variable frequency divider 15.

Incidentally, the oscillation range of the VCO24, F _osc (MIX) ~F
_{If osc} (MAX), NF _ref must satisfy the relationship of F _osc (MIX) ≤ NF _ref ≤ F _osc (MAX), and therefore F _ref is F _osc (MIX) / N ≤ F _ref It must be within the range of _{≤F osc} (MAX) / N (3).

From the formula (2), F _ref = ωkP / 2πnN, so if this is substituted into the formula (3), F _osc (MIX) ≦ ωkP / 2πn ≦ F _osc (MAX)
Regarding the rotation speed ω of 10, it is required that 2πnF _osc (MIX) / kP ≦ ω and ω ≦ 2πnF _osc (MAX) / kP (4).

Here, ω is F _osc (MI
X) and F _osc (MAX) can only be changed within the range defined by
Even if F _ref is changed beyond the range of the formula (3), accurate speed control cannot be performed.

However, in this embodiment, since n in the equation (4) can be changed, the variable of F _ref is performed within the range satisfying the relation of the equation (3), while changing n changes the range of speed change of the motor 10. It will be possible to expand.

Specifically, for example, N = P = 2560, _Fosc (MIX) = 500
If kHz and F _osc (MAX) = 2.5MHz, the reference frequency signal F _ref can be varied within the range of 195 ≤ F _ref ≤ 976 (Hz) (5) from the formula (3). Circuit 36A
In the variable setting control of, when the reference frequency signal generator 18 and the variable frequency divider 15 are set to F _ref = 400 and n = 1 respectively, the rotational speed is ω = 800π / k from the formula (2). The speed of the motor 10 is controlled as a target value.

At this time, the oscillation frequency of the VCO 24 is NF _ref = 1.024MHz.

If the speed of the motor 10 exceeds the target value for some reason, the cycle of each output pulse of the frequency generator 12, the FG amplifier / waveform shaping circuit 14, and the variable frequency divider 15 becomes small. Then, in the measuring instrument 28, the count value of the cycle of the divided rotation pulse is
It becomes less than 2560, and speed error data indicating a speed increase from the target value is output to the D / A converter 30.

The D / A converter 30 converts the speed error data sent from the measuring device 28 into an analog amount and outputs a speed error signal indicating a speed increase. The speed error signal is sent to the compensating circuit 32 to be compensated for gain and phase, and then input to the driving circuit 34.

The drive circuit 334 receives the motor 10 according to the input from the compensation circuit 32.
The output voltage to the motor 10 is lowered to slow down the rotation speed of the motor 10.

Conversely, if the speed of the motor 10 falls below the target value, the cycle of each output pulse of the frequency generator 12, the FG amplifier / waveform shaping circuit 14, and the variable frequency divider 15 becomes large. Then, in the measuring instrument 28, the count value of the cycle of the divided rotation pulse becomes more than 2560, and the speed error data indicating the speed decrease from the target value is D / A.
Output to converter 30.

The D / A converter 30 converts the speed error data sent from the measuring device 28 into an analog amount and outputs a speed error signal indicating a speed decrease. The speed error signal is sent to the compensating circuit 32 to be compensated for gain and phase, and then input to the driving circuit 34.

The drive circuit 34 increases the output voltage to the motor 10 according to the input from the compensation circuit 32 to increase the rotation speed of the motor 10.

In this way, when the rotation speed of the motor 10 fluctuates, feedback is applied to restore the original speed.

In this state, when it is desired to increase the rotation target value of the motor 10 to, for example, twice, there is still a margin in F _ref from the equation (5).
The system control circuit 36A remains n = 1, and only the reference frequency signal generator 18 is variably set and controlled so that F _ref = 800 Hz.

Then, the lock state of the digital PLL loop is once released, and the pull-in operation causes the oscillation frequency of the VCO 24 to rise and change to NF _ref = 2.048 MHz after a certain period of time to lock to this frequency. In other words, the VCO24 output clock cycle becomes shorter.

Since the control band of LPF22 is set low, even if the frequency of the reference frequency signal changes suddenly, LPF2
The pull-in action is made relatively slow by the integral action of 2, and V
CO24 output frequency changes gently.

As is clear from the equation (2), the target rotational speed of the motor 10 continuously increases from ω = 800π / k as the oscillation frequency of the VCO 24 changes, and finally doubles to 1600π / k.

When the clock cycle of the VCO 24 becomes shorter, the measuring instrument 28 increases the coefficient value of one cycle of the divided rotation pulse, and since P is constant, the rotation speed of the motor 10 becomes relatively slow, which is a speed error data. Is output.

Therefore, the D / A converter 30 outputs a speed error signal indicating that the rotation speed of the motor 10 is slow, and the compensation circuit 32
By the action of the drive circuit 34, the rotation speed of the motor 10 is increased.

This increase in the rotation speed of the motor 10 causes the frequency generator 12, FG
The frequency of the output of the amplifier / waveform shaping circuit 14 and the variable frequency divider 15 also rises, and the cycle of the divided rotation pulse becomes short.

However, since the clock cycle is further shortened while the frequency of the VCO 24 output is increasing, the measuring instrument 28 outputs speed error data indicating that the speed of the motor 10 has slowed down again.

Therefore, the D / A converter 30 outputs a speed error signal indicating that the rotation speed of the motor 10 is slow, and the compensation circuit
The rotation speed of the motor 10 is increased by the action of 32 and the drive circuit 34.

The same control operation is repeated thereafter, and the oscillation frequency of the VCO 24 becomes a steady state, and when the rotation speed of the motor 10 rises to a target value determined by this frequency and becomes stable, the speed error data output by the measuring instrument 28 becomes zero. And the motor 10
Is driven at a constant speed.

 As a result, the rotation speed of the motor 10 is doubled.

The control band of LPF22 (loop filter) of digital PLL is frequency generator 12, FG amplifier / waveform shaping circuit 14, variable frequency divider circuit 15, measuring instrument 28, D / A converter 30, compensation circuit 3
2. Since the frequency is narrower than the control band of the motor control loop consisting of the drive circuit 34 and only in the low band part, the frequency of the VCO24 output gradually changes until a new lock state is reached as described above. Data output and D /
The change in the speed error signal output from the A converter 30 also becomes gentle.

Therefore, the motor control loop can reliably follow the speed error signal, the outputs of the compensation circuit 32 and the drive circuit 34 also change gently, and the rotation speed of the motor 10 increases smoothly.
The speed can be changed smoothly according to the change in the output frequency of O24, and the steady state is quickly achieved.

On the other hand, if the upper limit of the control band of the LPF22 is higher than the upper limit of the control band of the motor control loop, when the frequency of the reference frequency signal is switched, the lock state of the digital PLL loop is released, and then the pull-in operation is performed quickly. Is performed, the oscillation frequency of the VCO 24 increases rapidly, and the speed error data also changes suddenly.

On the other hand, since the response of the motor control loop to the sudden change of the speed error data (speed error signal) is slow, the speed error data output of the measuring instrument 28 and the speed error signal output from the D / A converter 30 become large, and the compensation circuit The output level of 32 also changes greatly, so the output of the drive circuit 34 also changes greatly and the motor
A step-responsive driving voltage is applied to 10, causing the speed to stop changing smoothly or causing overshoot.

In this way, when the motor 10 is rotating at the speed of 1600π / k and when it is desired to reduce the motor speed to 1/4, the system control circuit 36A changes the reference frequency signal oscillator 18 in a variable manner. Perform reference frequency signal frequency F _ref
200Hz

Then, the lock state of the digital PLL loop is once released, and the pull-in operation causes the oscillation frequency of the VCO 24 to decrease, and after a certain period of time, it changes to NF _ref = 256 kHz, and locks to this frequency. In other words, the cycle of the VC024 output clock becomes long.

Since the control band of LPF22 is set low, even if the frequency of the reference frequency signal changes suddenly, LPF2
The pull-in action is made relatively slow by the integral action of 2, and V
CO24 output frequency changes gently.

As is clear from the equation (2), the target value of the rotation speed of the motor 10 continuously decreases from ω = 1600π / k as the oscillation frequency of the VCO 24 changes, and finally becomes a quarter of 400π / k. Become.

When the clock cycle of the VCO 24 becomes longer, the measuring instrument 28 decreases the count value of one cycle of the divided rotation pulse, and since P is constant, the speed error data indicating that the rotation of the motor 10 becomes relatively fast. Is output.

Therefore, the D / A converter 30 outputs a speed error signal indicating that the rotation speed of the motor 10 is high, and the compensation circuit 32
The drive circuit 34 functions to reduce the rotation speed of the motor 10.

Due to the decrease in the rotation speed of the motor 10, the frequency generator 12, FG
The frequency of the output of the amplifier / waveform shaping circuit 14 and the variable frequency divider 15 is also reduced, and the cycle of the divided rotation pulse is lengthened.

However, when the frequency of the VCO 24 output is decreasing, the clock cycle is further lengthening, so the speed error data indicating that the speed of the motor 10 has increased again is output from the measuring instrument 28.

Therefore, the D / A converter 30 outputs a speed error signal indicating that the rotation speed of the motor 10 is high, and the compensation circuit
The rotation speed of the motor 10 is reduced by the action of 32 and the drive circuit 34.

The same control operation is repeated thereafter, and the oscillation frequency of the VCO 24 becomes a steady state, and when the rotational speed of the motor 10 decreases to a target value determined by this frequency and becomes stable, the speed error data output by the measuring instrument 28 becomes zero. And the motor 10
Is driven at a constant speed.

 As a result, the rotation speed of the motor 10 becomes 1/4.

The control band of LPF22 (loop filter) of digital PLL is frequency generator 12, FG amplifier / waveform shaping circuit 14, variable frequency divider circuit 15, measuring instrument 28, D / A converter 30, compensation circuit 3
2. Since the frequency is narrower than the control band of the motor control loop consisting of the drive circuit 34 and only in the low range, the frequency of the VCO24 output gradually changes until a new lock state is reached as described above. Data output and D / A
The change in the speed error signal output from converter 30 also becomes gradual.

Therefore, the motor control loop can reliably follow the speed error signal, the outputs of the compensation circuit 32 and the drive circuit 34 also change gently, and the rotation speed of the motor 10 decreases smoothly.
A smooth and stable speed change can be performed according to the change in the output frequency of O24, and the steady state is quickly achieved.

Separately from this, if the system control circuit 36A performs variable setting control of the variable frequency divider 15 in advance and sets n = 2, the output frequency of the reference frequency signal generator 18 is F _ref = 400H.
When z is set, the speed of the motor 10 is controlled from the equation (2) with ω = 1600π / k as the rotation speed target value.

At this time, the oscillation frequency of the VCO 24 is NF _ref = 1.024MHz.

When the reference frequency signal generator 18 is variably controlled in this state and the frequency is doubled to F _ref = 800Hz, the oscillation frequency of the VCO 24 gradually rises to 2.048MHz, and the target speed value of the motor 10 is ω = It is set to 3200π / k.

The motor control system follows the frequency change of the VCO 24 to increase the speed of the motor 10 and finally reach the target value in the same manner as described above.

The k value is set to, for example, about 300 puls / rev. So that the control band of the motor control system does not become low.

According to this embodiment, the VCO output frequency of the digital PLL can be varied by the variable setting control of the reference frequency signal oscillator 18 to perform the variable speed setting for the motor 10, the output side of the FG amplifier / waveform shaping circuit 14 and the measuring instrument. Since the variable frequency divider 15 is provided between 28 and the variable frequency divider 15 can be variably set and controlled, the frequency change of the reference frequency signal can be clearly understood from the equation (2). Since the speed variable setting of the motor 10 can be performed independently of the speed setting by, and since the k value of the frequency generator 12 does not have to be reduced, VC02
Even if it is necessary to set multiple types of speed over a wide range with one motor while keeping the oscillation frequency of 4 within the oscillation range, it is possible to reliably control in a wide control band. .

Further, by setting the control band of the LPF22 of the digital PLL lower than the control band of the motor control loop, when changing the speed of the motor 10 by changing the frequency of the reference frequency signal,
Since the frequency change of the VCO 24 is made gradual, the motor control loop can reliably follow the frequency change of the VCO 24, and the speed change of the motor 10 is stable and smooth even if the frequency of the reference frequency signal is suddenly changed. It is done and there is no overshoot. Therefore, the trouble of changing the frequency of the reference frequency signal stepwise is not required, and the steady rotation state is quickly achieved at the new speed after the change.

Next, another embodiment according to the present invention will be described with reference to FIG.

In the example of FIG. 1, the case where the speed control for the motor 10 is performed has been described, but in FIG. 3, the phase control is applied at the same time.

That is, in the motor control IC 16A, a second measuring instrument 37 is provided in addition to the measuring instrument 28 described above.

The output pulse signal of the frequency divider 26, VCO24
The clock signal from, and the divided rotation pulse from the variable frequency divider 15 are input.The phase difference between the rising edge of the output pulse of the frequency divider 26 and the rising edge of the divided rotation pulse is counted by the clock, and the phase error It is designed to be output as data.

A D / A converter 38 is connected to the output side of the measuring instrument 37, converts the phase error data input from the measuring instrument 37 into an analog quantity, and outputs it as a phase error signal from the output terminal OUT ′ to the compensation circuit 32A. .

The compensation circuit 32A obtains a compensation signal by adding to the error signal (speed error signal) input from the output terminal OUT and the phase error signal input from OUT ′ while performing appropriate gain compensation and phase compensation. The compensation signal is output to the drive circuit 34.

The other components are the same as in the case of FIG.

 Next, the operation of this embodiment will be described.

Now, for example, in the variable setting control of the system control circuit 36A, the reference frequency signal generator 18 and the variable frequency divider 15 respectively have F _ref =
When 400 and n = 1 are set, from formula (2), ω = 800
The speed of the motor 10 is controlled with π / k as the target rotational speed, and at the same time the rising timing of the pulse output from the frequency divider 26 (locked to the reference frequency signal in the steady state) is used as the target rotational frequency dividing pulse. Phase control is performed.

At this time, the oscillation frequency of the VCO 24 is NF _ref = 1.024MHz.

If, for some reason, the speed of the motor 10 rises slightly above the target value and the phase advances, the cycle of each output pulse of the frequency generator 12, the FG amplifier / waveform shaping circuit 14, and the variable frequency divider 15 decreases, and The phase of the divided rotation pulse advances. Measuring instrument
In 28, the count value of one cycle of the divided rotation pulse becomes less than 2560 in the same manner as described above, and the speed error data indicating the speed increase from the target value is output to the D / A converter 30.

The D / A converter 30 converts the speed error data sent from the measuring device 28 into an analog amount and outputs a speed error signal indicating a speed increase.

On the other hand, the measuring device 37 obtains a count value according to the phase difference between the frequency divider 26 output and the frequency-divided rotation pulse, and outputs the phase error data indicating the phase lead to the D / A converter 38.

The D / A converter 38 converts the data into an analog amount by the phase error sent from the measuring instrument 37, and outputs a phase error signal indicating the phase lead.

The speed error signal and the phase error signal are sent to the compensating circuit 32A, where the gain and the phase are respectively compensated and then added, and the summed signal is input to the drive circuit 34.

The drive circuit 34 lowers the output voltage to the motor 10 according to the input from the compensation circuit 32 to slow down the rotation speed of the motor 10 and delay the phase.

Conversely, if the speed of the motor 10 falls slightly below the target value and the phase is delayed, the frequency generator 12, FG amplifier / waveform shaping circuit 1
4, the cycle of each output pulse of the variable frequency divider 15 becomes large,
Moreover, the phase of the divided rotation pulse is delayed. In the measuring instrument 28, the count value of the cycle of the divided rotation pulse becomes more than 2560,
The speed error data indicating the speed decrease from the target value is output to the D / A converter 30.

The D / A converter 30 converts the speed error data sent from the measuring device 28 into an analog amount and outputs a speed error signal indicating a speed decrease.

On the other hand, the measuring device 37 obtains a count value according to the phase difference between the output of the frequency divider 26 and the divided rotation pulse, and outputs the phase error data indicating the phase delay to the D / A converter 38.

The D / A converter 38 converts the phase error data sent from the measuring instrument 37 into an analog amount, and outputs a phase error signal indicating a phase delay.

The speed error signal and the phase error signal are sent to the compensating circuit 32A, where the gain and the phase are respectively compensated and then added, and the summed signal is input to the drive circuit 34.

The drive circuit 34 raises the output voltage to the motor 10 according to the input from the compensation circuit 32 to increase the rotation speed of the motor 10 and advances the phase.

In this way, when the rotation speed and the phase of the motor 10 change, feedback is given to restore the original. By including the phase control, the feedback control is made more accurate and quick.

When the speed target value is changed by performing variable setting control of the reference frequency signal generator 18 from the state where the motor 10 is constantly rotating at a predetermined set speed, for example, when the speed is increased, the output of the frequency divider 26 is output. Since the phase of the divided rotation pulse is delayed relative to the pulse, the measuring instrument 36 outputs phase error data indicating the delay of the phase. Therefore, the D / A converter 30 outputs a phase error signal indicating a phase delay.

This phase error signal is sent to the compensation circuit 32 together with the speed error signal output from the D / A converter 30 to be signal-compensated, and then output to the drive circuit 34 to increase the speed of the motor 10.

While the speed of the motor 10 is lower than the target value, the above phase control and speed control are continued.

Then, when the speed of the motor 10 reaches a new target value, the speed error signal becomes zero, and when the phase difference between the output pulse of the frequency divider 26 and the divided rotation pulse becomes zero, the phase error signal also becomes zero. It becomes zero and the speed change is completed.

Here, since the control band of LPF22 is low and the oscillation frequency of VCO24 changes gently, it is possible to follow the VCO oscillation frequency change together with the speed control on the measuring instrument 28 side and the phase control on the measuring instrument 37 side, and also the speed error. Since the variable speed control is performed on the basis of both the phase error and the phase error, the speed of the motor 10 can be stably, quickly and smoothly changed to a new target value.

According to this embodiment, in the measuring instrument 37, the phase error between the output pulse of the frequency divider 26 and the divided rotation pulse is digitally obtained by using the clock of the VCO 24 output, and the analog error is obtained by the D / A converter 38. After being converted into a phase error signal, it is sent to the compensating circuit 32A together with the speed error signal on the D / A converter 30 side, and the gain and phase are respectively compensated and added.
Since it is output to the motor 10 including phase control
It becomes possible to control the speed with high accuracy, and when changing the speed, the target value can be reached stably, quickly and smoothly.

[Effect of device]

According to the motor control device of the present invention, the reference frequency signal generating means for generating the frequency variable reference frequency signal and the PLL loop filter are used, and the reference frequency signal is generated from the reference frequency signal generated by the reference frequency signal generating means. PLL means for obtaining a clock output of n times the frequency, speed detecting means for generating a pulse having a frequency proportional to the rotation speed of the motor, the cycle of the output pulse of the speed detecting means, and the clock output from the PLL means. Measured using, measuring means for obtaining the difference with a predetermined set value, and a control means for controlling the motor so that the difference obtained by this measuring means becomes zero, the control band of the PLL loop filter The upper limit of the reference frequency signal is set so that it does not exceed the upper limit of the control band of the motor control system including the motor, the speed detecting means, the measuring means, and the controlling means. When the speed of the motor is changed by the change, the VCO frequency change is made gradual, so the motor control loop can reliably follow the VCO frequency change and even if the frequency of the reference frequency signal is changed rapidly. The speed change of the motor is stable and smooth,
No overshoot occurs. Therefore, there is no need for the trouble of changing the frequency of the reference frequency signal step by step, and there is an excellent effect that the steady rotation state is quickly achieved at the new set speed after the change.

[Brief description of drawings]

FIG. 1 is a block diagram of a motor control device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing a comparison of control bands of an LPF and a motor control loop, and FIG. 3 is a block showing another embodiment. 4 and 5 are block diagrams showing a conventional motor control device. 10: Motor, 12: Frequency generator, 14: FG amplifier / wave shaping circuit, 15: Variable frequency divider, 16A: Motor control IC, 18: Reference frequency signal generator, 24: VCO, 28: Measuring instrument, 30 : D / A converter, 32: compensation circuit, 34: drive circuit.

Continuation of the front page (56) Reference JP 62-2874 (JP, A) JP 56-86084 (JP, A) JP 61-85086 (JP, A) JP 61-248264 (JP , A) JP 61-224167 (JP, A) JP 59-75453 (JP, A) JP 63-191351 (JP, A) JP 61-137277 (JP, A) JP 58-192479 (JP, A) JP-A-57-189587 (JP, A) JP-A-57-186994 (JP, A) JP-A-56-157291 (JP, A) JP-A-56-10087 (JP, A) A) JP-A-56-10086 (JP, A) JP-A-54-82010 (JP, A)

Claims (1)

[Scope of utility model registration request] 1. A reference frequency signal generating means for generating a variable frequency reference frequency signal and a PLL loop filter, wherein a frequency of n times the reference frequency signal is generated from the reference frequency signal generated by the reference frequency signal generating means. PLL means that obtains the clock output, speed detection means that generates a pulse of a frequency proportional to the rotation speed of the motor, and the output pulse period of the speed detection means is measured using the clock output from the PLL means And a control means for controlling the motor so that the difference obtained by this measurement means becomes zero, and the upper limit of the control band of the PLL loop filter is
A motor control device characterized by being set so as not to exceed an upper limit of a control band of a motor control system including a motor, a speed detecting means, a measuring means, and a controlling means.