JPH08106781A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] (Corrected) [Purpose] Adopting the shared sense method and bit line I /
The amplification operation of the read signal by the sense amplifier such as the dynamic RAM adopting the O system is accelerated, and the access time in the read mode is also accelerated. When the outer memory array is brought into a selected state, the internal control signal PA is set to a high level and the complementary bit line BO0 is read from the memory cell coupled to the selected word line WOs.
When the minute read signal Vsig output to * to BOn * is amplified by the sense amplifier, the internal control signal S
After HI and SHO are set to low level to disconnect the memory arrays on both sides from the sense amplifier, first, the internal control signal S
HI is returned to high level, the inner memory array is connected to the sense amplifier, the read signal is transmitted to the Y switch, then the internal control signal SHO is returned to high level, the outer memory array is connected to the sense amplifier, and the selected word is selected. The read signal is rewritten to the memory cell coupled to the line WOs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, for example, to a dynamic RAM (random access memory) adopting a shared sense system and a technique particularly effective when used for speeding up its access time. is there.

[0002]

2. Description of the Related Art A memory array including word lines and complementary bit lines arranged orthogonally and dynamic type memory cells arranged in a grid pattern at intersections of the word lines and complementary bit lines, and each complementary memory array. There is a dynamic RAM including a sense amplifier centered on a unit amplifier circuit which is provided corresponding to a bit line and is selectively operated in accordance with a predetermined internal control signal. Further, in such a dynamic RAM, there is a so-called shared sense system in which a sense amplifier is shared by a pair of memory arrays arranged on both sides thereof and selectively used. Further, in the dynamic type RAM adopting the shared sense method, the Y switch YS is arranged on the opposite side of the sense amplifier SA with the memory array ARYI interposed therebetween as shown in FIG. 11, and the bit line of the memory array ARYI is arranged. A so-called bit line I / that is used as a transmission path for transmitting the read signal of the memory cell coupled to the selected word line of the memory array ARYO to the Y switch YS.
There is an O method.

A dynamic RAM adopting the bit line I / O system is disclosed in, for example, Japanese Patent Laid-Open No. 57-100689.
No., published in Japanese Unexamined Patent Publication No.

[0004]

By the way, each of the unit amplifier circuits constituting the sense amplifier of the dynamic RAM has a pair of cross-coupled CMOS (complementary MO).
S) MOSFETs (metal oxide semiconductor type field effect transistors, which are MOSFETs collectively referred to as insulated gate type field effect transistors) that include these CMOS inverters, including inverters, are used in the manufacturing process and use. The threshold voltage varies depending on the environment. As a result, the operation characteristics of the unit amplifier circuits forming the sense amplifier are biased, and the operation margin of the dynamic RAM is compressed. In order to deal with this, the inventors of the present application, prior to the present invention, preset the offset amounts of variations in the threshold voltage of the MOSFETs constituting the unit amplifier circuit to the corresponding non-inverted and inverted signal lines of the complementary bit lines to cancel them. A so-called threshold voltage compensating method was devised, and an application was filed in Japanese Patent Application No. 5-28599.

On the other hand, in the dynamic RAM of FIG. 11 which adopts the bit line I / O system, the internal control signal SHI is set to the high level to connect the inner memory array ARYI to the sense amplifier SA, and the internal control signal SHO. Is set to a high level to connect the outer memory array ARYO. As described above, the sense amplifier SA includes unit amplifier circuits provided corresponding to the complementary bit lines of the memory arrays ARYI and ARYO. In these unit amplifier circuits, the internal control signal PA is set to the high level. Is selectively activated. And the memory array ARY
A minute read signal output from the memory cell connected to the selected word line of I or ARYO to each complementary bit line is amplified to be a high level or low level binary read signal. The sense amplifier SA also includes a bit line precharge circuit provided between the non-inverting and inverting input / output nodes of each unit amplifying circuit, and these bit line precharging circuits set the internal control signal PC to a high level. By doing so, the non-inverting and inverting input / output nodes of the corresponding unit amplifier circuit are set to a predetermined precharge level.

When the outer memory array ARYO is selected and the read operation is performed, in the dynamic RAM, first, as shown in FIG. 12, the internal control signal PC for precharging the bit line is set to the low level. , The designated word line WOs of the memory array ARYO is brought to a high level selected state at a predetermined timing. Also,
The internal control signal PA for driving the sense amplifier is set to the high level at the time when the minute read signals of the memory cells coupled to the selected word line WOs come out to the corresponding complementary bit lines, and further the read signal is amplified by the sense amplifier SA. When the operation is completed, the bit line selection signal YSs corresponding to the designated column address is set to the high level. The internal control signal SHO for connecting the outer memory array ARYO to the sense amplifier SA is kept at the high level during the read operation. The internal control signal SHI for connecting the inner memory array ARYI is
The sense amplifier SA is once set to a low level at startup.
When the amplification operation of the read signal by each unit amplifier circuit is finished, it is returned to the high level, and the binary read signal determined at the non-inverting and inverting input / output nodes of each unit amplifier circuit corresponds to the memory array ARYI. Is transmitted to the Y switch YS via the complementary bit line. These read signals are selectively complemented by the bit line selection signal YSs at the high level, and the complementary common data lines CD * (here, for example, the non-inverted common data lines CDT and CDB are combined together are complemented common data line CD. It is expressed by adding * like *.
In addition, a non-inverted signal or the like that is selectively set to high level when it is enabled is represented by adding T to the end of the name, and an inverted signal that is selectively set to low level when it is enabled. Signals and the like are indicated by adding B to the end of their names. The same applies hereinafter) and is further amplified by a main amplifier (not shown). Needless to say, 2 fixed to the non-inverting and inverting input / output nodes of each unit amplifier circuit
The value read signal is directly returned to the memory cell connected to the selected word line WOs via each complementary bit line of the memory array ARYO, and rewritten (rewritten).

That is, in the conventional dynamic RAM adopting the bit line I / O system, the sense amplifier SA and the outer memory array ARYO are constantly connected while the dynamic RAM is in the selected state. Therefore, in each unit amplifier circuit of the sense amplifier SA, in addition to the distributed capacitance of the non-inverted and inverted input / output nodes, the memory array ARY to which the rewriting is performed is initially provided when the unit amplifier circuit is operated.
The distributed capacitance of each complementary bit line of O is coupled as a load,
When the bit line selection operation by the Y switch YS is started, the distributed capacitance of the common data line and the distributed capacitance of each complementary bit line of the memory array ARYI serving as a transmission path are further coupled as a load. As a result, the sense amplifier SA
The amplification operation of the read signal due to
This causes a problem that the transmission operation of the read signal via S is delayed and the access time of the dynamic RAM is delayed. This is a serious problem, especially when the dynamic RAM adopts the threshold voltage compensation method and the amount of read signals to the unit amplifier circuit of the sense amplifier is compressed.

An object of the present invention is to provide a dynamic RA which adopts a shared sense method and a bit line I / O method.
The purpose is to speed up the read signal amplification operation by the sense amplifier such as M, speed up the read signal transmission operation via the Y switch, and speed up the access time of the dynamic RAM or the like.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM adopting the shared sense method and the bit line I / O method, for example, when the outer memory array is in a selected state, a minute read signal of the memory cell coupled to the selected word line is amplified. In order to operate the sense amplifier, the memory arrays on both sides are separated from the sense amplifier at first, and then the inner memory array is connected to the sense amplifier to transmit the read signal to the Y switch, and then the outer memory array. The memory array is connected to the sense amplifier to rewrite the memory cell coupled to the selected word line.

[0011]

According to the above-mentioned means, the read signal amplifying operation by the sense amplifier and the read signal transmitting operation by the Y switch are influenced by the distributed capacitance of the complementary bit lines of the outer memory array to be rewritten. It can be done fast without. As a result, the read operation of the dynamic RAM or the like adopting the shared sense method, the bit line I / O method, and particularly the threshold voltage compensation method can be sped up, and the access time can be sped up.

[0012]

1 is a block diagram of an embodiment of a dynamic RAM to which the present invention is applied. Further, FIG. 2 shows a partial circuit diagram of an embodiment of the sense amplifier SA and related parts included in the dynamic RAM of FIG. Based on these figures, the outline of the configuration and operation of the dynamic RAM of this embodiment will be described first. The circuit elements of FIG. 2 and the circuit elements of each block of FIG. 1 are formed on a single semiconductor substrate such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique. Further, in FIG. 2, an MO having an arrow on its channel (back gate) part
The SFET is a P-channel type and is shown separately from an N-channel MOSFET without an arrow.

In FIG. 1, the dynamic RAM of this embodiment adopts a shared sense system, and a sense amplifier SA and a pair of memory arrays ARYI (first memory array) and AR arranged with the sense amplifier SA interposed therebetween.
YO (second memory array). Of these, the memory arrays ARYI and ARYO are arranged in parallel with the m + 1 word lines WI0 to WIm and WO0 to WOm arranged in parallel in the vertical direction of the drawing, as shown in FIG. N + 1 sets of complementary bit lines BI
0 * to BIn * and BO0 * to BOn *, respectively. An information storage capacitor Cs and an address selection MOSF are provided at the intersections of these word lines and complementary bit lines.
(M + 1) × (n + 1) dynamic memory cells made of ETQa are arranged in a grid pattern.

Address selection M of m + 1 memory cells arranged in the same column of the memory arrays ARYI and ARYO
The drains of the OSFETs Qa have complementary drain bit lines BI0 * to BIn * and BO0 * to BOn *, respectively.
Are alternately coupled to the non-inverted or inverted signal lines of the above with a predetermined regularity. The gates of the address selection MOSFETs Qa of n + 1 memory cells arranged in the same row have corresponding word lines WI0 to WIm and WO0.
~ Wom commonly coupled. The internal voltage HV is commonly supplied to the other electrodes of the information storage capacitors Cs of all the memory cells forming the memory arrays ARYI and ARYO. The internal voltage HV is set to a substantially intermediate potential between the power supply voltage VCC and the ground potential VSS. The power supply voltage VCC is set to a positive potential such as + 3V, although not particularly limited.

Word lines WI0 to WIm and WO0 to WOm forming the memory arrays ARYI and ARYO.
Corresponds to the corresponding X address decoder XD below
It is coupled to I and XDO and is alternatively selected.
To the X address decoders XDI and XDO, i-bit internal address signals X0 to Xi-1 excluding the most significant bit are commonly supplied from the X address buffer XB, and internal control signals XGI and XGO are respectively supplied from the timing generation circuit TG. To be done. The X address buffer XB is supplied with the X address signals AX0 to AXi via the address input terminals A0 to Ai, and the timing generation circuit TG is supplied.
The internal control signal XL is supplied from.

The X address buffer XB has an X address signal AX supplied via address input terminals A0 to Ai.
0 to AXi are fetched and held according to the internal control signal XL, and internal control signals X0 to Xi are formed based on these X address signals. Of these, the most significant bit internal address signal Xi is supplied to the timing generation circuit TG, and the other internal address signals X0 to Xi-1 are
As described above, it is commonly supplied to the X address decoders XDI and XDO. On the other hand, the X address decoders XDI and XDO are selectively activated by receiving the high level of the corresponding internal control signals XGI and XGO,
The internal address signals X0 to Xi-1 are decoded and the corresponding word line WI of the memory array ARYI or ARYO is decoded.
0 to WIm or WO0 to WOm are alternatively set to a high level selected state. Needless to say, the most significant bit internal address signal Xi is used for selectively designating the memory array ARYI or ARYO and related parts.

Next, the complementary bit lines BI0 * to BIn * forming the memory array ARYI are connected to the corresponding unit circuit of the sense amplifier SA on the right side thereof and to the Y switch YS on the left side thereof. In addition, complementary bit lines BO0 * to BO that form the memory array ARYO
The n * is coupled to the corresponding unit circuit of the sense amplifier SA on its left side. The sense amplifier SA is supplied with internal control signals PC, PA, CS and SHI and SHO from the timing generation circuit TG, and the Y switch YS is supplied with bit line selection signals YS0 to YSn of n + 1 bits from the Y address decoder YD. To be done. The Y address decoder YD is supplied with the internal address signals Y0 to Yi of i + 1 bits from the Y address buffer YB and the internal control signal YG from the timing generation circuit TG.
Further, the Y address buffer YB is supplied with the Y address signals AY0 to AYi via the address input terminals A0 to Ai, and the timing control circuit TG outputs the internal control signal YL.
Is supplied.

The Y address buffer YB is supplied with the Y address signal AY via the address input terminals A0 to Ai.
0 to AYi are fetched and held in accordance with the internal control signal YL, and internal address signals Y0 to Yi are formed based on these Y address signals to generate the Y address decoder Y.
Supply to D. Further, the Y address decoder YD is selectively activated by receiving the high level of the internal control signal YG, decodes the internal address signals Y0 to Yi supplied from the Y address buffer YB, and selects the corresponding bit line. The signals YS0 to YSn are alternatively set to the high level.

The sense amplifier SA is a memory array ARY.
2 includes n + 1 unit circuits provided corresponding to complementary bit lines BI0 * to BIn * and BO0 * to BOn * of I and ARYO, and each of these unit circuits is P, as illustrated in FIG. Channel MOSFET P2
And P3 and N-channel MOSFETs N2 and N
A unit amplifier circuit centered on 3 and 3 N channels M
And a bit line precharge circuit including OSFETs N8 to NA.

Of these, the sources of the MOSFETs P2 and P3 forming the unit amplifier circuit of each unit circuit are commonly coupled to the common source line SP, and the sources of the MOSFETs N2 and N3 are commonly coupled to the common source line SN. Below the common source line SN, an N-channel drive MOSFE receiving the internal control signal PA at its gate is formed.
It is coupled to the ground potential VSS via TN1 and, above it, has an inverter V for the internal control signal PA at its gate.
It is coupled to a prescribed internal voltage VP through an N-channel MOSFET NH which receives an inverted signal of 1, that is, an inverted internal control signal PAB. Above the common source line SP, the common source line SP is coupled to the power supply voltage VCC through the P-channel drive MOSFET P1 which receives the inverted internal control signal PAB at its gate. The internal voltage VP is MO
When the threshold voltage of the SFETs N2 and N3 is Vth, it is set to a predetermined value such that VP≈HV-Vth with respect to the internal voltage HV.

MOSFET P2 constituting a unit amplifier circuit
, N2 are commonly coupled drains, which are non-inverting input / output nodes BS0T to BSnT of each unit circuit,
The drains of the MOSFETs P3 and N3, which are commonly connected to each other, serve as their inverting input / output nodes BS0B to BSnB. The gate of the MOSFET P2 is coupled to the corresponding inverting input / output node BS0B to BSnB, and the MOSF
The gate of ETP3 has a corresponding non-inverting input / output node BS.
It is connected to 0T to BSnT.

In this embodiment, the sense amplifier SA
Adopts a threshold voltage compensation method and is provided between the gates of the MOSFETs N2 and N3 and the corresponding gates of the MOSFETs P2 and P3, that is, the inverting input / output nodes BS0B to BSnB and the non-inverting input / output nodes BS0T to BSnT, respectively. Channel MOSFETs N4 and N6, and N channel M provided between the gates of MOSFETs N2 and N3 and the common source line SN, respectively.
It includes a threshold voltage compensation circuit consisting of OSFETs N5 and N7. M which constitutes these threshold voltage compensation circuits
The internal control signal C is applied to the gates of the OSFETs N4 and N6.
S is commonly supplied, and its inverted signal is commonly supplied to the gates of the MOSFETs N5 and N7.

The MOSFETs N4 and N6 forming the threshold voltage compensation circuit of each unit circuit of the sense amplifier SA are
Upon receiving the high level of the internal control signal CS, it is selectively turned on, and the gates of the MOSFETs N2 and N3 are selectively connected to the corresponding inversion input / output nodes BS0B to BSnB and the non-inversion input / output nodes BS0T to BSnT. And At this time, the MOSFETs N2 and N3 are
A pair of cross-coupled CMOS inverters is configured together with the MOSFETs P2 and P3 and acts as a unit amplifier circuit. Then, the internal control signal PA is set to the high level and selectively becomes the operating state on condition that the power supply voltage VCC and the ground potential VSS are supplied through the common source lines SP and SN, and the selected word of the memory array ARYI or ARYO. The corresponding complementary bit lines BI0 * to BIn * or BO0 * from the n + 1 memory cells coupled to the line
Each of the minute read signals output via BOn * is amplified to be a high level or low level binary read signal.

On the other hand, the MOSFETs N5 and N7 forming the threshold voltage compensating circuit of each unit circuit are selectively turned on in response to the low level of the internal control signal CS, and MO
The gates of the SFETs N2 and N3 and the common source line SN are selectively connected. At this time, the internal control signal PA is set to the low level, and the common source line SN has M
The internal voltage VP is supplied via the OSFET NH. As a result, the MOSFETs N2 and N3 are diode-shaped because their gates and sources are short-circuited via the MOSFETs N5 and N7, and the non-inverting and inverting input / output of the complementary input / output nodes BS0 * to BSn * of each unit circuit are performed. The node is pushed up to a level such as internal voltage HV which is higher than internal voltage VP by its threshold voltage Vth.

As is well known, M which constitutes a unit amplifier circuit
The threshold voltage Vth of the OSFETs N2 and N3 varies depending on the manufacturing process, the usage environment, etc., and ΔVt
has a difference of h. This difference ΔVth is
When TN2 and N3 act as a unit amplifying circuit, the amplifying operation is unbalanced.
And N3 are in diode form, these MO
The gates of the MOSFETs N3 and N2 on the opposite side via the SFET, that is, the non-inverting input / output nodes BS0T to BSnT and the inverting input / output nodes BS0B to BSnB, are canceled because they are transmitted and preset, thereby operating in the read mode of the dynamic RAM. The margin will be expanded.

Each unit circuit of the sense amplifier SA further has complementary complementary input / output nodes BS0 * to BSn * and corresponding complementary bit lines BI0 * to BI of the memory array ARYI.
A pair of N-channel type switch MOSFETs NB and NC (first switch means) provided respectively between n * and n *, their complementary input / output nodes BS0 * to BSn *, and the corresponding complementary bit line BO0 * of the memory array ARYO.
To BOn * and another pair of N-channel type switch MOSFETs ND and NE (second
Switch means). Of these, switch MOS
The internal control signal SHI is commonly supplied to the gates of the FETs NB and NC, and the internal control signal SHO is commonly supplied to the gates of the switch MOSFETs ND and NE.

As a result, the switch MOS of each unit circuit is
The FETs NB and NC are selectively turned on in response to the high level of the internal control signal SHI, and the memory array AR
The complementary bit lines BI0 * to BIn * of YI and the corresponding complementary input / output nodes BS0 * to BSn * are selectively connected. Similarly, switch MOSFETs ND and N
E is selectively turned on in response to the high level of the internal control signal SHO, and the complementary input / output node BS corresponding to the complementary bit lines BO0 * to BOn * of the memory array ARYO.
A connection state is selectively established between 0 * and BSn *. As a result, the internal memory array ARYI is selectively connected to the sense amplifier SA when the internal control signal SHI is set to the high level, and the external memory array ARYO is set to the internal control signal SHO when the internal control signal SHO is set to the high level. Will be selectively connected.

On the other hand, a predetermined internal voltage VCC / 3 is commonly supplied to the commonly connected sources of MOSFETs N8 and N9 which form the bit line precharge circuit of each unit circuit. Further, the gates of the MOSFETs N8 to NA forming the bit line precharge circuit are commonly connected and the internal control signal PC is commonly supplied. The internal voltage VC
C / 3 is set to one third of the power supply voltage VCC.
As a result, the MOSFETs N8 to NA are selectively turned on in response to the high level of the internal control signal PC, and the complementary input / output node BS0 of each unit circuit of the sense amplifier SA.
The non-inverting and inverting input / output nodes of * to BSn * are precharged to the internal voltage VCC / 3.

The Y switch YS is a memory array ARYI.
Of n channel type n + 1 pairs of switch MOSFETs NF and NG provided between the complementary bit lines BI0 * to BIn * and the complementary common data line CD *. The gates of the switch MOSFETs NF and NG of each pair are commonly connected, and the corresponding bit line selection signals YS0 to YSn are supplied from the Y address decoder YD. This allows
The switch MOSFETs NF and NG forming the Y switch YS are selectively turned on when the corresponding bit line selection signals YS0 to YSn are set to the high level, and the complementary bit lines BI0 * to BI0 * to corresponding to the memory array ARYI.
BIn *, that is, the corresponding complementary input / output nodes BS0 * to BSn * of the sense amplifier SA and the complementary common data line CD *.
And are selectively connected. The dynamic RAM of this embodiment adopts a bit line I / O system,
Complementary bit lines BI0 * to BIn of the memory array ARYI
* Indicates the corresponding complementary bit line B of the memory array ARYO
It is used as a transmission path for connecting between O0 * to BOn * and the complementary common data line CD *.

The complementary common data line CD * is coupled to the output terminal of the write amplifier WA and is connected to the main amplifier M.
Coupled to the A input terminal. The input terminal of the write amplifier WA is coupled to the output terminal of the data input buffer IB, and the input terminal of the data input buffer IB is coupled to the data input terminal Din. On the other hand, the output terminal of main amplifier MA is coupled to the input terminal of data output buffer OB, and the output terminal of this data output buffer OB is coupled to data output terminal Dout. The internal control signal WP is supplied to the write amplifier WA from the timing generation circuit TG. Further, the internal control signal RP is supplied from the timing generation circuit TG to the main amplifier MA, and the data output buffer OB is supplied.
Is supplied with an internal control signal DOC.

The data input buffer IB fetches the write data input via the data input terminal Din and transmits it to the write amplifier WA when the dynamic RAM is selected in the write mode. At this time, the write amplifier WA is selectively activated by receiving the high level of the internal control signal WP, and the data input buffer IB
After the write data transmitted from the complementary write signal is converted into a predetermined complementary write signal, the complementary common data line CD * is switched to the Y switch Y.
Write to one selected memory cell of the memory array ARYI or ARYO via S.

On the other hand, the main amplifier MA is selectively operated by receiving the high level of the internal control signal RP when the dynamic RAM is selected in the read mode, and the memory array ARYI or ARYO is selected. 1
The read signal output from each memory cell via the Y switch YS and the complementary common data line CD * is further amplified and transmitted to the data output buffer OB. At this time,
The data output buffer OB is selectively operated in response to the high level of the internal control signal DOC, and outputs the read signal output from the main amplifier MA to the data output terminal Do.
It is output to the outside of the dynamic RAM via ut.

The timing generation circuit TG selectively forms the above various internal control signals based on a row address strobe signal RASB, a column address strobe signal CASB and a write enable signal WEB which are externally supplied as activation control signals. And dynamic RA
Supply to each part of M.

FIG. 3 shows a signal waveform diagram of one embodiment when the inner memory array ARYI is selected in the read mode of the dynamic RAM of FIG. 1, and FIG. 4 shows the outer memory array ARYO. A signal waveform diagram of one embodiment when is selected is shown. Also, in FIG.
A signal waveform diagram of one embodiment when the inner memory array ARYI is selected in the refresh mode of the dynamic RAM of FIG. 1 is shown, and FIG. 6 shows one embodiment when the outer memory array ARYO is selected. An example signal waveform diagram is shown. Further, FIG. 7 shows a signal waveform diagram of the second embodiment when the inner memory array ARYI is selected in the read mode of the dynamic RAM of FIG. 1, and FIG. 8 shows the outer memory array. The signal waveform diagram of the second embodiment when ARYO is selected is shown. Based on these figures, the details and characteristics of the operation of the dynamic RAM of this embodiment in the read mode and refresh mode will be described.

In FIG. 3, when the dynamic RAM is in the non-selected state, the internal control signals PC, CS and SHI and SHO are at the high level, and the internal control signal PA is at the low level. Therefore, the sense amplifier S
In each unit circuit of A, first, a MOS which receives the high level of the internal control signal PC and constitutes a bit line precharge circuit.
FETN8-NA are turned on, and internal control signal SH
Switch MOSFE in response to high level of I and SHO
TNB and NC and ND and NE are turned on all at once. Further, in response to the high level of the internal control signal CS, the MOSFETs N4 and N6 forming the threshold voltage compensation circuit are turned on, and the MOSFETs N5 and N7 are turned off. Further, the drive MOSFETs P1 and N1 are turned off in response to the low level of the internal control signal PA, and the MOSFET NH provided between the internal voltage VP and the common source line SN is turned on.

From these facts, the memory array ARYI
And complementary bit lines BI0 * to BIn forming ARYO
The non-inverting and inverting signal lines of * and BO0 * to BOn * are non-inverting and inverting inputs of corresponding complementary input / output nodes BS0 * to BSn * of the sense amplifier SA via corresponding switch MOSFETs NB and NC and ND and NE. M of the bit line precharge circuit connected to the output node
It is precharged to the internal voltage VCC / 3 via the OSFETs N8 to NA. MOSF is connected to the common source line SN.
The internal voltage VP is supplied via ETNH. Also, M
The OSFETs N2 and N3 have MOs to which their gates correspond.
The MOSFETs P2 and P3 are combined with the gate of the SFET P2 or P3 to form a unit amplifier circuit, but the driving MOSFET P1 is not turned into the operating state because it is turned off.

On the other hand, when the dynamic RAM is selected in the read mode and the inner memory array ARYI is selected, the internal control signals PC and SHO are first set at time T0.
Is set to the low level, and the internal control signal CS is set to the low level during the time T1 to T2. Further, the word line WIs designated at the time T3 is alternatively set to the high level,
At 5, the internal control signal PA is set to high level. further,
The internal control signal SHI is temporarily set to the low level during the time T4 to T6, and the bit line selection signal YSs designated at the time T7 is alternatively set to the high level. Internal control signal P
C is returned to the high level at time TB. Also, time T
At 9, the word line WIs and the internal control signal SHO are returned to the low level and the high level, respectively, and at the time TA, the bit line selection signal YSs and the internal control signal PA are returned to the low level.

In each unit circuit of the sense amplifier SA, first, the low level of the internal control signal PC is received to turn off the MOSFETs N8 to NA forming the bit line precharge circuit, and the complementary bit lines and complementary inputs by these MOSFETs N8 to NA are turned on. The output node precharge operation stops. Further, the switch MOSFETs ND and NE are turned off in response to the low level of the internal control signal SHO, and the complementary input / output nodes BS0 * to B of the sense amplifier SA.
Complementary bit line BO0 * of Sn * and memory array ARYO
The connection between ~ Bon * is broken. On the other hand, the threshold voltage compensation circuit of each unit circuit receives the low level of the internal control signal CS between times T1 and T2, and the MOSFET
N4 and N6 are turned off, and instead MOSFET
N5 and N7 are turned on. Therefore, the MOSFE
TN2 and N3 have corresponding MOSFETs N5 and N7
Via a diode form, and complementary input / output nodes BS0 * to BSn * of each unit circuit, that is, a memory array ARY.
The complementary bit lines BI0 * to BIn * of I are MOSFETs
Via N2 and N3, the voltage is pushed up to a potential higher than the internal voltage VP by the threshold voltage Vth, that is, the internal voltage HV.

It should be noted that the MOSFE which constitutes the unit amplifier circuit
The threshold voltages Vth of TN2 and N3 vary depending on the manufacturing process, use environment, etc. and have a difference of ΔVth. This difference ΔVth is the internal control signal CS.
Is set to the low level and the MOSFETs N2 and N3 are in the diode form, the non-inverting input / output nodes BS0T to BSnT and the inverting input / output nodes BS0B to BSnB to which the gates of the MOSFETs N3 and N2 on the opposite side are coupled via these MOSFETs are connected. It is transmitted, and thereby the potential difference corresponding to each node is preset.

Next, at time T3, the word line WIs is alternatively set to the high level, and the complementary bit lines BI0 * to BIn * of the memory array ARYI and the sense amplifier SA are formed.
Complementary input / output nodes BS0 * to BSn * of n + 1 connected to the selected word line WIs of the memory array ARYI.
A minute read signal Vsig according to the held data is output from each memory cell. Further, when the internal control signal SHI is set to the low level at time T4, the sense amplifier SHI
The connection between the complementary input / output nodes BS0 * to BSn * of A and the complementary bit lines BI0 * to BIn * of the memory array ARYI is cut off, but the minute read signal Vsig corresponds to the complementary input / output nodes BS0 * to BSn. Accumulated in the distributed capacity of * and remains. Further, at time T5, the internal control signal P
When A is set to the high level, the MOSFETs N5 and N7 forming the threshold voltage compensation circuit are turned off, and instead, the MOSFETs N4 and N6 are turned on again. Therefore, the MOSFETs N2 and N3 act as a unit amplifier circuit together with the MOSFETs P2 and P3 by connecting their gates to the gates of the corresponding MOSFETs P2 and P3, and the corresponding complementary input / output nodes BS0 * ...
The minute read signal Vsig remaining in BSn * is amplified to be a binary read signal.

By the way, when the MOSFETs N2 and N3 act as a unit amplifier circuit together with the corresponding MOSFETs P2 and P3, these MOSFETs N2 and N3
As described above, the amplification operation of No. 3 becomes unbalanced due to the difference ΔVth of the threshold voltages. However, in the dynamic RAM of this embodiment, when the internal control signal CS is at the low level and the MOSFETs N2 and N3 are in the diode form as described above, these MOSs are
Non-inverting input / output nodes BS0T to BSn to which the gates of the MOSFETs N3 and N2 on the opposite side are coupled via the FET
Since it is preset to T and the inverted input / output nodes BS0B to BSnB, the imbalance of the unit amplifier circuit due to the difference ΔVth of the threshold voltage is canceled out, and thereby the operation margin in the read mode of the dynamic RAM is expanded. Become. The difference in threshold voltage ΔV
The preset of th results in compressing the amount of read signal to the unit amplifier circuit when the minute read signal output from the selected memory cell has the opposite polarity, but in this embodiment, the unit of Since the memory arrays ARYI and ARYO are both disconnected from the sense amplifier SA at the beginning of the operation of the amplifier circuit, there is no problem.

On the other hand, when the internal control signal SHI is returned to the high level at time T6, the complementary input / output nodes BS0 * to BSn * of the sense amplifier SA are connected to the corresponding complementary bit lines BI0 * to BIn * of the memory array ARYI. And complementary input / output nodes BS0 * to BSn * of the sense amplifier SA.
The binary read signal determined in the memory array ARY
It is transmitted to the Y switch YS via the complementary bit lines BI0 * to BIn * of I. These binary read signals are rewritten (rewritten) to n + 1 connected to the selected word line WIs of the memory array ARYI, and the bit line selection signal YSs is alternatively set to the high level at time T7. As a result, it is selectively transmitted to the complementary common data line CD * and is transmitted to the main amplifier MA.

Next, when the outer memory array ARYO is selected in the read mode, the dynamic RA
In M, as shown in FIG. 4, the internal control signal SHI is first set to low level at time T0, and the internal control signal SHO is set to low level at time T4. Internal control signal SHI
Is returned to the high level at time T5, and the internal control signal SH
O is returned to the high level at time T8. The minute read signal Vsig output from the n + 1 memory cells coupled to the selected word line WOs of the memory array ARYO to the complementary bit lines BO0 * to BOn * is the internal control signal SH.
While the O is at the high level, it is transmitted to the corresponding complementary input / output nodes BS0 * to BSn * of the sense amplifier SA, and the internal control signal PA is set to the high level, so that the unit amplifier circuit corresponding to the sense amplifier SA is caused. Is amplified. In addition, complementary input / output nodes BS0 * to B of the sense amplifier SA
The binary read signal determined to Sn * is transmitted to the Y switch YS via the complementary bit lines BI0 * to BIn * of the inner memory array ARYI when the internal control signal SHI is returned to the high level, and the internal control is performed. When the signal SHO is returned to the high level, the n + 1 memory cells coupled to the selected word line WOs of the memory array ARYO are rewritten.

As described above, in the dynamic RAM of this embodiment, the memory array ARYI or ARYO is selected immediately before the internal control signal PA is set to the high level and the unit amplifier circuit of the sense amplifier SA is activated. Complementary bit lines BI0 * to BIn * or BO0 * to BOn * corresponding to minute read signals output from the n + 1 memory cells coupled to the word line WIs or WOs.
Is transmitted to the corresponding complementary input / output nodes BS0 * to BSn * of the sense amplifier SA via the internal control signal PA, and the internal control signal PA is set to the high level to initially activate the unit amplifier circuit of the sense amplifier SA. Internal control signal SHI
And SHO are both at low level, and the memory array A
Complementary bit lines BI0 * to form RYI and ARYO
BIn * and BO0 * to BOn * are sense amplifiers S
The corresponding complementary input / output nodes BS0 * to BSn * of A are disconnected. As a result, the amplification operation of the read signal by each unit amplifier circuit of the sense amplifier SA is performed by the complementary bit lines BI0 * to BI of the memory arrays ARYI and ARYO.
It is performed at high speed without being affected by the capacity distributed in n * and BO0 * to BOn *.

On the other hand, the dynamic RAM of this embodiment
Is a bit line I / O system, and the inner memory array A
The complementary bit lines BI0 * to BIn * of RYI are n + 1 coupled to the selected word line of the outer memory array ARYO.
It is used as a transmission path for transmitting the read signal of each memory cell to the Y switch YS. Internal control signal S
When HI is returned to the high level and the complementary bit lines BI0 * to BIn * of the memory array ARYI are used as the transmission path, the internal control signal SHO is set to the low level and the complementary bit lines BO0 * to BOn * of the memory array ARY are sensed. The corresponding complementary input / output node BS0 * of the amplifier SA
~ Disconnected from BSn *. And Y switch YS
The internal control signal SHO is returned to the high level at the end of the bit line selecting operation by, and the read signal is rewritten to the n + 1 memory cells coupled to the selected word line of the memory array ARYO. As a result, Y
The operation of transmitting the read signal by the switch YS is performed by complementary bit lines BO0 * to BOn of the outer memory array ARYO.
It is performed at high speed without being affected by the capacity distributed in *. As a result, the read operation of the dynamic RAM is speeded up, and the access time thereof is speeded up.

When the dynamic RAM selects the inner memory array ARYI and enters the refresh mode, the internal control signal SHO is always at the low level throughout the period in which the refresh mode is performed, as shown in FIG. , The internal control signal SHI includes a time T5 that includes a time T5 during which the internal control signal PA is at a high level.
A low level is temporarily set between 4 and T6. Complementary bit lines BI0 * to BI corresponding to n + 1 memory cells connected to the selected word line WIs of the memory array ARYI.
The minute read signal output at n * is time T3 to T4.
Between the corresponding complementary input / output nodes BS of the sense amplifier SA
0 * -BSn * is transmitted, and the internal control signal P is transmitted at time T5.
When A is set to the high level, it is amplified by the corresponding unit amplifier circuit of the sense amplifier SA and becomes a binary read signal. These binary read signals are supplied to the corresponding complementary bit lines BI0 * to BI0 * of the memory array ARYI when the internal control signal SHI is returned to the high level at time T6.
It is transmitted to BIn * and rewritten to the n + 1 memory cells coupled to the selected word line WIs.

Similarly, when the dynamic RAM selects the outer memory array ARYO to enter the refresh mode, the internal control signal SHI is always at the low level throughout the period in which the refresh mode is performed, as shown in FIG. The internal control signal SHO includes the time T5 that includes the time T5 during which the internal control signal PA is at the high level.
A low level is temporarily set between 4 and T6. Complementary bit lines BO0 * to BO corresponding to n + 1 memory cells coupled to the selected word line WOs of the memory array ARYO.
The minute read signal output at n * is time T3 to T4.
Between the corresponding complementary input / output nodes BS of the sense amplifier SA
0 * -BSn * is transmitted, and the internal control signal P is transmitted at time T5.
When A is set to the high level, it is amplified by the corresponding unit amplifier circuit of the sense amplifier SA and becomes a binary read signal. These binary read signals are supplied to the corresponding complementary bit lines BO0 * to BOn of the memory array ARYO when the internal control signal SHO is returned to the high level at time T6.
N + 1 transmitted to * and coupled to the selected word line WOs
It is rewritten to the memory cells.

That is, the dynamic RA of this embodiment
The refresh mode of M is performed by simply selecting only the designated memory array ARYI or ARYO without paying attention to the complicated timing control in the read mode, thereby refreshing the dynamic RAM. Dynamic RAM that simplifies and speeds up timing control in modes
The cycle time in the refresh mode can be shortened.

By the way, when the inner memory array ARYI is selected in the read mode, the read operation of the dynamic RAM is performed by transmitting the read signal by the Y switch YS and n + 1 number of word lines connected to the selected word line of the memory array ARYI. Even if the rewriting of the read signal to the memory cell is performed at the same time, there is no limitation. Therefore, as shown in FIG. 7, the internal control signal SHI may be always at the high level during the period. However, when the outer memory array ARYO is selected, as shown in FIG. 8, both internal control signals SHI and SHO are set to the low level at the beginning when the internal control signal PA is set to the high level, and the sense amplifier SA is set to the low level. Complementary input / output nodes BS0 * to BSn * to memory arrays ARYI and AR
YO complementary bit lines BI0 * to BIn * and BO0
It is necessary to separate * to BOn * to speed up the amplification operation of the unit amplifier circuit of the sense amplifier SA.

FIG. 9 shows a memory array connection diagram of a third embodiment of a dynamic RAM to which the present invention is applied. Further, FIG. 10 shows a signal waveform diagram of an embodiment when the left or right memory array is selected in the read mode of the dynamic RAM of FIG.

In FIG. 9, the dynamic RAM of this embodiment comprises a pair of memory arrays ARYL and ARYR arranged with a sense amplifier SA sandwiched between them, and an X address decoder XDL and an X address decoder XDL provided corresponding to these memory arrays. It includes XDR and a Y address decoder YD arranged outside the memory array ARYL.

In this embodiment, the sense amplifier SA
Includes n + 1 unit circuits provided corresponding to the complementary bit lines BL0 * to BLn * and BR0 * to BRn * of the memory arrays ARYL and ARYR, and each of these unit circuits is selected according to the internal control signal PA. Unit amplifier circuit that is normally operated, and internal control signal PC
According to the bit line precharge circuit which is selectively activated according to the memory array AR according to the bit line selection signals YS0 to YSn supplied from the Y address decoder YD.
And a Y switch for selectively connecting the designated complementary bit line of YL or ARYR and the complementary common data line CD *. Each unit circuit of the sense amplifier SA is connected to the memory array ARYL via a pair of switch MOSFETs that are selectively turned on in accordance with the internal control signal SHL.
Corresponding complementary bit lines BL0 * to BLn * are selectively connected to the corresponding complementary bit lines BR0 * of the memory array ARYR via another pair of switch MOSFETs that are selectively turned on according to the internal control signal SHR. ~
It is selectively connected to BRn *.

When the dynamic RAM is in the read mode and, for example, the left memory array ARYL is selected, the internal control signal SHR corresponding to the right memory array ARYR is set to low level together with the internal control signal PC for precharge control. It In addition, the internal control signal SHL
Is set to the low level when a predetermined time has elapsed after the specified word line WLs is set to the high level, the internal control signal PA is set to the high level, and the specified bit line selection signal YSs is set to the high level. The level is returned to the high level when a predetermined time elapses.

That is, the dynamic RA of this embodiment
M is a normal dynamic RAM that does not adopt the bit line I / O system, but at the beginning when the unit amplifier circuit of the sense amplifier SA is activated by receiving the high level of the internal control signal PA, the memory array The complementary bit lines BL0 * to BLn * of ARYL are separated from the complementary input / output nodes BS0 * to BSn * of the sense amplifier SA, the read signal amplification operation by the sense amplifier SA is accelerated, and the bit line selection signal YSs is transmitted. Even when the bit line selecting operation is performed by the sense amplifier SA after being set to the high level, the complementary bit line BL0 of the memory array ARYL
* To BLn * are complementary input / output nodes B of the sense amplifier SA
It is separated from S0 * to BSn *, which speeds up the read signal transmission operation by the sense amplifier SA, that is, the Y switch.

The operational effects obtained from the above embodiments are as follows. That is, (1) in a dynamic RAM adopting the shared sense method and the bit line I / O method, for example, when the outer memory array is in the selected state, minute reading of the memory cells coupled to the selected word line is performed. Initially, when the sense amplifier is activated to amplify the signal, the memory arrays on both sides are separated from the sense amplifier, then the inner memory array is first connected to the sense amplifier and the read signal is transmitted to the Y switch. By rewriting the memory cells connected to the selected word line by connecting the outer memory array to the sense amplifier, the read signal amplification operation by the sense amplifier and the read signal transmission operation by the Y switch are rewritten. Is performed at high speed without being affected by the distributed capacitance of the complementary bit lines of the outer memory array. The effect that can be obtained is obtained. (2) According to the above item (1), it is possible to speed up the read operation of a dynamic RAM or the like which adopts the shared sense method, the bit line I / O method, and particularly the threshold voltage compensation method. Is obtained. (3) According to the above items (1) and (2), it is possible to obtain the effect that the access time in the read mode of the dynamic RAM can be shortened.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the sense amplifier SA and the memory array A
RYI and ARYO and their peripheral circuits can be divided into a plurality of mats. Also, dynamic type R
The AM may have a so-called multi-bit configuration in which a plurality of bits of storage data are simultaneously input / output, and the data input terminal Di
n and the data output terminal Dout may be shared as a data input / output terminal. Furthermore, the block configuration of the dynamic RAM, the combination of the activation control signal and the address signal, and the like can adopt various embodiments.

In FIG. 2, the sense amplifier SA does not have to adopt the threshold voltage compensation method as an essential condition. Further, the memory arrays ARYI and ARYO can include a predetermined number of redundant elements, and can adopt a so-called word shunt method. Drive MOSFETs P1 and N
Each of the 1 can be replaced with a plurality of P-channel MOSFETs or N-channel MOSFETs that are in parallel form and are sequentially turned on after a predetermined time. Furthermore, the sense amplifier SA and the memory array A
The specific configuration of RYI and ARYO, the polarity and absolute value of the power supply voltage, the conductivity type of the MOSFET and the like are not limited by this embodiment.

In FIGS. 3 to 8 and FIG. 10, the time relationship of each internal control signal, the logic level when valid, and the like are merely examples, and various embodiments thereof can be considered. In FIG. 9, the sense amplifier SA and the memory array A
RYL and ARYR and their peripheral circuits can be divided into a plurality of mats.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM which is the field of application which is the background of the invention has been described.
The present invention is not limited to this, and is also applied to various memory integrated circuits such as a multiport memory and a synchronous memory having a dynamic RAM as a basic configuration, and a gate array integrated circuit device equipped with such a memory integrated circuit. it can. INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a semiconductor memory device adopting the shared sense method and devices and systems including such a semiconductor memory device.

[0060]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM adopting the shared sense method and the bit line I / O method, for example, when the outer memory array is in a selected state, a minute read signal of the memory cell coupled to the selected word line is amplified. In order to operate the sense amplifier, the memory arrays on both sides are separated from the sense amplifier at first, and then the inner memory array is connected to the sense amplifier to transmit the read signal to the Y switch, and then the outer memory array. By connecting the memory array to the sense amplifier and rewriting the memory cells coupled to the selected word line, the read signal amplifying operation by the sense amplifier and the read signal transmitting operation by the Y switch are rewritten. It can be performed at high speed without being affected by the distributed capacitance of the complementary bit lines of the outer memory array. That. As a result, the read operation of the dynamic RAM or the like adopting the shared sense method, the bit line I / O method, and particularly the threshold voltage compensation method can be sped up, and the access time can be sped up.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a partial circuit diagram showing an embodiment of a sense amplifier and related parts included in the dynamic RAM of FIG.

FIG. 3 is a signal waveform diagram showing an embodiment when an inner memory array is selected in a read mode of the dynamic RAM of FIG.

4 is a signal waveform diagram showing an embodiment when an outer memory array is selected in a read mode of the dynamic RAM of FIG.

5 is a signal waveform diagram showing an embodiment when the inner memory array is selected in the refresh mode of the dynamic RAM of FIG.

FIG. 6 is a signal waveform diagram showing an embodiment when the outer memory array is selected in the refresh mode of the dynamic RAM of FIG.

FIG. 7 is a signal waveform diagram showing a second embodiment when the inner memory array is selected in the read mode of the dynamic RAM of FIG.

8 is a signal waveform diagram showing a second embodiment when the outer memory array is selected in the read mode of the dynamic RAM of FIG.

FIG. 9 is a memory array connection diagram showing a third embodiment of a dynamic RAM to which the present invention is applied.

FIG. 10 is a signal waveform diagram showing an embodiment when the left or right memory array is selected in the read mode of the dynamic RAM of FIG.

FIG. 11 is a memory array connection diagram showing an example of a conventional dynamic RAM.

FIG. 12 is a signal waveform diagram showing an example when the outer memory array is selected in the read mode of the dynamic RAM of FIG.

[Explanation of reference symbols] ARYI, ARYO ... Memory array, XDI, XD
O ... X address decoder, XB ... X address buffer, SA ... sense amplifier, YS ... Y switch, YD ... Y address decoder, YB ... Y address buffer, WA ... Write amplifier, MA ... Main amplifier, IB ... Data input buffer, OB ...
-Data output buffer, TG ... Timing generation circuit. WI0 to WIm, WO0 to WOm ... word lines,
BI0 * to BIn *, BO0 * to BOn * ... Complementary bit lines, BS0 * to BSn * ... Complementary input / output node of sense amplifier, Cs ... Information storage capacitor, Qa ...
Address selection MOSFET, SP, SN ... Common source line, YS0 to YSn ... Bit line selection signal, C
D * ... Complementary common data line. PC: internal control signal for precharge, CS: internal control signal for threshold voltage compensation preset, PA: internal control signal for driving sense amplifier, SHI, SHO ... internal control signal for shared sense . ARYL, ARYR ... Memory array, X
DL, XDR ... X address decoder, WL0 to WL
m, WR0 to WRm ... Word line, SHL, SHR
..Internal control signals for shared sense P1-P3 ...
P-channel MOSFET, N1-NH ... N-channel MOSFET, V1-V2 ... Inverter.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hiroshi Otori 2326 Imai, Ome City, Tokyo, Hitachi Device Development Center (72) Masayuki Nakamura 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Nobutaka Ito 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Tsuyuki Suzuki 5-20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo SII Engineering Co., Ltd. (72) Inventor Kazuhiko Kajiya 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center

Claims (3)

[Claims] 1. A sense amplifier selectively activated according to a predetermined internal control signal, and a first or second switch means arranged on both sides of the sense amplifier to be selectively turned on. Y for selectively transmitting the read signal of the first and second memory arrays connected to the sense amplifier and the memory cells coupled to the selected word line of the first or second memory array to the common data line. A switch, and the first and second switch means are turned off at the beginning of the operation of the sense amplifier and are coupled to the selected word line of the first or second memory array. A semiconductor memory device, wherein a read signal is transmitted to the common data line before rewriting of a memory cell. 2. The Y switch is arranged on the opposite side of the sense amplifier with the first memory array sandwiched therebetween, and each of the bit lines forming the first memory array has the above-mentioned structure. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is used as a transmission path for transmitting a read signal of a memory cell coupled to a selected word line of the second memory array to the Y switch. 3. The sense amplifier includes a threshold voltage compensating circuit for compensating for variations in threshold voltage of MOSFETs constituting a unit amplifying circuit. Semiconductor memory device.