JPH08105940A - Diagnostic device, diagnosed device, and electronic device including these - Google Patents

Abstract

PURPOSE: To reduce the number of signal lines necessary for diagnosis by transmitting/receiving data in a serial packet form without using a scan clock. CONSTITUTION: Devices 200, 300 to be diagnosed receive data of a serial packet form supplied from a diagnostic device 100, and it writes the received data in FFs composing a scan pass provided in the device. The diagnostic device 100 transmits the data of the serial packet form, and receives data of the serial packet form for held data in each of the FFs composing the scan pass transmitted from the devices 200, 300. Diagnosis of each device to be diagnosed is performed based on the received data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device, and more particularly to an electronic device including a diagnostic device and a device to be diagnosed.

[0002]

2. Description of the Related Art As one of diagnostic methods for a system composed of digital electronic devices, there is a method using a scan path. For example, as disclosed in Japanese Unexamined Patent Publication No. 62-182938, a scan path is used for diagnosing a failure of a digital electronic device and collecting detailed information of a failure such as a failure.

A technique for previously providing a scan path inside an integrated circuit is disclosed in Japanese Patent Laid-Open No. 3-249574.
JP-A-4-50783, JP-A-4-181185
It is disclosed in the gazette and the like.

FIG. 9 is a block diagram showing a configuration example of a conventional electronic device. The electronic device includes a diagnostic device 700 that collects detailed data of fault information when a diagnostic process of the diagnostic devices 800 and 900 and a fault occurs, and a diagnostic device 700 that includes a plurality of LSIs and operates as a functional circuit in the system during normal operation. It is composed of diagnostic devices 800 and 900.

The diagnostic device 700 sets the processor 710 for controlling the decoder 720 and the selector 730 to diagnose the diagnostic device 800 or 900 and the diagnostic device 800 or 900 designated by the processor 710 in the shift mode. Decoder 720 and device under test 800
Alternatively, it is configured to include a selector 730 for selecting scan-out data from 900, and an FF number table 740 including a memory for storing the number of flip-flops in each diagnostic path.

The devices to be diagnosed 800 and 900 have the same internal structure. In the following description, the device under diagnosis 800 will be mainly described.

The device under diagnosis 800 includes LSIs 810 and 8
It is configured to include 20. When these LSIs 810 and 820 receive one scan clock 12 (one pulse) sent to the scan clock terminal SCLOCK while the scan mode signal 10 sent to the scan mode terminal SM is “1”, the LSI receives the scan-in terminal SI. Take in the scan-in data 11 sent. At the same time, both LSIs send out the scan-out data 13 from the scan-out data terminal SO. This state is called a scan mode. Note that the above configuration is the same for the device under diagnosis 900.

A case will be described below in which the diagnostic device 700 collects scan data of the device to be diagnosed 800 in such a configuration.

First, the processor 710 is the device under diagnosis 80.
The scan bit number of 0 is read from the FF number table 740 to prepare for the scan operation. Next, the scan mode signal 10 is set to "1", and the LSIs 810 and 820 connected to the scan path are set to the scan mode.

Then, the scan-in data 11 is set and the scan clocks 12 are input by the number of FFs. Each time the LSIs 810 and 820 connected to the scan path receive one scan clock 12, the LSI holds the information held in a flip-flop (not shown) inside the LSI itself as scan-out data 13. The processor 710 receives the scan-out data 13 via the selector 730.

Next, each control signal line will be described with reference to the time chart of FIG.

First, when the scan mode signal 10 rises, the LSIs 810 and 820 are set to the scan mode and the content of the scan-out data 13 changes to OUTDT.
It is determined as (00) to OUTDT (n). At the same time, the processor 710 scan-in data 11
Is determined as INDT (00) to INDT (n). In this state, the scan clock 12 is output to shift the data bit by bit.

Here, each clock width W of the scan clock 12 must be set to a value that satisfies all wiring delays of flip-flops (hereinafter abbreviated as FF) connected to the scan path. That is, if the clock width W is too short, the clock skew may increase and malfunction may occur when the distance between the devices is large, and the clock width W needs to be sufficiently large.

[0014]

In the above-mentioned conventional diagnostic apparatus and the like, all the FFs constituting the scan path are set to 1
Since the shift operation is performed by one scan clock, there is a drawback that the clock width W needs to be set to a value that satisfies all the wiring delay times between the FFs connected to the scan path.

Further, since it is necessary to send the scan clocks for all the bits of all the FFs forming the scan path from the diagnostic device, there is a drawback that one scan operation takes time. In particular, in the electronic device that is separated from the diagnostic device and the device to be diagnosed, the wiring becomes long, and therefore the delay amount is several times as large as the delay amount between the adjacent devices. Has the drawback that it takes a lot of time.

Furthermore, all F's forming the scan path
It is necessary to set F to the scan mode, which has the drawback of requiring many signal lines.

Each of these drawbacks also occurs in the scan paths disclosed in the above publications.
The technology disclosed in these publications cannot solve the problem.

The present invention has been made in order to solve the above-mentioned drawbacks of the prior art, and its purpose is to perform a scanning operation in a short time and a small number of signal lines, and a diagnostic device and a device to be diagnosed. It is to provide an electronic device including.

[0019]

A diagnostic device according to the present invention is a diagnostic device for writing data to each flip-flop constituting a scan path provided in a device to be diagnosed, the data being a serial packet. Data transmission means for transmitting in a format, and reception means for receiving serial packet format data of the data held by each flip-flop that constitutes the scan path transmitted from the device to be diagnosed, and based on this received data The diagnosis of the device to be diagnosed is performed.

The device to be diagnosed according to the present invention receives the serial packet format data sent from the diagnostic device to the receiving means, and the received data to the respective flip-flops constituting the scan path provided in the device itself. And a means for writing.

The electronic device according to the present invention comprises a device to be diagnosed,
An electronic device including a diagnostic device that writes data to each flip-flop that configures a scan path provided in the diagnostic device, wherein the diagnostic device is a serial packet sent from the diagnostic device. The diagnostic device includes a first receiving device for receiving data of a format and a writing device for writing the received data received into each flip-flop forming a scan path provided in the device itself. Data transmitting means for transmitting the data in the serial packet format, and second receiving means for receiving data in the serial packet format for the data held by the flip-flops constituting the scan path transmitted from the device to be diagnosed. And diagnosing the device to be diagnosed based on the data received by the second receiving means.

[0022]

The device to be diagnosed receives the data of the serial packet format sent from the device to be diagnosed, and writes the received data to each flip-flop forming the scan path provided in the device itself. The diagnostic device sends serial packet format data, and also receives serial packet format data about the data held by the flip-flops forming the scan path, which is sent from the device to be diagnosed. Based on the received data, the device under diagnosis is diagnosed.

[0023]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of a diagnostic device, a device to be diagnosed, and an electronic device including them according to the present invention.

In the figure, the electronic device of this embodiment is constructed to include devices to be diagnosed 200 and 300, and a diagnostic device 100 for performing these diagnoses.

The diagnostic device 100 includes devices to be diagnosed 200 and 3 to be diagnosed.
00 diagnostic processing and detailed data of failure information when a failure occurs.

The diagnostic device 100 responds to an instruction from the diagnostic control processor 120 to scan data in the serial packet format shown in FIG.
Serial communication transmission unit 11 for transmitting to 00 and 300
F, which stores 0 and the number of scan data peculiar to the device to be diagnosed, and gives the number of FFs for each diagnostic pass at the time of system initialization.
The F number table 130 and the serial communication receiving unit 140 that receives the communication in the serial packet format from the device to be diagnosed 200 are configured. The serial communication receiving unit 140 is configured to include an error detection circuit 141 that checks whether communication has been normally sent, and an error detection flag 142 that is set when an error is detected.

Further, the diagnostic device 100 has a selector 150 for selecting a path for fetching the serial communication packet returned from the device to be diagnosed into the processor, and a serial communication transmitting unit to the device to be diagnosed designated by the diagnostic control processor 120. Decoder 160 for transmitting serial communication from 110, serial communication transmitting unit 110, and decoder 16
0, selector 150, serial communication receiver 140, FF
The number table 130 is controlled to diagnose the devices 200, 300.
And a diagnostic control processor 120 for controlling the diagnostics.

The devices to be diagnosed 200 and 300 are digital electronic devices, each of which includes a plurality of LSIs. Then, these diagnosed devices operate as functional circuits in the system during normal operation.

The LSIs 210 and 220 are both LSIs to be diagnosed, and the diagnostic device 10 is connected to the scan-in terminal SI.
When the serial communication packet from 0 is received, the received serial communication packet is taken in, and at the same time, the scan data in the own LSI is returned to the diagnostic device 100 in the serial communication packet format shown in FIG.

Here, focusing on the LSI 210, the LS
The I210 includes a serial communication receiving unit 211, a serial communication transmitting unit 212, and an LSI internal information FF213.

The serial communication receiving section 211 is used for the diagnostic device 1.
00 is a circuit for receiving the serial communication packet from 00 and writing the received data in the LSI internal information FF 213, and an error detection circuit 214 for detecting whether or not the serial communication packet has been normally received, and a failure for normal reception. The error detection flag 215, which is set in some cases, is included.

The serial communication transmission unit 212 is a circuit that returns the data in the LSI internal information FF 213 to the diagnostic device 100 in the form of a serial communication packet.
When the serial communication packet from 00 cannot be received normally, that is, when the error detection flag 215 is "1", the end bit of the reply serial communication packet is "0".
Has a function of notifying that it could not be received normally.

The LSI internal information FF 213 is a group of FFs inside the LSI and is assumed to be connected by a scan path.

Next, the operation of each section will be described. In this example, the diagnostic device 100 is the LSI 21 of the device under diagnosis 200.
A case where 64-bit scan data of 0 is collected will be described.

First, the diagnostic processor 120 is the LSI 21.
The number of scan data of 0 is read from the FF number table 130, and it is recognized that it is 64 bits. Then, the diagnostic processor 120 gives the data to be scanned in and the scan bit number 64 to the serial communication transmission unit 110, and instructs the serial communication transmission unit 110 to start the operation. The serial communication transmission unit 110 generates a serial communication packet from the scan-in data and the scan bit number given from the diagnostic control processor 120 and sends it to the decoder 160. The decoder 160 sends the serial communication packet sent from the serial communication sending unit 110 over the path 1 to the LSI 210 instructed by the diagnostic control processor 120.

Serial communication receiving section 211 of LSI 210
Receives the start bit of the serial communication packet 1 at the scan-in terminal SI, extracts 64 bits of scan data following the start bit and writes the extracted data into the LSI internal information FF 213. At the same time, the serial communication receiving unit 211 instructs the serial communication transmitting unit 212 to return the serial communication packet. Further, the serial communication receiving unit 211 checks the serial communication packet from the diagnostic device 100 by the error detection circuit 214, and sets the error detection flag 215 when the serial communication packet is not normally received.

When the serial communication transmitting section 212 receives an instruction to return a serial communication packet, the LSI internal information F
The scan-out data of 64 bits of the own LSI is read from F213 and returned to the diagnostic device 100 in the form of a serial communication packet through the path 2. At this time, when the serial communication packet from the diagnostic device is normally received, the end bit is set to "1" and returned. However, when it cannot be received normally, that is, the error detection flag 21
When 5 is set, the end bit is set to "0" and a reply is sent.

When the diagnostic device 100 receives the reply serial communication packet 2 from the LSI 210 via the selector 150 at the serial communication receiving unit 140, the scan data 64 is received.
Extract bits. When it is confirmed that the end bit is "1", the error detection flag 142 is set to "0" and the received data is delivered to the diagnostic control processor 110. However, when it is confirmed that the end bit is “0”, the error detection flag 142 is set to “1”,
The received data is delivered to the diagnostic control processor 110. Also, when the serial communication packet 2 returned from the LSI 210 cannot be received normally, the error detection flag 1
42 is set to "1".

The diagnostic control processor 120, which has received the received data, judges the error detection flag 142 delivered from the serial communication receiving unit 140, and if reception fails, re-executes or performs failure processing.

With the operation described above, 64-bit scan data of the LSI 210 can be collected.
The same applies to other paths, and the scan bit number can be set to an arbitrary bit number by storing it in the FF number table 140 in advance.

Next, the format of the serial communication packet will be described with reference to FIG. The serial communication packet in this example includes start bits, scan data, and end bits.

The start bit is a bit for sending "0" for 1T (cycle) to notify the start of data.

The scan data is data whose contents are switched by 1 bit per 1T. Although the length of the data can be changed, it is necessary to make an agreement between the diagnostic device 100 and the device to be diagnosed in advance, and the data can be recorded in the FF number table 130. In this example, 64 of bits 0 to 63
Let T be the length. When all the diagnostic paths have the same number of bits and have a fixed length, the FF number table 140 of FIG. 1 is not necessary.

The end bit is set to "1" when the received scan data can be normally received, and is set to "0" when there is an error to inform whether the serial communication packet has been normally received. Is a bit for.

It should be noted that during the period when serial communication is not performed, that is, during the no-operation (NOP) period, the signal is at "1" level.

Next, the serial communication transmission units 110 and 21
A second hardware configuration example will be described.

The serial communication transmitters 110 and 212 are
Since it can be realized with almost the same circuit configuration, the configuration of the serial communication transmission unit 110 on the diagnostic device 100 side will be mainly described here.

FIG. 3 is a block diagram showing a configuration example of the serial communication transmission unit 110. The configuration of FIG. 3 has 320 [ns] for 1T of the serial communication packet described in FIG.
And the system clock of the diagnostic device 100 is 40 [n
s]. In the figure, a transmission data storage buffer 401 is composed of a group of FFs connected in a multi-stage shift, and shift advance (Shift Adva).
nce) is a buffer which outputs the transmission data 4010 input bit by bit in response to the input of the signal SFTADV.

The in-operation flag 402 is an operation start signal 402.
This flag is set by 0, and the transmission operation is started by setting this flag.

The time counter 403 has 1 bit 320.
This is a 3-bit counter for guaranteeing [ns], and is incremented by 1 when "1" of the operating flag 402 is input to the strobe terminal STB, and returns to "0" when counting up to "7" and counts up. To continue.

The data number counter 404 is sequentially incremented by 1 when a signal resulting from the logical product of the time counter value "7" and the operating flag 402 is input to the strobe terminal STB.
A bit counter for counting the number of data bits of a serial communication packet.

In-operation flag 402, time counter 403
The data counter 404 is reset by the output signal of the AND gate 423.

The data number storage register 405 is provided with the scan bit number 40 given by the diagnostic control processor 120.
This is a register for storing 50.

The selector 407 is a selector for selecting the start bit, data bit, and end bit of the serial communication packet.

The serial communication transmission FF 406 is an FF for transmitting the signal selected by the selector 407 to the serial communication path.

The selector 408 is a selector for selecting an end bit. In the case of the serial communication transmitting unit 110, the fixed value “1” is selected, and the serial communication transmitting unit 212 is selected.
In the case of, the output 4080 from the error detection flag of the serial communication transmission unit 211 is selected. That is, the communication transmitter 1
Control signal 4 according to 10 or serial communication transmission unit 212
The level of 081 will be decided, and once decided, it will be fixed.

The plus 1 circuits 409 to 411 are circuits that output a value obtained by adding 1 to the input data.

The plus 2 circuit 412 is a circuit for outputting a value obtained by adding 2 to the input data.

The comparators 413 to 417 are circuits which output "1" when the two inputs match. One of the inputs of the comparator 413 is always given "000", and the comparator 41
"111" is always given to one of the four inputs.
One of the inputs of the comparator 415 is fixed to "0".

AND gates 418 to 423 are circuits that output the logical product of the respective inputs.

The inverters 424 to 427 are circuits which output inverted signals of their respective inputs.

Serial communication transmission unit 1 having the above configuration
The operation of 10 will be described with reference to the drawings. FIG. 4 is a time chart showing the operation of each part of FIG. 3, in-operation flag 402, time counter 403, data number counter 4
04, the shift advance signal SFTADV, and the output signal of the serial communication transmission FF.

First, the scan-in data is given from the diagnostic control processor 120 to the transmission data storage buffer 401, and the number of scan bits is set to the data number storage register 4.
05, which is given as a start instruction to the operating flag 40.
2 is set. Then, the time counter 403 starts counting up. At the same time, since the value of the data number counter 404 is "0", the selector 407 selects "0" of the start bit to output the serial communication transmission FF.
Set to 406.

When the time counter 403 continues to count up and its value becomes "7", the data number counter 404
Is incremented by 1. When the value of the time counter 403 becomes “0”, the selector 407 causes the transmission data storage buffer 40
The scan-in data of 1 is selected and output, and the serial communication transmission FF 406 is set.

The output of scan-in data is performed until the value of the data number counter 404 reaches the value of the data number storage register 405, that is, until the sending of scan data is completed. Then, when the value of the data number counter 404 becomes the value of +1 of the data number storage register 405, the selector 407 selects the end bit and outputs the serial communication transmission FF.
Set to 406. Further, the data number counter 404
When the value of is the value of +2 of the data number storage register 405, the in-operation flag 402 and the data number counter 404 are reset and the operation ends.

Next, the serial communication receiving units 140 and 21
A hardware configuration example of No. 1 will be described.

The serial communication receivers 140 and 211 are
Since it can be realized with almost the same circuit configuration, the operation of the serial communication receiving unit 140 on the diagnostic device 100 side will be mainly described here.

FIG. 5 is a block diagram showing a configuration example of the serial communication receiving section 140. The configuration of FIG. 5 is designed such that 1T of serial communication described in FIG. 2 is 320 [ns] and the system clock of the device is 40 [ns]. That is, the cycle of the system clock of the device is shorter than the cycle of the data clock of the serial communication packet. The same applies to the serial communication receiving unit and the serial communication transmitting unit 211 in the device to be diagnosed.

In FIG. 5, the scan-in register (S
IR) 501 is a signal 5010 of a serial communication packet.
Of the system clock, which is 40 [n
It is composed of 8 stages of FFs that shift in a cycle of [s] and receives data of 320 [ns] per bit in 8T.

The time counter 502 is a 3-bit counter for determining the timing of extracting data from the received serial communication packet, and is incremented by 1 when the operating flag 506 is "1" and "0" when it is counted up to "7". I will return to "and continue counting up.

The data number counter 503 is a counter which is composed of n bits and which is incremented by the logical product of the time counter value "7" and the operating flag 506, and counts the number of data bits of the serial communication packet. It is a thing.

The time counter 502 and the data number counter 503 are reset by the output signal of the AND gate 536.

The data number storage register 504 is provided with the scan bit number 50 supplied from the diagnostic control processor 120.
40 is a register for storing 40.

The start detection flag 505 is a flag which is set when the start bit of the serial communication packet is received, and is for detecting the sampling timing of data extraction.

The operating flag 506 is a flag set at the sampling timing detected by the start detection flag 505.

The error detection flag 142 is set to 80 [n before and after the sampling timing during reception of 1-bit data.
It is a flag that is set when there is a change by checking that the data does not change within [s]. The error detection flag 142 is also set when the end bit is not "1", that is, when there is an error notification from the transmitting side. The value of the error detection flag 142 is sent as the error detection signal 1420.

The reception data storage buffer 508 is a buffer which is composed of FF groups and stores the reception data bit by bit by the shift advance signal SFTADV. From the received data storage buffer 508, received data 5080
Is sent.

The plus 1 circuits 509, 510 and 512 are
It is a circuit that outputs a value obtained by adding 1 to input data.

The plus 2 circuit 551 is a circuit for outputting a value obtained by adding 2 to the input data.

The comparators 513 to 517 are circuits which output "1" when the two inputs match. One of the inputs of the comparator 513 is always supplied with "000", and the comparator 51
"111" is always given to one of the four inputs.
One of the inputs of the comparator 515 is fixed to "0".

AND gates 518 to 524, 526, 5
Reference numerals 28 to 530 and 534 to 536 are circuits that output the logical product of the respective inputs.

The NAND gate 519 is a circuit for outputting an inverted signal of the logical product of the inputs.

The inverting input NAND gate 520 is a circuit which inverts each input to obtain a logical product and outputs the inverted signal.

The inverters 527, 531 to 533 are circuits which output inverted signals of their respective inputs.

The OR gate 525 is a circuit which outputs a logical sum of inputs.

Serial communication receiver 1 having the above configuration
The operation of 40 will be described with reference to the drawings. 6 and 7 are time charts showing the operation of each part of FIG.

First, referring to FIG. 6, when the serial communication receiving unit 140 receives a serial communication packet, a pattern "1" → "0" is generated in the scan-in register 501, and the start bit is detected. When the start bit is detected, the start detection flag 505 is set (). The sampling timing, that is, the center of the communication packet data is detected by the start detection flag 505 and the sixth and seventh bits of the scan-in register 501, and the operating flag 506 is set ().

When the operating flag 506 is set, the time counter 502 starts counting up ().
When the value of the time counter 502 becomes "7", the data number counter 503 is incremented by 1 and becomes "1" ().

When the value of the data number counter 503 becomes "1", the shift advance signal S becomes "0" with the value of the time counter.
FTADV becomes "1" and the received data storage buffer 5
In 08, the third bit of the scan-in register 501, that is, 1 extracted from the received data of the serial communication packet
Store bits ().

Thereafter, the scan-in data bit extraction is repeated until the values of the data number counter 503 and the data number storage register 504 match.

Then, moving to FIG. 7, it is repeated until the reception of the scan data bit is finished (), and when the value of the data number counter 503 becomes a value obtained by adding “1” to the value of the data number storage register 502. , Receive the end bit ().

If the received end bit is "1", it means normal termination, and if it is "0", the error detection flag 142 is set (). Then, when the value of the data number counter 502 becomes a value obtained by adding “2” to the value of the data number storage register 503, the in-operation flag 506, the time counter 502, and the data number counter 503 are reset and the operation ends. To ().

The diagnostic control processor 120 monitors the operating flag 506, and when the value becomes "0", it refers to the received data storage buffer 508 and the error detection flag 142. When the error detection flag 142 is "1", the diagnostic control processor 120 performs re-execution or failure processing.

FIG. 8 is a block diagram showing the configuration of the second embodiment of the diagnostic apparatus and the apparatus to be diagnosed according to the present invention and the electronic apparatus including them, and the same parts as those in FIG. 1 are designated by the same reference numerals. In the figure, the electronic device of this embodiment is configured to include devices to be diagnosed 600 and 601 and a diagnostic device 100 for performing these diagnoses.

In this embodiment, the LS in the device under diagnosis 600 is
The number of I scan bits is unified, and LSIs in the same device are connected to each other. With such a configuration, the number of paths between the diagnostic device 100 and the devices to be diagnosed 600 and 601 can be reduced.

In such a configuration, the scan data of the LSI 210 is moved to the LSI 220 as the returned serial data from the diagnostic device 100 in the first serial communication. At the same time, the scan data of the LSI 220 is read into the diagnostic device 100 as reply serial data. Further, in the second serial communication, the scan data of the LSI 210 moved to the LSI 220 in the first serial communication is used as the reply serial data and the diagnostic device 100
Read by.

When an error occurs during these two serial communications, the diagnostic device 100 can determine the presence / absence of an error by the propagation of the error indication displayed in the end bit of the serial communication packet.

As described above in the first and second embodiments, in the electronic device of the present invention, the scanning operation is performed by the communication in the serial packet format, so that the diagnostic device and the device to be diagnosed are installed separately. However, the scanning operation can be performed while ignoring the wiring delay between the devices. Therefore, it is possible to quickly diagnose the device to be diagnosed. Also, the I / O (Input / Ou) of the LSI in the device to be diagnosed
It is also possible to reduce the number of input pins (tput) compared to the conventional scan path method. Further, since the diagnosis is performed using the clock in each device without having the scan clock, the internal information of the LSI can be read during the operation of the device without stopping the system.

Here, the diagnosis time by the electronic device of the present invention will be verified in comparison with the conventional device. When the wiring delay time X [ns] between devices and the transfer bit length L [bit] are used as parameters, one transfer time TP according to the conventional technique is used.
Is TP = 2XL [ns]. On the other hand, one transfer time TN according to this embodiment is
If the transfer cycle per bit is C [ns], then TN = 2X + CL [ns]. Further, when the transfer bit length L is large, TN≈CL [ns]. The following can be said by comparing the transfer time TP and the transfer time TN. First, in the conventional technique, the transfer time is determined by the maximum inter-device delay time, which is disadvantageous for diagnosing a device having a physical spread. It is also clear that generally X> C and TP> TN.

From the above, unless L is extremely small or X and C are almost the same (this is very unlikely), the device of this example diagnoses faster than the conventional device. You can see that you can.

[0102]

As described above, the present invention has an effect that the number of signal lines required for diagnosis is small because the scan clock is not used by transmitting / receiving data in the serial packet format.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a diagnostic device, a device to be diagnosed, and an electronic device including them according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a format of a serial communication packet in FIG.

FIG. 3 is a block diagram showing an internal configuration example of a serial communication transmission unit in FIG.

FIG. 4 is a time chart showing the operation of each unit in FIG.

5 is a block diagram showing an example of an internal configuration of a serial communication receiving unit in FIG.

FIG. 6 is a time chart showing the operation of each part of FIG.

FIG. 7 is a time chart showing the operation of each part of FIG.

FIG. 8 is a block diagram showing a configuration of a diagnostic device, a device to be diagnosed, and an electronic device including them according to a second embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional diagnostic device, a device to be diagnosed, and an electronic device including them.

FIG. 10 is a time chart showing the operation of each part of FIG.

[Explanation of symbols]

 100 Diagnostic Device 110, 212 Serial Communication Transmitter 130 FF Number Table 140, 211 Serial Communication Receiver 150 Selector 160 Decoder 200, 300, 600, 601 Diagnosed Device 210, 220 LSI 213 LSI Internal Information FF

Claims (6)

[Claims] 1. A diagnostic device for writing data to each flip-flop forming a scan path provided in the device to be diagnosed, comprising data sending means for sending the data in a serial packet format, and a device to be diagnosed. Receiving means for receiving data in serial packet format about the data held in each flip-flop that constitutes the scan path, which is sent from the device, and diagnoses the device to be diagnosed based on the received data. Diagnostic device. 2. The receiving means comprises sampling means for sampling the data with a clock having a cycle shorter than a cycle of a data clock of the data, and the sampling result is used as the received data. 1. The diagnostic device according to 1. 3. Receiving means for receiving data in the serial packet format sent from the diagnostic device, and means for writing this received data to each flip-flop forming a scan path provided in the device itself. A device to be diagnosed comprising: 4. The receiving means has a sampling means for sampling the data with a clock having a cycle shorter than a cycle of a data clock of the data, and the sampling result is used as the received data. 3. The diagnostic device according to 3. 5. An electronic device including a device to be diagnosed and a device to write data to each flip-flop that constitutes a scan path provided in the device to be diagnosed, wherein the device to be diagnosed is A first receiving means for receiving serial packet format data sent from the diagnostic device,
Writing means for writing the received data thus received to each flip-flop forming a scan path provided in the device itself, wherein the diagnostic device sends data in the serial packet format. And second receiving means for receiving data in serial packet format regarding the data held by each flip-flop that constitutes the scan path and is sent from the device to be diagnosed. The received data of the second receiving means An electronic device which diagnoses the device to be diagnosed based on the following. 6. The sampling means for sampling the data with a clock having a cycle shorter than a cycle of a data clock of the data, and the sampling results are used as the reception data. The electronic device according to claim 5.