JPH0799493A - Atm transmitter - Google Patents

Abstract

PURPOSE:To relay and transmit an STM signal of a multiplex access line with an ATM network by processing each basic line of the multiplex access line to be a cell and setting different VPI and VCI from each basic line. CONSTITUTION:A cell composing section 2 decomposes a synchronous transfer mode(STM) signal for each basic line and accommodates the signal of the basic line to an asynchronous transfer mode(ATM) cell having a different virtual path identifier(VPI) and a different virtual channel identifier(VCI) from each base line so as to compose the ATM cell having the presence of a head time slot of a frame of an STM signal of the basic line in an information filed of the ATM cell and pointer information representing the position of the head time slot. A cell decomposing section 3 uses the VPI and VCI to decomposes the ATM cell received from the ATM network for each basic line and reproduces the STM signal from each ATM cell for each basic line by using the pointer information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM transmission device for performing an ATM adaptation process for relaying and transmitting an STM signal in an ATM network, and more particularly to an ATM transmission device for an STM signal of a multiple access line.

[0002]

2. Description of the Related Art As a conventional ATM transmission device for performing an ATM adaptation process for relaying and transmitting an STM signal in an ATM network, there is, for example, one disclosed in Japanese Patent Laid-Open No. 4-249447. FIG. 10 is a conceptual diagram of a conventional system for relaying and transmitting a point-to-point STM signal in an ATM network.

FIG. 11 shows the AT of FIG. 10 shown in the above document.
It is explanatory drawing of the ATM adaptation process in M transmission apparatus. Here, the STM signal is the existing 6.3 Mb / s.
Taking the signal of the high-speed digital leased line of, for example, the ATM cell as I. Compliant with 362.

As shown in FIG. 11, one frame of a 6.3 Mb / s high-speed digital leased line is composed of 98 time slots + 5 bits. Here, one time slot is composed of 8 bits (= 1 byte). When these STM signals are accommodated in ATM cells, 6.3 Mb
All signals (98 time slots + 5 bits) for one frame of the / s leased line were accommodated in the 47-byte long area of the information field of the ATM cell without any space. That is, in the information field of the ATM cell, 4 bits of a sequence number (hereinafter, referred to as SN) indicating the order of ATM cells and 4 bits of a sequence number protection bit (hereinafter, referred to as SNP) for performing error correction of the above sequence number.
Together with the bits, it accommodated 47 bytes of high-speed digital line signals.

Regarding the consecutive frames of the above 6.3 Mb / s high-speed digital line, 47 bytes from the beginning of frame A are accommodated in cell C, the next 47 bytes of frame A are accommodated in cell D, and frame A is accommodated. 4 bytes remaining +
All the signals of the high-speed digital line are mapped to the ATM cells such that 5 bits and 42 bytes + 3 bits from the beginning of the next frame B are accommodated in the cell E. The start position of the frame is indicated by 5 bits of F bits included in the signal of the high speed digital line.

Further, in the conventional ATM transmission apparatus, the reception A
5. By connecting the time slot and the F bit mounted in the information field of the TM cell,
It is possible to reproduce the signal of the 3 Mb / s high-speed digital leased line. At this time, it is possible to judge the loss of the ATM cell from the continuity of the SN of the received ATM cells.
By using N and SNP together, bit error detection and correction in SN can be performed. If ATM
When cell loss is detected, fixed data is inserted in place of the lost data, so that the periodicity of the STM signal frame can be guaranteed.

[0007]

A conventional STM signal is
The ATM transmission device for relay transmission in the TM network has been proposed as described above, but has the following problems. (1) All time slots have the same virtual path identifier (VPI) and virtual channel identifier (VCI)
Since it is mapped to an ATM cell having an STM signal, it is impossible to relay and transmit an STM signal having a different destination for each time slot as in a multiple access line. (2) As the number of time slots per frame of the STM signal is smaller than the octet length of the information field of the ATM cell, the processing time for assembling and disassembling the ATM cell increases, so the transmission delay time of the ATM cell increases. . (3) The time slot configuration of the basic line of the STM signal is not fixed and cannot be easily dealt with when it is changed in a timely manner.

The present invention has been made to solve the above problems, and obtains an ATM transmission apparatus capable of relaying and transmitting an STM signal having a different destination for each time slot of a multiple access line through an ATM network. The purpose is to Another object of the present invention is to obtain an ATM transmission device that suppresses an increase in the transmission delay time of an ATM cell even when the number of time slots per frame of the STM signal is small. Another object of the present invention is to obtain an ATM transmission device that can easily cope with the case where the time slot structure of the basic line of the STM signal is not fixed and can be changed in a timely manner.

[0009]

In order to achieve the above object, an ATM transmission apparatus according to a first aspect of the present invention uses a synchronous transfer mode (hereinafter referred to as STM) signal in an asynchronous transfer mode (hereinafter referred to as ATM). A) for relay transmission on the network
An ATM transmission device for performing a TM adaptation process is provided with the following elements so that an STM signal of a multiple access line is relayed and transmitted by an ATM network.
(A) The STM signal is decomposed for each basic line, and the signal of the basic line is provided with a different virtual path identifier (hereinafter referred to as VPI) and a virtual channel identifier (hereinafter referred to as VCI) for each basic line. In the ATM cell, the presence / absence of the head time slot of the frame of the STM signal of the basic line in the information field of the ATM cell, and the pointer information indicating the position of the head time slot in the information field are stored in the ATM cell. A cell assembler having means for assembling an ATM cell in the information field of the cell; and (b) A received from the ATM network.
A cell disassembling unit having means for separating the TM cells for each basic line using the VPI and VCI, and reproducing the STM signal from each ATM cell for each basic line using the pointer information.

Further, in the ATM transmission apparatus of the invention according to claim 2, the cell assembling unit of the ATM transmission apparatus of the invention according to claim 1 provides information indicating the length of the time slot of the STM signal accommodated in the ATM cell. The means for accommodating the information field of the ATM cell and the means for cell disassembling unit are provided with means for reproducing the STM signal by using the information indicating the length of the time slot of the STM signal.

The ATM transmission apparatus of the invention according to claim 3 is the AT of the invention according to claim 1 or 2.
The M transmission device has an address control memory for storing information indicating the position of a valid time slot in the STM signal, and by rewriting the above information, the ATM transmission device
The time slot accommodated in the cell can be changed at any time.

[0012]

In the ATM transmission apparatus of the invention according to claim 1 configured as described above, a cell is formed for each basic line of the multiple access line, and VPI and VCI different for each basic line.
By setting, the STM signal of the multiple access line can be relayed and transmitted by the ATM network.

Further, in the ATM transmission apparatus of the invention according to claim 2, in addition to the operation of the invention according to claim 1,
By using the information indicating the number of time slots of the STM signal in the M cell, at the time of cell formation, all the areas that can accommodate the STM signal in the information field of the ATM cell,
When a basic line with a low transmission rate is converted into a cell without mapping the STM signal, the transmission delay time of the ATM cell can be shortened by mapping only one frame of the STM signal in one cell.

Further, in the ATM transmission apparatus of the invention according to claim 3, in addition to the operation of the invention according to claim 1 or claim 2, the portion storing the "time slot attribute" of the address control memory is By configuring the random access memory (RAM) that is easy to rewrite, the time slot configuration of the basic line of the STM signal is not fixed but can be easily changed.

[0015]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a concept of a system for relaying and transmitting an STM signal of a multiple access line in which an ATM transmission device which is the object of the present invention is used. FIG. 2 shows A of FIG.
It is an overall configuration block diagram of a TM transmission device. In FIG. 2, the ATM transmission device comprises an existing network interface unit 1, a cell assembly unit 2, a cell disassembly unit 3, and a user network interface unit 4.

FIG. 3 is a diagram showing an example of the construction of the cell assembling section 2 of FIG. In FIG. 3, 5 is a cell assembling unit A, 6 is a cell assembling unit B, 7 is a cell multiplexing unit (hereinafter referred to as MUX), 8 is a transmission side address control memory (hereinafter referred to as AC).
M (S)) and 9 are STM frame cycle counter units.

FIG. 4 is a diagram showing a configuration example of the cell disassembling unit 3 of FIG. In FIG. 4, 11 is a cell separation unit (hereinafter, D
MUX), 12 decellization unit A, 13 decellization unit B, 14 multiplexing unit, 15 address control memory on the receiving side (hereinafter referred to as ACM (R)), 16 STM frame cycle It is a counter section.

As an STM signal handled in the first embodiment, consider an existing 6.3 Mb / s high-speed digital leased line having a multiple access service function. This high-speed digital line is composed of 98 time slots (96 time slots for data lines and the remaining 2 time slots for undefined bits) and 5 F bits in one frame. Is. The multiple access service function divides all or part of the 96 data line time slots into several groups, and each group is provided as one basic line. At this time, the connection partner of each basic line is different. In the first embodiment, as shown in FIG. 5, as a basic line for multiple access,
It is assumed that basic lines of 3 Mb / s and 1.5 Mb / s are set. The former basic line is called basic line 1 and the latter basic line is called basic line 2. The basic line 1 is composed of 48 time slots, and the basic line 2 is composed of 24 time slots. The remaining STM signals are unused 26
Number of time slots and F bits.

Next, the operation will be described with reference to FIGS. ST input to the ATM transmission apparatus shown in FIGS.
The M signal is converted into transmission data and a frame synchronization signal by detecting frame synchronization of the STM signal using the F bit of the high speed digital line in the existing network interface unit 1. Here, the frame synchronization signal is a signal indicating the head position of the STM frame. The transmission data and the transmission frame synchronization signal are sent to the cell assembling unit 2 to assemble a transmission cell.

Next, the procedure for making cells will be described with reference to FIGS. FIG. 3 is a diagram showing a configuration example of the cell assembling unit of FIG. In FIG. 3, the STM frame cycle counter unit 9 uses the transmission frame synchronization signal from the existing network interface unit 1 to generate an address for ACM (S). This address cyclically increases in synchronization with the frame phase of the STM signal. That is, the address 0 is generated at the head time slot (first time slot) position of the STM frame, and the address i is generated at the i-th time slot position. (Here, i = 1 to 97) The ACM (S) 8 stores information (called time slot attribute) indicating which of the basic line 1, the basic line 2, and the empty area each time slot corresponds to. is doing. FIG. 8 illustrates a time slot attribute for each time slot of the STM signal stored in the ACM (S) 8. Here, the address is the address of this storage area, and the time slot attribute is stored as data at the corresponding address. In this example, as the time slot attribute, as shown in FIG. 8, the time slots from the 0th to the 47th belong to the basic line 1, and the 48th to the 7th.
Time slots up to number 1 belong to basic line 2, 72nd
It shows that the time slots from No. to No. 97 are empty areas.

The ACM (S) 8 shown in FIG. 3 outputs the time slot attribute corresponding to the address output by the STM frame cycle counter section 9. In the cell assembling unit A5, A
Using the value of the time slot attribute output from the CM (S) 8, the time slot of "basic line 1" in the STM signal is fetched and converted into an ATM cell. That is, when "time slot attribute" = 1, the time slot of the basic line 1 is fetched and converted into an ATM cell. Similarly, in the cell assembling unit B, when "time slot attribute" = 2, the time slot of the basic line 2 is fetched and converted into an ATM cell. When the time slot attribute indicates "free space",
That is, when "time slot attribute" = 0, the time slot is not captured and is not converted into an ATM cell. In the cell assembling section A5 and cell assembling section B6, the VPI and VCI given to the cell are as follows:
Use a combination of different values. These VPI, VC
I is determined in advance by negotiation with the ATM network.

Next, regarding the method of ATM adaptation (AAL) in the cell assembling section A5 and cell assembling section B6,
This will be described with reference to FIGS. FIG. 5 shows an example of a frame structure of a signal of a multiple access service function of a high speed digital line of 6.3 Mb / s as an STM signal and a method of mapping a high speed digital signal to an ATM cell (AAL). As shown in FIG. 5, it is assumed that two basic lines of 3 Mb / s and 1.5 Mb / s are set as basic lines of multiple access.

Mapping to ATM cells is performed as follows. First, 44 bytes from the beginning of the basic line 1 of the frame A of the STM signal are placed in the cell D, the remaining 4 bytes of the basic line 1 of the frame A and 4 bytes from the beginning of the basic line 1 of the frame B.
0 bytes in cell E, 24 bytes of basic line 2 in frame A and 20 bytes from the beginning of basic line 2 in frame B in cell F, 8 bytes remaining in basic line 1 in frame B and basic line in frame C 36 bytes from the beginning of 1 is the cell G
Map to. That is, for each basic line, the time slots of consecutive frames are divided into 44 bytes and are sequentially accommodated in the payload of cells.

Next, the accommodating position in the payload will be described with reference to FIG. 6 prior to the description with reference to FIGS.

FIG. 6 shows an example of the structure of an ATM cell in the ATM transmission device of the present invention. As shown in FIG.
The M cell is composed of an ATM header of 5 bytes and a payload of 48 bytes. The payload further includes a 1-byte SAR-PDU header and a 45-byte SAR-PD.
It consists of a U payload and a 2-byte SAR-PDU trailer. The SAR-PDU header is composed of a sequence number (hereinafter referred to as SN) and a sequence number protection bit (hereinafter referred to as SNP), and the SAR-PDU payload is a pointer (hereinafter referred to as PTR) and user information. The SAR-PDU trailer consists of areas
It is composed of a user area length identifier (hereinafter referred to as LI) and an error detection bit (hereinafter referred to as CRC). STM
The time slots of the signal are accommodated in order from the beginning of the user information area.

Here, the same SN and SNP as the SN and SNP in AAL (type 1) shown in CCITT Recommendation (I.363) are used. Also, L
I and CRC are also the same as I. AAL indicated at 363
The same LI and CRC in (Type 3/4) are used. Here, description of these bits is omitted.

The PTR is an STM in the user information area.
Indicates the presence and position of the first byte of the signal. When the first byte of the STM signal exists in the user area, its position is represented by the number of bytes from the PTR area. At this time, PT
Possible values of R are 1 to 44. When the first byte of the STM signal does not exist in the user information area, the value other than 1 to 44, for example, the value 0 is assumed.

As shown in FIG. 5, the cell D accommodates 44 bytes of the basic line 1 in the frame A of the high speed digital line. Since this cell D is the first cell including the time slot of the basic line 1, SN = 0. Correspondingly, SNP = 0. The PTR is a value indicating how many bytes the head byte of the basic line is away from the head position of the user area of the cell when the head byte of the basic line is included in the cell. Therefore, PTR takes a value from 0 to 43. In cell D, since the first byte of the basic line 1 is accommodated in the first byte of the user information area of the cell, PTR =
Set to 0. The LI is the ST accommodated in the user information area.
It indicates the number of bytes of the M signal and takes a value from 1 to 44. In cell D, all user information areas have STM
Since the signal is accommodated, LI = 44. CRC is P
Insert the result of the CRC operation over the TR, user information, and LI areas. The cell E accommodates the remaining 4 bytes of the basic line 1 of the frame A and the first 40 bytes of the basic line 1 of the frame B. Since it is the second cell including the time slot of the basic line 1, SN = 2 and SNP = 7 is set for this. Further, since the first byte of the basic line 1 of the frame B is accommodated in the fifth byte of the user information area of the cell E, PTR = 4 is set. Like the cell D, the LI is LI = 44. The cell F accommodates 24 bytes of the basic line 2 of the frame A and 20 bytes of the basic line 2 of the frame B. Since this cell is the first cell including the time slot of the basic line 2, SN = 0. Correspondingly, SNP = 0. In the cell F, the first byte of the basic line 2 is of frame A and frame B
It is sufficient to indicate the position of the first byte of the frame A, which is the first first byte, in the PTR, since the first byte is included in the PTR. Therefore, PTR = 0. Naturally, LI
= 44. In the cell G, the remaining 8 bytes of the basic line 1 of the frame B and the first 36 bytes of the basic line 1 of the frame C are included.
Accommodates a bite. Since it is the third cell of basic line 1,
When SN = 3, SNP becomes SNP = 10. Since the first byte of the basic line 1 of the frame C is accommodated in the 9th byte of the user information area of the cell G, PTR = 8 is set. The LI is LI = 44.

The VPI and VCI of each cell are set in correspondence with the basic line. That is, certain VPI and VCI are set in the cell D, cell E and cell G, and VPI and V are set in the cell F.
The CI sets VPI and VCI such that at least one of VPI and VCI is different from that set in the cell D.

As described above, as shown in FIGS. 1, 2 and 3, A formed by the cell assembling section A5 and the cell assembling section B6.
The TM cell is cell-multiplexed by the MUX 7 and sent to the user network interface unit 4 as a transmission cell. In the user network interface unit 4, the above transmission cell is subjected to processing such as HEC calculation of the ATM header and then output to the ATM network as an ATM transmission signal.

Next, the procedure for reproducing the STM signal from the ATM received signal will be described with reference to FIGS. First, in the user network interface unit 4 of FIG. 2, a reception cell is obtained by performing cell separation conversion based on the format of the user network interface. The received cell is sent to the cell disassembling unit 3.

The cell disassembling unit 3 extracts the STM signal mapped to the reception cell and reproduces the reception STM signal. The operation of the cell disassembly unit 3 will be described below with reference to FIG. The reception cell is a cell separation unit (DMUX1
By identifying the VPI and VCI of the cell in 1), the cell including the time slot of the basic line 1 and the cell including the time slot of the basic line 2 are separated. At this time, the VPI corresponding to the basic line 1 and the basic line 2,
The VCI is decided in advance by negotiation with the ATM network. The cells other than the basic line 1 and the basic line 2 are discarded by the DMUX 11. The deceleration unit A12
The cell including the time slot of the basic line 1 is taken in,
The decellizing unit B13 takes in a cell including the time slot of the basic line 2. Decellization unit A12 and decellization unit B
At 13, the following processing is performed on each of the captured cells. First, if any of the following items is satisfied, the corresponding cell is discarded. (1) When an uncorrectable bit error is detected using SN and SNP. (2) When a bit error is detected by CRC. When the cell is discarded for these reasons, the maintenance person or the like can be notified to that effect.

When there is no bit error in the SN, the received SN is used as a reception sequence number (SNr), and when a correctable bit error is detected, the corrected SN is set to SN.
Let r. In this way, for cells whose information content is guaranteed by SN, SNP, and CRC, the time slots of STM signals included in the cells are stored in the buffer within the decellizing unit in the order of SNr. At this time, the time slot at the head position is identified by the PTR and the number of time slots stored in the cell is identified by the LI, and the phase of the time slot at the head is recognized and stored in the buffer. Further, when discontinuity is detected in the SNr of cells, the time slots corresponding to the missing cells are skipped and stored in the buffer. The size of the basic line is
Determined by the type of basic line described above, 48 time slots for basic line 1 and 24 for basic line 2
It is a time slot.

The STM frame cycle counter section 16 shown in FIG. 4 is the STM frame cycle counter section 9 shown in FIG.
Similarly, the value from 0 to 97 is counted periodically,
The count value is output to the ACM (R) 15 as an address. The phase of the count cycle does not have to match the phase of the STM frame cycle counter unit 6. Further, the STM frame cycle counter section 16 outputs a reception frame synchronization signal in synchronization with the above count cycle. Figure 4
The ACM (R) 15 shown in FIG. 3 is the ACM (S) shown in FIG.
The storage area is the same as in No. 8, and the time slot number of the STM signal is used as an address, and the value indicating whether each time slot belongs to the basic line 1, the basic line 2, or the empty area, and in each basic line The time slot number of is stored as a "time slot attribute". Figure 9 shows ACM (R) 1
5 illustrates a time slot attribute within 5. In FIG.
The time slot attribute is composed of a basic line number and a time slot number in each basic line. However, "basic line number = 0" indicates an empty area.

The ACM (R) 15 corresponds to the address output from the STM frame cycle counter section 16
The above "time slot attribute" information is output. When the "time slot attribute" indicates the basic line 1 ("basic line number = 1"), the time slot is read from the buffer in the decellizing unit A12, and the "time slot attribute" indicates the basic line 2 (" When the basic line number = 2 "), the time slot is read from the buffer in the decellizing unit B13. When reading the time slots stored in the buffers in the decellization unit A12 and the decellization unit B13, the phase at which the first time slot is read is “time slot number = 0” in the “time slot attribute”. Try to be in time.

The multiplexing unit 14 multiplexes the time slots read from the decellizing unit A12 and the decelerating unit B13 to create received data.

As shown in FIG. 2, the existing interface unit 1
Then, using the received data and the received frame synchronization signal, the received data is subjected to signal conversion as an STM signal, and then sent as an STM received signal.

Example 2. In the first embodiment, when the STM signal is mapped to the ATM cell, the time slots of consecutive frames are accommodated in the cell without a gap, so when the number of time slots per frame is small, a plurality of frames are included in one cell. STM signal of Therefore, the cell generation interval increases, and when regenerating the cell, it becomes necessary to store the cell in a larger buffer to absorb the cell arrival interval. The accumulation in this buffer causes an increase in processing delay time. Therefore, in order to suppress the generation interval of this cell, when the STM signal is mapped to the ATM cell, for example, only one frame of the STM signal may be mapped to one cell.

FIG. 7 shows a second embodiment of the ATM transmission device of the present invention.
FIG. 6 is an explanatory diagram of an ATM adaptation process showing The STM signal having the multiple access function of the high-speed digital line of 6.3 Mb / s as in FIG.
The second embodiment shows a mapping method in which only one frame of the STM signal is stored in one cell for the basic line 2.

Next, a method of mapping STM signals onto ATM cells will be described with reference to FIG. Although the detailed structure of the payload is not shown in FIG. 7, the structure of the ATM cell is the same as that of FIG. First, S
Regarding the basic line 1 of the TM signal, since the number of time slots contained in one frame of the STM signal is larger than 44 bytes of the storage area in the ATM cell, cells D, E, G are processed in the same manner as in the first embodiment. Map without gaps.

Regarding the basic line 2 of the STM signal, ST
Since the number of time slots included in one frame of the M signal is 24, which is smaller than 44 bytes of the storage area in the ATM cell, mapping is performed so that only one frame of the STM signal is stored in one cell. That is, first, S
24 bytes of the basic line 2 of the frame A of the TM signal are stored in the cell F. A fixed pattern (for example, all bits are set to 1) is inserted into the remaining 24 bytes of the cell. In cell F, LI = 24 and PTR = 0 are set. Next, the 24 bytes of the basic line 2 of the frame B are stored in the cell H. In addition, the area of the remaining 24 bytes of the cell,
The same value as that of the cell F is set in LI and PTR.

In the first embodiment, the generation interval of the cells storing the time slots of the basic line 2 is about 1.8 times the frame period of the STM signal, but according to the second embodiment, Since the mapping is performed so that only one frame of the STM signal is stored in one cell, cells can be generated at the frame cycle intervals of the STM signal.

Comparing the mapping methods of the first embodiment and the second embodiment, the first embodiment is advantageous in terms of cell mapping efficiency and H / W scale of the buffer and the like, while the cell processing is performed. The second embodiment is more advantageous in terms of delay time. Therefore, which method to select may be determined by these trade-offs.

The structure of the ATM cell shown in FIG. 6 used in the description of the first and second embodiments is not limited to this, and a cell structure in which LI and CRC are deleted may be used, for example. Further, the PTR configuration can use a P format pointer in the structured data transmission method as discussed in the AAL (type 1) of CCITT Recommendation (I.363).

In the first and second embodiments, 6.3 is used.
Although the F bit including the failure information is not transmitted in the signal of the multiple access service function of the Mb / s high-speed digital line, if the failure information is desired to be transmitted,
An AM cell or a cell for failure information may be separately set, and failure information may be transmitted using these cells.

Example 3. In the first and second embodiments of the ATM transmission apparatus of the present invention, the time slot structure of the basic line of the STM signal was considered as fixed, but it is possible to easily cope with the case of changing this timely. For example, it is possible to easily use the basic lines 1 and 2 in the daytime and only the basic line 1 in the nighttime. In the ACM (S) 4 and the ACM (R) 11 shown in FIGS. 3 and 4, a portion for storing the “time slot attribute” is configured by a random access memory (RAM), and the stored content of the RAM is rewritten. As a result, even when the time slot configuration of the basic line 1 and the basic line 2 is changed in a timely manner, it can be easily dealt with.

Further, the ACM (S) 4 and the ACM (R) 11
It is also possible to combine the two and use them as one address control memory. It goes without saying that the same configuration can be realized even when the number of basic lines is two or more.

[0048]

As described above, according to the invention of claim 1, it is possible to obtain an ATM transmission device capable of relaying and transmitting an STM signal having a different destination for each time slot of a multiple access line through an ATM network. You can Further, according to the invention of claim 2, in addition to the effect of the invention of claim 1, even when the number of time slots per frame of the STM signal is smaller than the octet length of the information field of the ATM cell, the ATM It is possible to obtain an ATM transmission device that suppresses an increase in cell transmission delay time. Further, according to the invention of claim 3, in addition to the effect of the invention of claim 1 or 2, it is possible to easily cope with the case where the time slot configuration of the basic line of the STM signal is changed and used in a timely manner. It is possible to obtain an ATM transmission device that can be used.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of a system that relays an STM signal of a multiple access line in an ATM network.

FIG. 2 is an overall configuration block diagram of an ATM transmission device common to the embodiments of the present invention.

3 is a block diagram showing a configuration of a cell assembly unit shown in FIG.

FIG. 4 is a block diagram showing the configuration of a cell disassembly unit shown in FIG.

FIG. 5 is an explanatory diagram of ATM adaptation processing according to the first embodiment of the present invention.

6 is a diagram showing a configuration example of the ATM cell of FIG.

FIG. 7 is an explanatory diagram of an ATM adaptation process showing a second embodiment of the present invention.

FIG. 8 is an explanatory diagram of an address control memory (ACM (S)) showing a third embodiment of the present invention.

FIG. 9 is an explanatory diagram of an address control memory (ACM (R)) showing a third embodiment of the present invention.

FIG. 10 is a conceptual diagram of a system for relaying a conventional point-to-point STM signal in an ATM network.

FIG. 11 is an explanatory diagram of ATM adaptation processing of a conventional ATM transmission device.

[Explanation of symbols]

 1 Existing Network Interface 2 Cell Assembly 3 Cell Disassembly 4 User Network Interface 5 Cellularization A 6 Cellularization B 7 Cell Multiplexing 8 Address Control Memory 9 STM Frame Period Counter 11 Cell Separation 12 Deceleration Decoding unit A 13 Decelling unit B 14 Multiplexing unit 15 Address control memory 16 STM frame cycle counter unit 20a to 20d Terminal A to terminal D 25a to 25d ATM transmission device A to ATM transmission device D 30 STM line 35 ATM line network

[Procedure amendment]

[Submission date] April 21, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

FIG. 11 shows the AT of FIG. 10 shown in the above document.
It is explanatory drawing of the ATM adaptation process in M transmission apparatus. Here, the STM signal is the existing 6.3 Mb / s.
The ATM cell is based on the ITU-T recommendation , taking as an example the signal of the high-speed digital leased line.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

[0007]

A conventional STM signal is
The ATM transmission device for relay transmission in the TM network has been proposed as described above, but has the following problems. (1) All time slots have the same virtual path identifier (VPI) and virtual channel identifier (VCI)
Since it is mapped to an ATM cell having an STM signal, it is impossible to relay and transmit an STM signal having a different destination for each time slot as in a multiple access line. (2) As the number of time slots per frame of the STM signal is smaller than the number of octets in the information field of the ATM cell, the processing time for assembling and disassembling the ATM cell increases, so the transmission delay time of the ATM cell increases. To do. (3) The time slot configuration of the basic line of the STM signal is not fixed and cannot be easily dealt with when it is changed in a timely manner.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

Further, in the ATM transmission apparatus of the invention according to claim 2, in addition to the operation of the invention according to claim 1,
By using the information indicating the number of time slots of the STM signal in the M cell, at the time of cell formation, all the areas that can accommodate the STM signal in the information field of the ATM cell,
When the basic line with a low transmission rate is converted into a cell without mapping the STM signal, by mapping only one frame of the STM signal in one cell, a combination of ATM cells is formed.
The processing time for standing and disassembling can be shortened.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

As an STM signal handled in the first embodiment, consider an existing 6.3 Mb / s high-speed digital leased line having a multiple access service function. This high-speed digital line is composed of 98 time slots (96 time slots for data lines and the remaining 2 time slots for undefined bits) and 5 F bits in one frame. Is. The multiple access service function divides all or part of the 96 data line time slots into several groups, and each group is provided as one basic line. At this time, the connection partner of each basic line is different. In the first embodiment, as shown in FIG. 5, as a basic line for multiple access,
It is assumed that basic lines of 3.072 Mb / s and 1.536 Mb / s are set. The former basic line is called basic line 1 and the latter basic line is called basic line 2. Basic line 1
Consists of 48 time slots, and the basic line 2 is 2
It consists of 4 time slots. The remaining STM signals are
There are 26 unused time slots and F bits.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

Next, the operation will be described with reference to FIGS. ST input to the ATM transmission apparatus shown in FIGS.
The M signal is converted into transmission data and a transmission frame synchronization signal by performing frame synchronization detection of the STM signal using the F bit of the high speed digital line in the existing network interface unit 1. Here, the transmission frame synchronization signal is
It is a signal indicating the start position of the STM frame. The transmission data and the transmission frame synchronization signal are sent to the cell assembling unit 2 to assemble a transmission cell.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

Next, the procedure for making cells will be described with reference to FIGS. FIG. 3 is a diagram showing a configuration example of the cell assembling unit of FIG. In FIG. 3, the STM frame cycle counter unit 9 uses the transmission frame synchronization signal from the existing network interface unit 1 to generate an address for ACM (S). This address cyclically increases in synchronization with the frame phase of the STM signal. That is, the address 0 is generated at the position of the first time slot (which is the 0th time slot ) of the STM frame, and the address i is generated at the position of the i-th time slot. (Here, i = 0 to 97) The ACM (S) 8 stores information (referred to as time slot attribute) indicating whether each time slot corresponds to the basic line 1, the basic line 2, or an empty area. is doing. FIG. 8 illustrates a time slot attribute for each time slot of the STM signal stored in the ACM (S) 8. Here, the address is the address of this storage area, and the time slot attribute is stored as data at the corresponding address. In this example, as the time slot attribute, as shown in FIG. 8, the time slots from the 0th to the 47th belong to the basic line 1, and the 48th to the 7th.
Time slots up to number 1 belong to basic line 2, 72nd
It shows that the time slots from No. to No. 97 are empty areas.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

Next, regarding the method of ATM adaptation (AAL) in the cell assembling section A5 and cell assembling section B6,
This will be described with reference to FIGS. FIG. 5 shows an example of a frame structure of a signal of a multiple access service function of a high speed digital line of 6.3 Mb / s as an STM signal and a method of mapping a high speed digital signal to an ATM cell (AAL). As shown in FIG. 5, 3.072 Mb / s and 1.536 Mb / s are provided as basic lines for multiple access.
It is assumed that two basic lines of s are set.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

SN and SNP are ITU-T recommendations.
SN in AAL (Type 1) shown in, SN
Use the same as P. Further, the LI and CRC are also the same as the above I.S. The same ones as LI and CRC in AAL (type 3/4) indicated by 363 are used. Here, description of these bits is omitted.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] 0027

[Correction method] Change

[Correction content]

The PTR is an STM in the user information area.
Indicates the presence and position of the first byte of the signal. When the first byte of the STM signal exists in the user area, its position is represented by the number of bytes from the PTR area. At this time, PT
Possible values of R are 0 to 43 . When the first byte of the STM signal does not exist in the user information area, it takes a value other than 0 to 43 , for example, the value 63 .

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction content]

As shown in FIG. 5, the cell D accommodates 44 bytes of the basic line 1 in the frame A of the high speed digital line. Since this cell D is the first cell including the time slot of the basic line 1, SN = 0. Correspondingly, SNP = 0. The PTR is a value indicating how many bytes the head byte of the basic line is away from the head position of the user area of the cell when the head byte of the basic line is included in the cell. Therefore, PTR takes a value from 0 to 43. In cell D, since the first byte of the basic line 1 is accommodated in the first byte of the user information area of the cell, PTR =
Set to 0. The LI is the ST accommodated in the user information area.
It indicates the number of bytes of the M signal and takes a value from 1 to 44. In cell D, all user information areas have STM
Since the signal is accommodated, LI = 44. CRC is P
Insert the result of the CRC operation over the TR, user information, and LI areas. The cell E accommodates the remaining 4 bytes of the basic line 1 of the frame A and the first 40 bytes of the basic line 1 of the frame B. Since it is the second cell including the time slot of the basic line 1, SN = 1 and SNP = 7 is set for this. Further, since the first byte of the basic line 1 of the frame B is accommodated in the fifth byte of the user information area of the cell E, PTR = 4 is set. Like the cell D, the LI is LI = 44. The cell F accommodates 24 bytes of the basic line 2 of the frame A and 20 bytes of the basic line 2 of the frame B. Since this cell is the first cell including the time slot of the basic line 2, SN = 0. Correspondingly, SNP = 0. In cell F, the first byte of the basic line 2 is in frame A and frame B is in frame B.
It is sufficient to indicate the position of the first byte of the frame A, which is the first first byte, in the PTR, since the first byte is included in the PTR. Therefore, PTR = 0. Naturally, LI
= 44. In the cell G, the remaining 8 bytes of the basic line 1 of the frame B and the first 36 bytes of the basic line 1 of the frame C are included.
Accommodates a bite. Since it is the third cell of basic line 1,
When SN = 3, SNP becomes SNP = 13 . Since the first byte of the basic line 1 of the frame C is accommodated in the 9th byte of the user information area of the cell G, PTR = 8 is set. The LI is LI = 44.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0033

[Correction method] Change

[Correction content]

When there is no bit error in the SN, the received SN is used as a reception sequence number (SNr), and when a correctable bit error is detected, the corrected SN is set to SN.
Let r. In this way, for cells whose information content is guaranteed by SN, SNP, and CRC, the time slots of STM signals included in the cells are stored in the buffer within the decellizing unit in the order of SNr. At this time, the time slot at the head position of the basic line is identified by the PTR, the number of time slots stored in the cell is identified by the LI, and the phase of the head time slot is taken into consideration.
Store in buffer. Further, when discontinuity is detected in the SNr of cells, the time slots corresponding to the missing cells are skipped and stored in the buffer. The size of the basic line is determined by the type of the basic line described above. The basic line 1 has 48 time slots, and the basic line 2 has 24 time slots.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction content]

Example 2. In the first embodiment, when the STM signal is mapped to the ATM cell, the time slots of consecutive frames are accommodated in the cell without a gap, so when the number of time slots per frame is small, a plurality of frames are included in one cell. STM signal of Therefore, when assembling a cell from the STM signal,
The time required for the cell generation process increases and ATM transmission
This causes an increase in processing delay time. Therefore, the treatment of this cell
In order to suppress the processing delay time , when the STM signal is mapped to the ATM cell, for example, only one frame of the STM signal may be mapped to one cell.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0041

[Correction method] Change

[Correction content]

Regarding the basic line 2 of the STM signal, ST
Since the number of time slots included in one frame of the M signal is 24, which is smaller than 44 bytes of the storage area in the ATM cell, mapping is performed so that only one frame of the STM signal is stored in one cell. That is, first, S
24 bytes of the basic line 2 of the frame A of the TM signal are stored in the cell F. A fixed pattern (for example, all bits are set to 1) is inserted in the remaining 20- byte area of the cell. In cell F, LI = 24 and PTR = 0 are set. Next, the 24 bytes of the basic line 2 of the frame B are stored in the cell H. In addition, the area of the remaining 20 bytes of the cell,
The same value as that of the cell F is set in LI and PTR.

[Procedure Amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction content]

Comparing the mapping methods of the first embodiment and the second embodiment, the first embodiment is advantageous in terms of cell mapping efficiency and H / W scale of the buffer and the like, while the cell processing is performed. In terms of delay time, the second embodiment is more advantageous. Therefore, which method to select may be determined by these trade-offs.

[Procedure Amendment 15]

[Document name to be amended] Statement

[Correction target item name] Figure 8

[Correction method] Change

[Correction content]

FIG. 8 is an explanatory diagram of an address control memory (ACM (S)) showing the first embodiment of the present invention.

[Procedure Amendment 16]

[Document name to be amended] Statement

[Correction target item name] Figure 9

[Correction method] Change

[Correction content]

FIG. 9 is an explanatory diagram of an address control memory (ACM (R)) showing the first embodiment of the present invention.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H04Q 11/04

Claims (3)

[Claims] 1. Synchronous transfer mode (hereinafter referred to as STM)
A that performs ATM adaptation processing for relay transmission of signals in an asynchronous transfer mode (hereinafter referred to as ATM) network
An ATM transmission device comprising the following elements, wherein the STM signal of a multiple access line is relayed and transmitted by an ATM network: (a) The STM signal is disassembled for each basic line, and the above basic A signal of a line is accommodated in each basic line in an ATM cell having a different virtual path identifier (hereinafter referred to as VPI) and a virtual channel identifier (hereinafter referred to as VCI), and the basic line in the information field of the ATM cell is accommodated. Cell assembling unit having means for assembling an ATM cell having the presence or absence of the first time slot of the frame of the STM signal and pointer information indicating the position of the first time slot in the information field in the information field of the ATM cell. (B) The ATM cell received from the ATM network is transferred to the VP
A cell disassembling unit having means for separating each basic line using I and VCI and reproducing the STM signal from each ATM cell for each basic line using the pointer information. 2. An ST in which a cell assembling unit accommodates in an ATM cell.
A means for accommodating the information indicating the length of the time slot of the M signal in the information field of the ATM cell and a means for the cell disassembly unit to reproduce the STM signal using the information indicating the length of the time slot of the STM signal. The ATM transmission device according to claim 1, characterized by being provided. 3. An ATM control memory for storing information indicating the position of a valid time slot in an ATM signal, and by rewriting the above information, an ATM control memory is provided.
3. The ATM according to claim 1, wherein the time slot accommodated in the cell can be changed at any time.
Transmission equipment.