JPH0795728B2 - Frame transmission method - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention is used in digital time division multiplex transmission. In particular, American National Standard T1.107-1990 and Proposed Contribution to CCI
TT (Proposed Contribution to CCITT, T1X1.4 AT & T,
Jan.27 1992) and improvement of the DS3 C-bit Parity Frame system.

[0002]

2. Description of the Related Art In the DS3 / C-bit parity frame system, various alarms and information are exchanged using 21 DS2 level control bits (C bits, Control Bits) provided in one multiframe.

FIG. 4 shows the multi-frame structure. This multi-frame has 7 rows x 8 columns x 85 slots = 476
It has a 0-bit configuration, the first row, first column has X bits and 84 bits of information, the second column has F1 bits and 84 bits of information, the third column has AIC bits and 84 bits of information, and the fourth column has F0 bit and 84 bit information, 5th column Na bit and 84 bit information, 6th column F0 bit and 84 bit information, 7th column FEA bit and 84 bit information, 8th column
The columns are F1 bits, (zero bits), S1 bits, and 8
It is configured as 3-bit information. Among 4760 bits, there are 28 F bits, 2 X bits, 2 P bits, 3 M bits, 1 AIC bit, 1 Na bit, 1 FEA bit, 9 Bit C1 bit, 3 bit CP
Bit, 3 bit FEBE bit, 3 bit DLt
Bits, 7 S bits, and 4697 information bits are included.

[0004]

[Problems to be Solved by the Invention] However, the conventional DS3
-In the C-bit parity frame system, the control bits essential for the DS2 signal are used for other purposes. Therefore, when the DS3 / C-bit parity frame system is used, there is a problem that the DS2 signal cannot be accommodated and the DS2 signal cannot be handled.

The present invention solves such a problem and provides a DS
DS2 for 3C bit parity frame
It is an object to provide a frame transmission system capable of accommodating a signal.

[0006]

According to the frame transmission method of the present invention, 3 × 3 = 9 bits of C1 bits assigned to the second, sixth and seventh rows of a multiframe are used as D bits.
It is used as a control bit for two signals and is characterized by accommodating up to three DS2 signals in one multiframe.

[0007]

Operation: C1 bit assigned to the conventional DS3 C-bit parity frame, that is, C bit of the second channel, sixth channel, and seventh channel, 3 ×
3 = 9 bits (fixed) are used as control bits of the DS2 signal, which is the original purpose. The method of processing this bit may be exactly the same as the conventional control bit.

[0008]

1 and 2 show a frame transmission apparatus according to an embodiment of the present invention. FIG. 1 shows a block configuration of a transmitting side, and FIG. 2 shows a block configuration of a receiving side.

The transmitting side is provided with three DS2 stuff circuits 11, 12, and 13 as means for stuffing up to three DS2 signals, and these three DS3 stuff circuits 11, 12, and 13 are respectively provided. The signal from the DS2 interface is input. DS3 stuff circuit 1
The outputs of 1, 12, and 13 are multiplexed as signals of the second channel, the sixth channel, and the seventh channel by the multiplexing circuit 14 together with the DS1 inputs of the other channels. The multiplexed signal is input to the C-bit parity frame insertion circuit 15, and the necessary signal (AIC, N
a, FEA, CP, FEBE, PLt bits and C1 bit) are inserted and output as a DS3 signal. At this time, the C-bit parity frame insertion circuit 15
Inserts information regarding the stuffing process in the DS3 stuffing circuits 11, 12, and 13 into the C1 bit of the multiframe.

On the receiving side, the necessary signals (AIC, Na, FEA, CP, FEBE, P) included in the received DS3 signal are included.
Each bit of Lt and C1 bit) is extracted by the C-bit parity frame extraction circuit 21 and received D
The S3 signal is demultiplexed by the demultiplexing circuit 22. Second channel, sixth channel and seventh channel of demultiplexing circuit 22
The outputs of the channels are supplied to the DS2 destuff circuits 23, 24 and 25, respectively. The control information extracted from the C1 bit in the C-bit parity frame extraction circuit 21 is also applied to the DS2 destuffing circuits 23, 24, 25, and the DS signal destuffing process is performed based on this control information. This control information is the control bit itself of the DS2 signal, and the same processing as the conventional one, that is, the stuffing processing by the majority decision of the control bit of 3 bits corresponding to each DS2 signal is performed.

FIG. 3 shows the C1 bit position in the multi-frame structure of the DS3 C-bit parity frame.
The C1 bit is assigned to each of the 3rd bit in the 2nd, 6th and 7th rows, and these are used as the original control bits of the DS2 signal.

[0012]

As described above, in the frame transmission system of the present invention, a maximum of eight DS2 signals can be accommodated in a DS3.C bit parity frame.
Therefore, in the past, one DS2 signal could not be accommodated in a DS3.C bit parity frame, but a large degree of freedom can be obtained.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a transmission side of a frame transmission device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a receiving side of the frame transmission device according to the embodiment of the present invention.

FIG. 3 is a diagram showing C1 bit positions in a multiframe structure of a DS3 / C-bit parity frame system.

FIG. 4 is a diagram showing a multiframe structure of a DS3 / C-bit parity frame system.

[Explanation of symbols]

 11, 12, 13 DS2 stuffing circuit 14 Multiplexing circuit 15 C-bit parity frame inserting circuit 21 C-bit parity frame extracting circuit 22 Demultiplexing circuit 23, 24, 25 DS2 destuffing circuit

Claims (3)

[Claims] 1. American National Standard and Proposed Contribution to CC
In the frame transmission method for transmitting multiframes of the DS3 / C-bit parity frame method defined by ITT, 3 × 3 = 9-bit C1s assigned to the second, sixth, and seventh rows of the multiframe A frame transmission method characterized in that a maximum of three DS2 signals are accommodated in one multiframe by using the bits as control bits of the D2 signal. 2. The frame according to claim 1, wherein the transmitting side comprises means for performing stuffing processing on up to three DS2 signals, and means for inserting information regarding the stuffing processing into C1 bits of a multiframe. Transmission method. 3. The receiving side is provided with means for extracting control information from the C1 bit of the received multi-frame, and means for performing destuffing processing of the DS signal based on this control information. Frame transmission method.