[go: up one dir, main page]

JPH0794668A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPH0794668A
JPH0794668A JP5239638A JP23963893A JPH0794668A JP H0794668 A JPH0794668 A JP H0794668A JP 5239638 A JP5239638 A JP 5239638A JP 23963893 A JP23963893 A JP 23963893A JP H0794668 A JPH0794668 A JP H0794668A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
memory chip
memory
frame body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5239638A
Other languages
Japanese (ja)
Inventor
Masao Iwata
雅男 岩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP5239638A priority Critical patent/JPH0794668A/en
Publication of JPH0794668A publication Critical patent/JPH0794668A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/144Stacked arrangements of planar printed circuit boards

Landscapes

  • Dram (AREA)

Abstract

PURPOSE:To provide an integrated circuit device provided with means preventing the integrated circuit itself from being rejected even if any one of a large number of memory chips is mounted incorrectly thereon. CONSTITUTION:The integrated circuit comprises a frame body 3 provided with connecting pads 7 on the outer periphery thereof, and memory modules 1, 2 bonded tightly through the frame body 3. Each of the memory modules 1, 2 is provided, on the wiring board 4, with a memory chip 5 and an alternative memory chip 5a connected each other through a signal switching pad 6a.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はメモリーチップを配線基
板上に実装したメモリーモジュールを有する集積回路装
置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device having a memory module having a memory chip mounted on a wiring board.

【0002】[0002]

【従来の技術】図4は従来の集積回路装置を示す分解斜
視図である。図4に示すように、集積回路装置は枠体2
1と、この枠体21を介して密着接合した2つのメモリ
ーモジュール22とからなる。枠体21は外周面の内側
を陥没させた段部23と、この段部23の上下に形成さ
れ外周壁となるガイド部24とを備え、このガイド部2
4の一部を取り除いてスペーサ部25を形成している。
各々のメモリーモジュール22は配線基板26と、この
配線基板26の枠体21を介して相互に向き合う配線基
板26面上の中央部に設けた2つのメモリーチップ27
と、このメモリーチップ27の外側に設けた複数の接続
パッド28とを備え、接続パッド28とメモリーチップ
27とを配線29によって電気的接続をしている。この
配線基板26はガイド部24に沿わせ、かつ段部23に
密着するように嵌合させて接着し、その時両配線基板2
6のメモリーチップ27は枠体21を介して対向してい
る。
2. Description of the Related Art FIG. 4 is an exploded perspective view showing a conventional integrated circuit device. As shown in FIG. 4, the integrated circuit device includes a frame body 2.
1 and two memory modules 22 that are closely bonded to each other via the frame 21. The frame body 21 is provided with a step portion 23 in which the inside of the outer peripheral surface is depressed and a guide portion 24 formed above and below the step portion 23 and serving as an outer peripheral wall.
A part of 4 is removed to form the spacer part 25.
Each memory module 22 includes a wiring board 26, and two memory chips 27 provided in the central portion on the surface of the wiring board 26 facing each other via the frame 21 of the wiring board 26.
And a plurality of connection pads 28 provided outside the memory chip 27, and the connection pad 28 and the memory chip 27 are electrically connected by the wiring 29. This wiring board 26 is fitted along the guide portion 24 and is closely fitted to the step portion 23 so as to be adhered.
The memory chips 27 of No. 6 face each other via the frame 21.

【0003】[0003]

【発明が解決しようとする課題】しかしながら上記従来
の構成では、上下の配線基板26を、そのメモリーチッ
プ27側を内側にして枠体21に固定しているので、こ
の固定後の検査でメモリーチップ27の実装不良による
と思われる動作不良が発生しても、配線基板26を枠体
21から取外すことが困難なため、結果として集積回路
装置そのものが不良となり、多数のメモリーチップを実
装した集積回路装置の製造における歩留まり低下の発生
要因となっていた。
However, in the above-described conventional configuration, the upper and lower wiring boards 26 are fixed to the frame body 21 with the memory chip 27 side thereof facing inward. Even if an operation failure that seems to be caused by a mounting failure of 27 occurs, it is difficult to remove the wiring board 26 from the frame body 21. As a result, the integrated circuit device itself becomes defective, and an integrated circuit on which a large number of memory chips are mounted is mounted. This has been a cause of a decrease in yield in manufacturing the device.

【0004】本発明は上記問題点を解決するもので、多
数のメモリーチップを実装した集積回路装置にメモリー
チップの実装不良が生じても、集積回路装置そのものが
不良となることがないようにすることを目的としてい
る。
The present invention solves the above-mentioned problems, and prevents an integrated circuit device itself from becoming defective even if a defective mounting of the memory chip occurs in the integrated circuit device having a large number of memory chips mounted thereon. Is intended.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明の集積回路装置においては、前記配線基板面
上に代替メモリーチップを実装し、この代替メモリーチ
ップは信号切り替えパッドを介して前記メモリーチップ
に接続したものである。
In order to achieve the above object, in the integrated circuit device of the present invention, an alternative memory chip is mounted on the surface of the wiring board, and the alternative memory chip is provided with a signal switching pad. It is connected to the memory chip.

【0006】[0006]

【作用】上記構成により、集積回路装置のメモリーモジ
ュール内のメモリーチップに実装不良が生じても、不良
のメモリーチップにも信号切り替えパッドを介して代替
メモリーチップと接続しているので、この信号切り替え
パッドによって不良のメモリーチップと代替メモリーチ
ップとを電気的に接続すれば、集積回路装置の不良発生
をなくすことができるものである。
With the above structure, even if the memory chip in the memory module of the integrated circuit device is defectively mounted, the defective memory chip is connected to the alternative memory chip through the signal switching pad. By electrically connecting the defective memory chip and the alternative memory chip by the pad, it is possible to eliminate the occurrence of a defect in the integrated circuit device.

【0007】[0007]

【実施例】(実施例1)以下、本発明の第1の実施例に
ついて図1,図2を参照しながら説明する。
(Embodiment 1) A first embodiment of the present invention will be described below with reference to FIGS.

【0008】図1は本発明の第1の実施例における集積
回路装置の分解斜視図、図2は同集積回路装置の信号切
り替え手段の説明図である。図1に示すように、積層集
積回路装置は枠体3と、この枠体3を介して密着接合し
たメモリーモジュール1とメモリーモジュール2とを備
えた集積回路装置10を2組積層して構成されている。
メモリーモジュール1,2は、配線基板4と、枠体3を
介して相互に向き合う配線基板4上の中央部に設けた8
個のメモリーチップ5と、このメモリーチップ5の外周
に設けた接続パッド6と、メモリーチップ5と接続パッ
ド6とを電気的に接続する配線9とを有している。メモ
リーモジュール1の接続パッド6とメモリーモジュール
2の接続パッド6とを枠体3の接続パッド7と接触さ
せ、これによりメモリーモジュール1とメモリーモジュ
ール2と枠体3とからなる集積回路装置10の電気的な
接続をしている。また集積回路装置10の2つの配線基
板4の内一つは、配線基板4上の接続パッド6の外側に
カードエッジコネクタ8を有し、2組の集積回路装置1
0のカードエッジコネクタ8を備えた2つの配線基板4
を互いに密着接合し、かつ2つの配線基板4のカードエ
ッジコネクタ8を互いに接触させて2組の集積回路装置
10の電気的な接続をしている。さらに2組の集積回路
装置10の配線基板4には、少なくとも一つの代替メモ
リーチップ5aを実装しており、開放状態の信号切り替
えパッド6aを介してこの代替メモリーチップ5aと複
数のメモリーチップ5とを接続している。
FIG. 1 is an exploded perspective view of an integrated circuit device according to a first embodiment of the present invention, and FIG. 2 is an explanatory view of a signal switching means of the integrated circuit device. As shown in FIG. 1, the laminated integrated circuit device is configured by laminating two sets of an integrated circuit device 10 including a frame body 3 and a memory module 1 and a memory module 2 which are closely bonded to each other via the frame body 3. ing.
The memory modules 1 and 2 are provided in the central portion of the wiring board 4 facing the wiring board 4 and the frame body 3 with each other.
It has individual memory chips 5, connection pads 6 provided on the outer periphery of the memory chips 5, and wires 9 that electrically connect the memory chips 5 and the connection pads 6. The connection pad 6 of the memory module 1 and the connection pad 6 of the memory module 2 are brought into contact with the connection pad 7 of the frame body 3, so that the integrated circuit device 10 including the memory module 1, the memory module 2 and the frame body 3 can be electrically connected. Making a physical connection. Further, one of the two wiring boards 4 of the integrated circuit device 10 has a card edge connector 8 on the outside of the connection pad 6 on the wiring board 4, and two sets of the integrated circuit devices 1 are provided.
Two wiring boards 4 with 0 card edge connector 8
Are closely joined to each other, and the card edge connectors 8 of the two wiring boards 4 are brought into contact with each other to electrically connect the two sets of integrated circuit devices 10. Further, at least one alternative memory chip 5a is mounted on the wiring boards 4 of the two sets of integrated circuit devices 10, and the alternative memory chip 5a and the plurality of memory chips 5 are connected via the signal switching pad 6a in the open state. Are connected.

【0009】以上のように構成された積層集積回路装置
について、以下その動作について説明する。通常、積層
集積回路装置はメモリーモジュール1とメモリーモジュ
ール2とを枠体3の接続パッド7を介して電気的に接続
した集積回路装置10の状態で検査を行って製造上発生
する初期的な接続不良を洗い出す。
The operation of the laminated integrated circuit device configured as described above will be described below. Normally, in a laminated integrated circuit device, an initial connection that occurs during manufacturing is performed by inspecting the integrated circuit device 10 in which the memory module 1 and the memory module 2 are electrically connected via the connection pads 7 of the frame body 3. Wash out the defects.

【0010】この際、集積回路装置10に実装したメモ
リーチップ5に実装不良があった場合、実装不良のメモ
リーチップ5の配線9から分線する信号線13に接続し
た開放状態の信号線切り替えパッド6aをハンダ付けに
より短絡して、配線基板4上の接続パッド6と代替メモ
リーチップ5aとを電気的に接続することにより、集積
回路装置10が不良となることを防止し、積層集積回路
装置の不良の発生を抑制することができる。
At this time, when the memory chip 5 mounted on the integrated circuit device 10 has a mounting failure, the signal line switching pad in an open state connected to the signal line 13 which is divided from the wiring 9 of the memory chip 5 having the mounting failure. 6a is short-circuited by soldering to electrically connect the connection pad 6 on the wiring board 4 and the alternative memory chip 5a, thereby preventing the integrated circuit device 10 from being defective, and The occurrence of defects can be suppressed.

【0011】このように本実施例によれば、集積回路装
置10のメモリーチップ5に実装不良が生じていても、
代替メモリーチップ5aにより積層集積回路装置そのも
のが不良となることを防止することができるものであ
る。なお信号線切り替えパッド6aは枠体3外に表出す
る配線基板4端面に形成されており、上記短絡された一
つの信号線切り替えパッド6a以外のものはその後表面
を絶縁樹脂等で覆う。
As described above, according to this embodiment, even if the memory chip 5 of the integrated circuit device 10 is defectively mounted,
The alternative memory chip 5a can prevent the laminated integrated circuit device itself from becoming defective. The signal line switching pad 6a is formed on the end surface of the wiring board 4 exposed to the outside of the frame body 3, and the surface other than the one shorted signal line switching pad 6a is thereafter covered with an insulating resin or the like.

【0012】また、信号線13に信号線切り替えパッド
を設けずに、代替メモリーチップとメモリーチップ5と
を予め短絡しておき、実装不良をしたメモリーチップ5
の配線9から分線する信号線13以外の信号線13を断
線させても上記と同様な効果を生じる。
Further, without providing a signal line switching pad on the signal line 13, the alternative memory chip and the memory chip 5 are short-circuited in advance, and the defective memory chip 5 is mounted.
Even if the signal lines 13 other than the signal line 13 that is branched from the wiring 9 are disconnected, the same effect as described above can be obtained.

【0013】(実施例2)以下、本発明の第2の実施例
について図3を参照しながら説明する。基本的な構成は
実施例1で示した積層集積回路装置と同等であるが、本
実施例では実施例1の構成に加えてメモリーチップ5の
実装側とは反対側の配線基板4面側に導体層11を設け
ている。そして二枚のメモリーモジュール1の配線基板
4に設けた導体層11と、二枚のメモリーモジュール2
の配線基板4に設けた導体層11の一方の導体層11
は、アースラインに接続し、他方の導体層11は、電源
ラインに接続しており、さらに、積層した二組の集積回
路装置10間に誘電体フィルム12を挟んだ構成として
いる。
(Second Embodiment) A second embodiment of the present invention will be described below with reference to FIG. The basic structure is the same as that of the laminated integrated circuit device shown in the first embodiment, but in this embodiment, in addition to the structure of the first embodiment, the wiring board 4 surface side opposite to the mounting side of the memory chip 5 is provided. A conductor layer 11 is provided. The conductor layer 11 provided on the wiring board 4 of the two memory modules 1 and the two memory modules 2
One conductor layer 11 of the conductor layers 11 provided on the wiring board 4
Is connected to a ground line, the other conductor layer 11 is connected to a power supply line, and a dielectric film 12 is sandwiched between two stacked sets of integrated circuit devices 10.

【0014】上記構成によれば集積回路装置そのものが
コンデンサを構成することになり、電源ラインに重畳し
たノイズを吸収することができる。
According to the above configuration, the integrated circuit device itself constitutes a capacitor, and noise superimposed on the power supply line can be absorbed.

【0015】さらに、導体層11が集積回路装置10の
外側面を形成することにより、外部からのノイズも吸収
することができる。
Further, since the conductor layer 11 forms the outer surface of the integrated circuit device 10, noise from the outside can be absorbed.

【0016】このように本実施例によれば、実施例1の
効果に加え、集積回路装置10内の電源ラインに重畳し
たノイズ、集積回路装置10の外部からのノイズを吸収
することができるという効果を生じるものである。
As described above, according to this embodiment, in addition to the effects of the first embodiment, noise superimposed on the power supply line in the integrated circuit device 10 and noise from the outside of the integrated circuit device 10 can be absorbed. It produces an effect.

【0017】[0017]

【発明の効果】以上のように本発明によれば、集積回路
装置内のメモリーチップに実装不良が生じていても、実
装不良のメモリーチップに替えて代替メモリーチップを
使用することができるので、集積回路装置そのものが不
良となることを防止することができる。
As described above, according to the present invention, even if a memory chip in an integrated circuit device has a mounting failure, an alternative memory chip can be used in place of the defective mounting memory chip. It is possible to prevent the integrated circuit device itself from becoming defective.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例における集積回路装置を
示す分解斜視図
FIG. 1 is an exploded perspective view showing an integrated circuit device according to a first embodiment of the present invention.

【図2】同集積回路装置のメモリーチップの信号切り替
え手段を示す説明図
FIG. 2 is an explanatory view showing a signal switching means of a memory chip of the integrated circuit device.

【図3】本発明の第2の実施例における集積回路装置を
示す分解斜視図
FIG. 3 is an exploded perspective view showing an integrated circuit device according to a second embodiment of the present invention.

【図4】従来の集積回路装置を示す分解斜視図FIG. 4 is an exploded perspective view showing a conventional integrated circuit device.

【符号の説明】[Explanation of symbols]

1 メモリーモジュール 2 メモリーモジュール 3 枠体 4 配線基板 5 メモリーチップ 5a 代替メモリーチップ 6 接続パッド 6a 信号線切り替えパッド 7 接続パッド 8 カードエッジコネクタ 9 配線 10 集積回路装置 11 導体層 12 誘電体フィルム 13 信号線 1 Memory Module 2 Memory Module 3 Frame 4 Wiring Board 5 Memory Chip 5a Alternative Memory Chip 6 Connection Pad 6a Signal Line Switching Pad 7 Connection Pad 8 Card Edge Connector 9 Wiring 10 Integrated Circuit Device 11 Conductor Layer 12 Dielectric Film 13 Signal Line

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 枠体と、この枠体を介して密着接合した
2つのメモリーモジュールとからなり、前記枠体はその
外周上に接続パッドを有し、前記メモリーモジュールは
配線基板と、この配線基板の前記枠体を介して互いに向
き合う前記配線基板面上に夫々設けたメモリーチップお
よび代替メモリーチップと、配線によって前記メモリー
チップと電気的接続をした接続パッドとを有し、前記枠
体の接続パッドと前記メモリーモジュールの接続パッド
とを接触させ、前記メモリーチップと代替メモリーチッ
プとは信号切り替えパッドを介して接続した集積回路装
置。
1. A frame body and two memory modules that are closely bonded to each other via the frame body, the frame body having a connection pad on the outer periphery thereof, the memory module having a wiring board, and the wiring board. Connection of the frame body, which has a memory chip and a substitute memory chip respectively provided on the wiring board surface facing each other through the frame body of the substrate, and a connection pad electrically connected to the memory chip by wiring. An integrated circuit device in which a pad and a connection pad of the memory module are brought into contact with each other, and the memory chip and the alternative memory chip are connected via a signal switching pad.
【請求項2】 配線基板のメモリーチップ実装面とは反
対側面上に導体層を設けた請求項1記載の集積回路装
置。
2. The integrated circuit device according to claim 1, wherein a conductor layer is provided on a side surface of the wiring board opposite to the memory chip mounting surface.
JP5239638A 1993-09-27 1993-09-27 Integrated circuit device Pending JPH0794668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5239638A JPH0794668A (en) 1993-09-27 1993-09-27 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5239638A JPH0794668A (en) 1993-09-27 1993-09-27 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0794668A true JPH0794668A (en) 1995-04-07

Family

ID=17047695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5239638A Pending JPH0794668A (en) 1993-09-27 1993-09-27 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0794668A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07153903A (en) * 1993-11-29 1995-06-16 Nec Corp Semiconductor device package
KR100290445B1 (en) * 1998-09-03 2001-06-01 윤종용 Memory module and socket for same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07153903A (en) * 1993-11-29 1995-06-16 Nec Corp Semiconductor device package
KR100290445B1 (en) * 1998-09-03 2001-06-01 윤종용 Memory module and socket for same

Similar Documents

Publication Publication Date Title
US6501157B1 (en) Substrate for accepting wire bonded or flip-chip components
US6841855B2 (en) Electronic package having a flexible substrate with ends connected to one another
JP3499202B2 (en) Method for manufacturing semiconductor device
CA1078071A (en) Integrated circuit package
US5949135A (en) Module mounted with semiconductor device
US6198162B1 (en) Method and apparatus for a chip-on-board semiconductor module
JPS582054A (en) Semiconductor device
CN100492638C (en) Stack package of semiconductor device
JP3898350B2 (en) Semiconductor device
JPH05335695A (en) Single in-line module
US20060138630A1 (en) Stacked ball grid array packages
JPH0794668A (en) Integrated circuit device
US20030043650A1 (en) Multilayered memory device
CN110402022B (en) PCB and terminal
JP2715767B2 (en) Flex-rigid board
JP2837521B2 (en) Semiconductor integrated circuit device and wiring change method thereof
JP2738232B2 (en) Printed board
JPH01183196A (en) Manufacture of multilayer printed wiring board device
JPH0828395B2 (en) Flexible circuit board and liquid crystal display device
KR940006872Y1 (en) Circuit Board Structure of Multi Chip Module
JPH0661404A (en) Semiconductor device
JPH01183195A (en) Manufacture of multilayer printed wiring board device
JPH0645763A (en) Printed wiring board
JPH1146053A (en) Package structure of electronic component
KR100206975B1 (en) Semiconductor package