JPH0793720B2 - One-way data communication receiver - Google Patents

Abstract

According to this invention, a field of useful data is split into a number of basic entities, called "data groups". Each data group is, in turn, split into smaller basic entities or "data blocks". Each resulting data block is inserted in a data packet to be transmitted through a teletext or videotext network. Therefore, an input coupler has two functional parts: a data group generator and a data packet generator.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a one-way data communication scheme of the DIDON system type disclosed in US Pat. No. 4,058,830. This Daedon system is further described in U.S. Patent Nos. 4,115,662 and 4,317,132.
And United States Patent Application No. 189,080 (September 1980)
No. 376,790 (filed on May 10, 1982) and filed on May 22, 1982.

This type of one-way data communication system of the Daidon system,
It includes a transmitting station that transmits digital data supplied from a plurality of channels in the form of data packets. The maximum duration of each data packet is 1 of the television image.
Equal to scanline duration. Such data packets are typically used during the line sync signal of a television,
It is inserted instead of the image or following the flyback line in the field.

Upon transmission, each data packet begins with a prefix. The prefix portion includes a sync signal for bits or bytes, a channel designation code signal, and a packet type signal that represents the length of the data following the prefix portion. In each packet, the front part and the valid data following it are formed of bytes. Thus, the packet format signal is a byte that represents the number of valid data bytes that follow the prefix.

In this one-way data communication system of the Daddon system, the clarity of the transmitted digital data has so far been determined at the data packet stage. This is partly because it uses packets to regulate the flow of data. That is, the data packet is represented in byte format and has a length of 32 to 40 bytes. The 9th byte and below represent information for each data packet. The eighth byte represents the number of the last byte that represents such information. The other is because the Daedon system conforms to the television standard.

However, the stage of this data packet depends on the electrical properties of the propagation medium. That is, if the television standard does not allow 32 to 40 bytes of data packets,
For example, when using the PAL or NTSC (NTSC) system instead of the French television standard, the clarity of the data communication system is impaired.
In the one-way data communication system according to the invention of this application, the clarity of the data communication system is not secured at the data packet stage, but is secured at a new stage of “data group”. In addition to using such data group steps, ensuring intelligibility does not depend on the electrical properties of the propagation medium, and that the size of these data groups can be different. , Allows you to:

Being able to multiplex digital data of different natures into one digital channel. here,
These digital data are commonly used by being transmitted according to the electrical characteristics of the propagation medium, and are, for example, a certain number of data groups for systematically repeating and transmitting to cope with transmission errors. .

Being able to multiplex digital data of different natures into one digital channel. These digital data are used to switch between the specific processing circuits of the receiver.

To enable the use of specific data groups for encryption in the transmission of valid digital data. This encryption ensures that only certain subscribers of the Daddon system can use their encrypted digital data.

According to the first feature of the present invention, the following receiver used in the one-way data communication system can be obtained.

A data group broadcast in a one-way data communication system, each representing digital data from a data source by a data group each consisting of a series of data blocks forming a field of a data packet, represents the first of each of these data groups. The data block contains a byte that specifies the format of the data group, a group continuity indicator byte, a byte that indicates the number of data blocks that the data group contains following the first data block, and a last byte of the data group. A group header consisting of bytes indicating the size of the data block is provided, and in addition to the synchronization signal and the channel designation code signal, the data packet continuity indicating signal, the data packet structure information, and the data block of this data packet in the data group. the first A data packet having a front part including information indicating whether or not it is a data block is received in each data block, and a demodulator circuit, a data acquisition device, a peripheral device, a microprocessor, and a program memory connected to the bus are received. In a receiver provided, the data acquisition device includes a group and packet processing circuit including a data packet processing circuit and a data group management circuit and connected to the demodulator circuit, and the data packet processing circuit includes a first input circuit. And a main memory that stores each of the incoming data packets that is the output of this input circuit, and the number of bytes that form the incoming data packet are counted, and the output of the input circuit is output each time this count reaches a predetermined value. Means for stopping and data packets stored in the main memory Means for confirming the data continuity instruction signal and the data packet continuity information, and an AND circuit for supplying the data blocks stored in the main memory to the input terminal and passing these supplied data blocks from the first data block. A one-way data communication type receiver comprising a block memory in which the output of the AND circuit is stored, and means for outputting the output of the block memory.

According to the second feature of the present invention, the following receiver can be obtained.

A data group management circuit includes a second input circuit, a detection circuit that detects from the output of the input circuit whether or not a byte designating the format of the data group matches a predetermined byte, and a third input circuit. A group header memory for storing the output of the input circuit; a fourth input circuit; a data group memory for storing the output of the input circuit; an output circuit for outputting the output of the data group memory; A byte counter that counts the number of bytes forming an incoming data group with output terminals connected to the third input circuit and the fourth input circuit, and a group continuity index byte that is supplied with the output of the group header memory. Analyzing means for analyzing, wherein the detection circuit is configured such that the byte designating the format of the data group matches a predetermined byte. If the third input circuit is detected, the third input circuit is activated, and the third and fourth input circuits are activated by the count value counted by the byte counter as long as the analyzing unit analyzes that the group continuity index byte is correct. The one-way data communication type receiver described in the first feature described above that sequentially operates.

According to the third feature of the present invention, the following receiver can be obtained.

The one-way data communication type receiver according to the second feature, further comprising a decoding circuit controlled by a decoding control interface between the fourth input circuit and the data block memory.

According to the fourth feature of the present invention, the following receiver can be obtained.

The output of the detection circuit is supplied to a gate circuit which activates the byte counter when detecting that the byte designating the format of the data group matches the predetermined byte. The one-way data communication type receiver described in.

Next, an embodiment of the present invention will be described with reference to the drawings. This embodiment is a case where the present invention is applied to a one-way data communication system of the type of Daddon system and broadcast from a data file. .

Referring to FIG. 1, this embodiment includes a transmitter station with a database 1 and a transmitter 2 of the Daddon system type that can also transmit video programs from a data source 3. Each of the receivers 5 connected to the television broadcasting network 4 includes a reception antenna 6, a video signal demodulation circuit unit, a data acquisition circuit, and a peripheral device for interaction, which will be described later.

The transmitter 2 is for adapting the information supplied from the database 1 to the broadcast network 4, and has the following two other functions.

It generates so-called access message information for the encoded and transmitted data.

It generates real-time date and time information for resynchronizing the clocks contained in the receiver 5.

As shown in FIG. 2, the transmitter 2 is the node of this data communication system, and the output signal from any of the data sources such as the database 1 is supplied as an input signal to the transmitter 2, and As the output signal, the output signal from the modulator 10 is supplied to the broadcasting network 4. The video program from data source 3 is also provided to modulator 10. The broadcasting network 4 is generally a highway main network, and is for broadcasting digital data based on the Daedon standard improved by the present invention.

The components of the transmitter 2 are interconnected by a standard bus (BUS) 11 and include the following interfaces. That is, an input coupler 12, a central processor (central processing unit) 13, a multiplexing circuit (multiplex communication circuit) 14, the modulator 10, a digital clock (clock) circuit 15, an operating device 16,
And a program memory 19 which is an aprom (erasable program memory). In the example shown,
The transmitter 2 is an input coupler 12 connected to the database 1.
There is only one.

The input coupler 12 manages data groups including a date and time data group, an access message data group, and a file data group, and processes the digital data for the Daddon type one-way data communication system. Although the structure and operation of the input coupler 12 will be described later, it should be noted here that the information exchange between the input coupler 12 and the multiplexing circuit 14 is performed for each data packet.

The central processor 13 receives a connection with the operating device 16, manages the scanning of the input couplers 12 when a plurality of input couplers 12 and others are included, and multiplexes a circuit 14 to determine where to send the data packet. Instruct. Also,
At the start of the operation of this one-way data communication system, the central processor 13 synchronizes the entire system.

The multiplexing circuit 14 is supplied with the data packets formed in the input coupler 12 and is responsible for sending them out. Therefore, the multiplexing circuit 14 is used as a passive circuit, each of which is a simple memory consisting of a plurality of pages containing data packets, as a direct access circuit to the pages from a plurality of input couplers, for a transmission window or data transmission. Acts as a supervisory circuit for the reserved video channel.

The modulator 10 shapes digital data and inserts the shaped digital data into a video signal of a television channel corresponding to a transmission window.

The digital clock circuit 15 is realized by a card called a "clock card" and supplies the real-time date and time data group created in the central processor 13.

The operating device 16 performs operations such as switching on the transmitter 2, generally initializing, synchronizing date and time, and the like.

In the present invention, valid digital data from the database 1 is divided into the above data groups, and each data group is divided into the above data blocks. Then, each data block is inserted into one data packet and sent out to the broadcasting network 4. Therefore, the input coupler 12 comprises a data group generator 17 detailed in FIG. 3 and a data packet generator 18 detailed in FIG.

Referring to FIG. 3, in the data group generator 17, the digital data from the database 1 (FIGS. 1 and 2) is sent through the type input junction J1 disclosed in French Patent 2,268,308. .
Junction J1 is eight wires 20 that send the bytes in parallel
Consisting of one of these 20 wires DOP
The signal level at represents the presence or absence of digital data from database 1. Another wire PA
The signal level at R represents whether the input coupler 12 is ready to receive digital data. The junction J1 is connected to the input terminal of the first logic circuit CL1, and the output terminal of this circuit CL1 is connected to the second logic circuit CL2 and the first byte register R1. First
There is a control terminal in the logic circuit CL1 of
An on / off command is supplied from the operating device 16 (FIG. 2) via The wire DOP indicates a change in the state of the byte supplied from the database 1, and is connected to one of the input terminals of the AND circuit P1 whose output terminal is connected to the input terminal of the first counter C1. ing. The first byte register R1 is reset by the reset command RAZ sent via the bus 11 and the connection line 37, and its output terminal is connected to the first input terminal of the first digital comparison circuit CN1. The output terminal of the first memory M1 is connected to the second input terminal of this circuit CN1. This memory
In M1, the designated binary-coded designated byte at the head of the file data group sent from the database 1 is stored. This memory M1 is connected to the central processor 13 (FIG. 2) via the bus 11 and the connecting line 38, and the stored contents are changed. The output terminal of the memory M1 is connected to the second input terminal of the first digital comparison circuit CN1, and this circuit C
The output terminal of N1 is connected to the second input terminal of the AND circuit P1 and the control terminal of the second logic circuit CL2.
When it is detected that the designated byte is stored in the memory M1 during processing of the flow of digital data sent from the first logic circuit CL1, the first digital comparison circuit CN1 generates an output signal and The logic circuit CL2 is activated and the AND circuit P1 is opened.

The output terminal of the second logic circuit CL2 is connected to the first input terminal of the exclusive OR circuit CEX which is the adder circuit of modulo 2, and the output terminal of this circuit CEX is connected to the input terminal of the main memory MG. . The second byte register R2 connected to the output terminal of the first counter C1 stores the number of bytes sent from the second logic circuit CL2 to the main memory MG. The second byte register R2 is connected to the bus 11 and the connecting line 39.
It is reset to zero by the reset command RAZ sent via the register R2, and the output terminal of the register R2 is connected to the first input terminal of the second digital comparison circuit CN2. Third
The logic circuit CL3 calculates the maximum number of valid bytes in each data group as described below. The output terminal of this circuit CL3 is the second input terminal of the digital comparison circuit CN2. It is connected to the.
The second logic circuit CL3 is sent via the bus 11 and the connecting lines 4 and 41, respectively, and represents the number of bytes in the data group, ie the "maximum group size" TMG.
And another piece of information, the "maximum block size" TMB. Second digital comparison circuit
The output terminal of CN2 is connected to the stop input terminal of the second logic circuit CL2 and the input terminal of the fifth (fourth will be described later) logic circuit CL5. Since the first input terminal of this circuit CL5 is connected to the output terminal of the second byte register R2, said input terminal will be referred to as the second input terminal of the circuit CL5 in some cases. When the content of the second byte register R2 becomes equal to the content of the third logic circuit CL3, the comparison circuit CN2 stops the operation of the second logic circuit CL2 and prevents the digital data from being supplied to the main memory MG.

The main memory MG consists of two parts: the first part EG stores the bytes of the group header of each data group and the second part GD contains the first and second logic circuits CL1 and CL2. Data bytes from database 1 are stored. The first portion EG has first to sixth input terminals E11 to E16 described below.

The first input terminal E11 is connected to the output terminal of the second memory M2. The contents of this memory M2 are bus 11 and connection line 42.
It is a data group forming byte TG of 1 byte that "specifies the type of group" and is changed by the central processor 13 via the. This byte TG is the receiver 5 (Fig. 1)
It also specifies which particular processing circuit of the receiver 5 to which the group header should be supplied, i.e. the processing carried out in the receiver 5 of this embodiment is carried out on four different data groups. . The first group of data is formed in the central processor 13 and represents real-time date and time information. Second
Data groups are also formed in the central processor 13, which represent access message information and are used to encode the information contained in the file data. The data groups of FIGS. 3 and 4 represent information about file data that is either encoded or uncoded. According to the information represented by this byte TG, it must be sent through one channel and sent to different processing circuits (date and time processing circuit, message information processing circuit, and file information processing circuit) of the receiver 5. Distinguish between different data groups that have different properties. In this embodiment, it is assumed that the digital data sent from the database 1 and stored in the main memory MG is encoded. The exclusive blue circuit CEX is for that purpose, and the second input terminal of this circuit CEX is connected to a coded byte generator GOC21, which is not the subject of the present invention. Which is described in French patent application No. 2,448,825.

The second input terminal E12 is connected to the output terminal of a second counter C2 which contains a data group continuity indicator byte C which serves as a "group continuity index". This data group continuity indication byte C is the type byte of the data group
This is because TG indicates that a common data group continues, and this byte C represents a number from 0 to 15, and 1 is sent modulo 16 for each data group of the same type byte sent. It gets bigger and bigger. The input terminal of this counter C2 is from the central processor 13 to the bus 11
And the signal PAG which is sent via the connection line 44 according to each data group. This counter C2
The output terminal of is connected to the second input terminal E12.

Before describing the third input terminal E13, the following will be described. The third counter CR3 has a reset terminal connected to the connection line 43, the output terminal of the counter CR3 is connected to the first input terminal of the third digital comparison circuit CN3, and the input terminal is connected by the connection line 44. Connected to bus 11. The second input terminal of this circuit CN3 is the third memory M
It is connected to the output terminal of 3 and the output terminal of this circuit CN3 is the 4th
Is connected to the control terminal of the logic circuit CL4 and the reset terminal. When the content of the counter CR3 becomes equal to the content of the memory M3, the signal from the comparison circuit CN3 stops the operation of the logic circuit CL4 and becomes the reset signal RAZ of the counter CR3. The content of the memory M3 is changed by the connection line 45 connected to the bus 11.

The connection line 44 is also connected to the input terminal of the up / down counter C3, and the initialization terminal of this counter C3 is connected to the output terminal of the comparison circuit CN3. Each time a data group is repeatedly sent, the "data group repeat index", ie, the byte R, which is the content of the counter C3, decreases, but this content is supplied to the third input terminal E13 of the first portion EG of the main memory MG. It

In practice, this repeat index byte R represents the number of remaining data groups to send repeatedly. By using this byte R, it is possible to repeatedly transmit information that tends to cause a transmission error. For example, the access message information is sent twice (that is, three times). By doing so, it is possible to prevent the access message information from being mistaken for transmission and the data file being missing and becoming unreadable. In this way, the byte R keeps the transmission characteristic at the time of transmission at a required residual error rate characteristic, and it is possible to secure necessary information and a propagation state of a signal representing the information.

The fourth input terminal E14 is connected to the first output terminal S1 of the fifth logic circuit CL5. The first input terminal E1 of this circuit CL5 is connected to the output terminal of the second byte register R2,
The input terminal E2 of is connected to the output terminal of the second digital comparison circuit CN2. Due to the information supplied from these circuit elements R2 and CN2, this circuit CL5 has two bytes T1 and T2 representing the "data group size" at the first output terminal S1.
The signal of is output. For more information, see these bytes T1 and T2
Represents the number of data blocks following the first data block in one data group and varies from 0 to 225. The length of a data group varies according to the information it represents, but can be represented in this way. For example, in a date and time data group, the group header followed by the valid date and time information is represented by one data block sent as one packet, so the bytes T1 and
T2 represents zero. The maximum length of a data group representing a data file is 11 data blocks.

The fifth input terminal 15 is connected to the second input terminal S2 of the fifth logic circuit CL5. A signal of 2 bytes F1 and F2 indicating the "size of the last data block", that is, the number of bytes of the last data block of one data group is output to the output terminal S2. For example, if the field of a certain message information is 46 bytes, the data group representing this is two data blocks, and the data group size bytes T1 and T2 represent one. Since the maximum length of the data block is 30 bytes and the group header is 8 bytes, the length of the last or second data block in this data group is 24 bytes which is represented by bytes F1 and F2. .

The sixth input terminal E16 is connected to the output terminal of the fourth memory M4, in which the byte N representing "information of the path of the data group" is stored. The byte N determines the route of the broadcasting network 4 (Figs. 1 and 2) when transmitting a data group including this, and is represented by a number from 0 to 15, and such a route is shown in the figure. It is decided in consideration of the transmission time by the clock measuring device which is not available. Typically, the byte N is not used in the receiver 5 but is used in a relay station (not shown). This byte N is limited to this description.

The fifth logic circuit CL5 has a third input terminal E3
It receives information on the maximum packet size sent from the central processor 13 via 1 and connection 46.

The data input terminal of the fourth logic circuit CL4 is connected to the read output terminal of the main memory MG, and the output terminal is connected to the output junction J2 having the same configuration as the input junction J1. This junction J2 consists of eight wires 25 for wire parallel feed and wires PAR and DOP.

When the signal PAG is supplied via the connection line 44 and the reset signal RAZ is supplied via the connection line 43 at the same time, the third counter CR3 is reset, so that the output signal of the third digital comparison circuit CN3 becomes high level. 4 logic circuit CL4 is operated.
This circuit CL4 reads the contents of the main memory MG and
Send to output junction J2 according to known protocol given by signals at AR and DOP. After repeating the data group a specified number of times,
Since the count of the up / down counter C3 and the contents of the third memory M3 become equal and the output signal of the comparison circuit CN3 becomes low level, the operation of the logic circuit CL4 is stopped. During the final iteration, the central processor 13 applies the reset signal RAZ to the byte registers R1 and R2 on the connecting lines 37 and 39.
And send each. The central processor 13 then sends an operating command to the first logic circuit CL1 via the connecting line 36, so that the main memory MG stores information about the next data group.

Referring to FIG. 4, in the data packet generator 18, the input terminal of the sixth logic circuit CL6 is connected to the output junction J2 which is now the input junction, and the output terminal is a buffer memory for storing one data packet. Connected to write input pin of MP. This circuit CL
6 is a central processor 13 via a bus 11 and a connecting line 26.
The operation command from (FIG. 2) is received. Junction J2
The wire DOP for transmitting the state change for each byte from the fourth logic circuit CL4 is connected to the input terminal of the byte counter, that is, the fourth counter C4. The fourth byte register R4 whose input terminal is connected to the output terminal of the counter C4 is connected to the buffer memory MP from the logic circuit CL6.
Stores the number of bytes sent to. The reset terminal of the register R4 receives the reset signal RAZ from the connection line 27, and the output terminal is connected to the first input terminal of the fourth digital comparison circuit CN4.

The buffer memory MP comprises first to third parts EP, BD and S. The first part EP stores the group header in the packet, and the second part BD stores the logic circuit.
What stores the data bytes from CL6, the third part S
Stores the later-described post-part of the packet.

The first part EP has first to sixth input terminals E21 to E21.
There are 26. The fifth memory M5, whose output terminal is connected to the first input terminal E21, is the byte synchronization signal, which is the two bytes R1 and R2 which are the bit synchronization signal R (using the same symbols as the above-mentioned repetition index byte R). 1 byte B is stored via bus 11 and connection 28.

The second input terminal E22 is connected to the output terminal of a sixth memory M6 which stores 3 bytes A1, A2 and A3 encoded by a Hamming code and indicating the address of a data packet. This memory M6 is connected to the bus 11 by a connecting line 29.

The third input terminal E23 is connected to the output terminal of the fifth counter C5, which is also called the packet counter. The counter C5 has an input terminal connected to the bus 11 by a connection line 34, and outputs from the above output terminal a 1-byte IC which is encoded by a Hamming code and indicates the number of data packets, that is, packet continuity. This byte IC starts from 0
It changes up to 15, and modulo 16 adds 1 to each data packet sent to the same channel.

The fourth input terminal E24 is connected to the output terminal of the first latch B1 whose reset input terminal is connected to the bus 11 via the connection line 30 and whose signal input terminal is connected to the bus 11 via the connection line 31. This latch B1 is set to 1 if the data block being sent contains a group header, otherwise it is set to 0.

The fifth input terminal E25 is a second latch B whose signal input terminal is connected to the output terminal of the digital comparison circuit CN4 described above.
Connected to 2 output terminals. The comparison circuit CN4 has a first input terminal connected to the output terminal of the fourth byte register R4 for counting the number of bytes sent from the sixth logic circuit CL6, and a second input terminal connected to the seventh input terminal. It is connected to the output terminal of the memory M7. The memory M7 has an input terminal connected to the bus 11 by a connection line 46, and has the maximum number of bytes in one data block (in this embodiment,
Remember 30). The latch B2 has a reset terminal connected to the bus 11 by a connection line 32.

The sixth input terminal E26 is connected to the output terminal of the eighth memory M8 whose input terminal is connected to the bus 11 by the connecting line 33. The size of the trailing part included at the end of the data packet is stored in this memory M8.

In this way, these input terminals E24 to E26 are the bytes SP indicating the structural information of the packet, that is, the byte that is encoded by the Hamming code and that distinguishes the synchronization data packet at the beginning of the data group from other data packets. Memorize This byte SP further indicates whether or not the data packet is filled with information bytes and indicates the size of the trailing part for detecting and correcting transmission errors in the data block. The even-numbered bits of the byte SP have the following meanings.

When the second bid b2 is 0, it is a standard packet, and when it is 1, it is a synchronization packet. When the fourth bid b4 is 0 and 1, the packet is filled and unfilled with the information bid, respectively. When the 6th and 8th bids are originally 0, it should not be a trailing part. If these are 1 and 0 respectively, the trailing part shall be 1 byte. When 0 and 1 respectively, the trailing part is 2 bytes. If both are 1, the trailing part must be 3 bytes.

The output terminal of the fourth comparison circuit CN4 is also connected to the control terminal of the sixth logic circuit CL6. When the number of bytes stored in the fourth byte register R4 becomes equal to the content of the seventh memory M7, the operation of the sixth logic circuit CL6 is stopped. However, when the packet is filled with information bytes, the output signal of the fourth comparison circuit CN4 is also used to generate the trailing bytes. That is, this output signal activates the post-part logic circuit CSU whose start input terminal is connected to the output terminal of the comparator circuit CN4 and whose output terminal is connected to the third part S of the buffer memory MP to activate the post-part. Let me calculate. In the present invention, the trailing part is always included at the end of the data packet, and the number of bytes of the data block of the data packet is equal to the number of bytes represented by the sixth and eighth bids of the packet structure byte SP. decrease. In this embodiment, the data block comprises a number of bytes up to 30 bytes and the size of the trailing part is 2 bytes.

The input coupler 12 (FIG. 2) includes a transmission simulator (not shown). This simulator is described in the above-mentioned United States Patent No. 4,058,830, by simulating the sending from the buffer memory MP,
The buffer memory MP prevents the receiver 5 (FIG. 1) from being unable to process because it sends out a series of data packets too quickly.

The output terminal of the buffer memory MP is connected to the transmission logic circuit CL7. The clock input terminal of this circuit CL7 is connected to the output terminal of a clock circuit H whose initialization input terminal M is connected to the bus 11 and which outputs the bid frequency signal FB, and the control terminal is connected to the bus 11 via a connection line 34. Central processor
In response to the supply of the command OEP from 13 (FIG. 2), the output terminal is connected to the bus 11 by the connection line 35. The connection line 34 is also connected to the input terminal of the counter C5, and the number of data packets sent from the input coupler 12 through the multiplexing circuit 14 (FIG. 2) is transferred to the counter C5 according to the instruction OPE from the central processor 13. Let me calculate. The logic circuit CL7 sends out a data packet byte by byte from the buffer memory MP to the multiplexing circuit 14 via the connection line 35 and the bus 11.

In FIG. 2, the data packet from the multiplexing circuit 14 is sent to the modulator 10 for each bid and becomes digital data. Preferably, the modulator 10 is the one described in U.S. Pat. No. 4,058,830.

In FIG. 1, the digital data inserted in the video signal is transmitted to the broadcasting network 4 as data information. The digital information broadcast in this way is received by the plurality of receivers 5. In this example,
All the receivers 5 are for acquiring the transmitted data file and using it by a peripheral device.

Referring to FIG. 5, each receiver 5 has an antenna 6
And a communication terminal 9 as a peripheral device. The demodulation device 7 includes a television receiving circuit 50 and a Daddon system circuit 51 including a demodulator and a demultiplexer. The program interface 52 is a television receiver circuit 50 and a demodulator and demultiplexer circuit 51.
Is common to. The clock circuit 53 having a crystal oscillator is for checking the validity of the data file. The Rydam access memory (RAM) 54 has a memory capacity for storing all the data files received. The group and packet processing circuit 55 processes data groups and data packets and will be described in detail later. Microprocessor 56 controls group and packet processing circuitry 55 as described below. The aprom 90 is for the software of the microprocessor 56. The decoding control interface 57 is used for decoding the transmitted digital data. The call terminal 9 is used for using the data files stored in the random access memory 54. The bus (BUS) 11 is connected as shown.

Television receiver circuit 50 is tuned to the desired television channel and outputs an output video signal containing digital data represented by a number of horizontal scan lines. This signal is sent to the demodulator and demultiplexer circuit 51. In this circuit 51, the digital data is decoded, that is, the digital data inserted in the video signal is extracted.

Separation of multiplexed digital data, that is, separation of digital data corresponding to a digital channel designated by three bytes A1, A2, and A3 indicating an address of digital data. In this way, the demodulator and demultiplexer circuit 51 outputs a data block including the packet continuity instruction byte IC, the packet structure byte SP, and the trailing portion.

The television receiver circuit 50 is known. A Daddon system circuit 51 consisting of a demodulator and a demultiplexer is described in the aforementioned U.S. Pat. No. 4,058,830. Therefore, the part that processes and manages data groups and data packets is described below. This group and packet processing circuit 55 has a sixth
The data packet processing circuit 58 shown in the figure and the data group management circuit 59 shown in FIG. 7 are provided.

Referring to FIG. 6, in the data packet processing circuit 58, the demodulator and demultiplexer circuit 51
The digital data from is input to the eighth (serial number from that at the transmitting station) logic circuit CL8 at junction J3.
Will be supplied via. The control terminal of this circuit CL8 is connected to the bus 11 via the connecting line 60, and the output terminal is the main memory MP.
It is connected to T. In this embodiment, the main memory M
The PT has a memory capacity of 34 bytes and stores other data packets of bit and byte sync bytes and 3 bytes indicating the address of digital data. Junction
The wire DOP of J3 is connected to the input terminal of the sixth counter C6, and the output terminal of the counter C6 is connected to the fifth byte register R5. The register R5 has a reset terminal connected to the bus 11 by a connection line 61, and is initialized by a reset signal RAZ from the microprocessor 56 (FIG. 5) every time one data packet is received. The output terminal of the register R5 is connected to the first input terminal of the fifth digital comparison circuit CN5. The second input terminal of the circuit CN5 is connected to the output terminal of the ninth memory M9 that stores the maximum size of the data packet, that is, the above 34 bytes, and the output terminal is connected to the inhibit input terminal of the logic circuit CL8. When the content of register R5 becomes equal to the content of memory M9, the comparison circuit CN5
Since the operation of the logic circuit CL8 is stopped, the storage in the main memory MPT is also stopped.

The main memory MPT comprises first to third parts PT, BD and S. As described below, the first part PT has a packet continuity instruction byte IC and a 3-byte SP indicating the packet structure.
Are stored, the second portion BD stores a data block, and the third portion S stores a trailing portion of 2 bytes.

The packet continuity instruction byte IC is sent to the first Hamming correction circuit CM1 from the first output terminal S21 of the first portion PT. When this byte IC is supplied, the correction circuit CM1
The instruction information I consisting of 4 bits is sent to the first output terminal, and the signal EM1 indicating an error in the information I is sent to the second output terminal. The first output terminal of the correction circuit CM1 is connected to the input terminal of a sixth register R6 which stores a valid instruction byte. The tenth memory M10 connected to the second input terminal of the sixth digital comparison circuit CN6, whose first input terminal is connected to the output terminal of the register R6, stores the data packet that should have been output now. Store the continuity indicator byte. Information EM1 indicating an error from the correction circuit CM1 is supplied to the bus 11 via a connection line 62, and the instruction information I is supplied to the bus 11 via a connection line 63. The instruction byte is supplied from the microprocessor 56 to the input terminal of the memory M10 via the bus 11 and the connection line 64. The output terminal of the comparator circuit CN6 is connected to the bus 11 by a connecting line 65 and outputs a signal D1 indicating that the packet has lost continuity to the microprocessor 56 unless the contents of the register R6 and the contents of the memory M10 are equal. . Using this signal D1 as an alarm signal, the microprocessor 56 manages the data group.

From the first output terminal of the second Hamming correction circuit CM2 connected to the second output terminal 22 of the first portion PT, the second, fourth, and sixth bytes SP indicating the structure information of the data packet are output.
And 8 bits are output as a 4-bit signal SP, and the second
An error signal EMSP representing an error in the 4-bit signal SP is output from the output terminal of. These have their first and second output terminals connected to the bus 11 by connection lines 66 and 67.
The second bit of the 4-bit signal SP supplied to the microprocessor 56 indicates, as described above, whether the data packet including this bit is a packet for synchronization.

The error detection / correction circuit CDC connected to the read terminals of the second and third portions BD and S of the main memory MPT is a circuit for detecting and correcting an error in the data block, and its control output terminal is connected to the bus 11. Connected by line 68,
The data output terminal is connected to the first input terminal of the AND circuit P2, and the control input terminal is connected to the bus 11 by the connecting line 69. The second input terminal of the AND circuit P2 is connected to the bus 11 by the connecting line 70
The output terminal is connected to the input terminal of the block memory BDC.

The data packet is for synchronization and the second bit b2 is 1.
Until it is found in the stream of data packets coming from the eighth logic circuit CL8, the microprocessor 56 is not supplied with the 4-bit signal SP from the connection line 66 and the AND circuit P2 is never closed via connecting line 70. Therefore, the first data block stored in the block memory BDC is guaranteed to have the data block corresponding to the data packet for synchronization.

On the other hand, the bytes stored in the second and third parts of the main memory MPT are read and processed by the error detection / correction circuit CDC, and the error detection signal EMD supplied to the connection line 68 is processed by the microprocessor 56. Data group errors are corrected. After the error correction is completed by the error detection / correction circuit CDC, the bytes of the data block are stored in the block memory BDC.

The capacity of the memory BDC is one data block, that is, 30 bytes in this embodiment. The microprocessor 69 is connected to the connection line 69 to the error detection / correction circuit CDC.
From 6, a signal indicating the size of the data block to be sent to the block memory BDC is supplied.

The output terminal of the ninth logic circuit CL9, whose input terminal is connected to the output terminal of the block memory BDC, is the output junction J.
Connect to 4. When the block memory BDC is full, the circuit CL9 sends the digital data byte by byte to the data group management circuit 59 (Fig. 5) via the junction J4. Information is exchanged by wires PAR and DOP.
In the seventh counter C7 whose input terminal is connected to the wire DOP of the junction J4, the reset terminal is connected to the bus 11 by the connection line 71, and the output terminal is connected to the seventh register R7. Counter for each byte sent out
The count of C7 is incremented and sent to register R7. The eleventh memory whose input terminal is connected to the bus 11 by the connecting line 72 is the second input terminal of the seventh digital comparison circuit CN7 whose output terminal of the register R7 is connected to the first input terminal. M11
Output terminal of is connected. The reset terminal of the register R7 is connected to the bus 11 by the connection line 73. The output terminal of the comparator circuit CN7 is connected to the inhibit input terminal of the logic circuit CL9. 7th
When the content of the register R7 becomes equal to the content of the eleventh memory M11, the output of the comparison circuit CN7 stops the operation of the logic circuit CL9 and stops the digital data from being sent to the data group management circuit 59 via the junction J4.

Referring to FIG. 7, in the data group management circuit 59, the tenth logic circuit CL10 connected to the junction J4, which is now the input junction, is connected to the bus 11 by the connection line 74, and the microprocessor 56 (the fifth circuit). (Figure) receives the start command. In this circuit CL10, the output terminal is connected to the input terminal of the Hamming correction circuit CH3 and the output terminal is the first
Connected to the input terminals of the 1st and 12th logic circuits CL11 and CL12. The Hamming correction circuit CH3 includes a second register R8 having an input terminal connected to a first output terminal thereof, and a second byte of the first byte of the first data block.
Supplies bits b2, b4, b6, and b8. A twelfth memory M12 for storing a byte TG designating the format of the data group is provided at a second input terminal of the eighth digital comparison circuit CN8 having the first input terminal connected to the output terminal of the register R8.
Connect the output terminal of. The reset terminal of register R8 and the input terminal of memory M12 are connected to bus 11 by lines 75 and 76.
Connected by. The second output terminal of the Hamming correction circuit CH3 is connected to the bus 11 by a connection line 77. Junction
The output terminal of the AND circuit P3 whose first input terminal is connected to the wire DOP of J4 is connected to the input terminal of the eighth counter C8. The output terminal of the comparison circuit CN8 is connected to the enable input terminal of the eleventh logic circuit CL11 and the first input terminal of another AND circuit P4. The output terminal of the AND circuit is connected to the second input terminal of the AND circuit P3. The output terminal of the counter C8 is connected to the inhibition input terminal of the eleventh logic circuit CL11 and the activation input terminal of the twelfth logic circuit CL12.

Let the incoming data group represent the encoded data of the output of the data file. If a byte specifying the format of such a data group is detected, the 8th
The comparator circuit CN8 activates the eleventh logic circuit CL11 and is supplied with the second byte or less of the first data block from the tenth logic circuit CL10.

The AND circuit P4 is currently ready to open with its second input terminal connected to the bus 11 by a connecting line 78. 8th
When the output of the digital comparison circuit CN8 becomes high level, the AND circuit P4 is opened, and the AND circuit P3 is opened in cooperation with the signal on the wire DOP of the junction J4.

Eighth counter connected to the output terminal of AND circuit P3
Before the operation of the eleventh logic circuit CL11 stops after the count of C8 reaches 9, the second to eighth bytes of the group header included in the first data group are input to the output terminal of this circuit CL11. Is sent to the Hamming correction circuit CH4 to which is connected. In this circuit CH4, the group header whose input terminal is connected to its first output terminal is a memory MEG.
Send these bytes to. The Hamming correction circuit CH4 is the second
Is connected to bus 11 on connection 79 to convey to the microprocessor 56 an error EM in each byte of the group header.

The first information stored in the group header memory MEG is the data group continuity indication byte C. The header memory MEC has first to fifth output lines S31 to S35 for outputting the information C, R, T1, T2, F1, F2 and N.

The second input terminal of the ninth digital comparison circuit CN9, to which the first output line 31 is connected to the first input terminal, stores the data group continuity instruction byte C which should have been output now. It is connected to the output terminal of memory M13. The input terminal of the memory M13 and the output terminal of the ninth digital comparison circuit CN9 are connected to the bus 11 by connection lines 80 and 81. Compared with the continuity indication byte C from the header memory MEG and the contents of the memory M13, if they are not equal, the comparison circuit CN9 connects the microprocessor 5 via the connecting line 81.
6 is supplied with the group continuity byte discontinuity signal DC.

The second input terminal of the tenth digital comparison circuit CN10 having the first input terminal connected to the second output line S32 of the group header memory MEG has the input terminal connected to the bus 11 by the connection line 82. It is connected to the output terminal of the 14th memory M14. The output terminal of the comparison circuit CN10 is connected to the bus 11 by a connection line 83. The group repeat byte R is output to the output line S32, and the memory M14 in the comparison circuit CN10.
It can be compared with the contents of. If these values are not equal, the comparison circuit CN10 sends to the microprocessor 56 a signal DR indicating the discontinuity of the group repeat bytes.

When the count of the eighth counter C8 reaches 9, the part of the data group excluding the group header is sent to the twelfth logic circuit CL12. The reset terminal of the counter C8 is connected to the bus 11 by the connection line 84. In the twelfth logic circuit CL12, the second input terminal of the exclusive OR circuit CEX having the inhibit input terminal connected to the bus 11 by the connection line 85 and the first input terminal connected to the output terminal thereof is the bus 11 Connected to wire 8
It is connected to the output terminal of the encoded byte generator GOC to which the input terminal is connected by 6. The content of this generator GOC is
It is connected to the interface 57 (Fig. 5). The output terminal of the exclusive OR circuit CEX is a data group memory MGD.
Connected to the input terminal of.

Above, it was assumed that the digital data was encoded.
The data output from the twelfth logic circuit CL12 is input to the exclusive OR circuit CEX. This circuit CEX decodes these data at the output of the coded byte generator GOC. The decrypted data is stored in the memory MGD. When the signal sent from the microprocessor 56 via the bus 11 and the connection line 85 stops the operation of the twelfth logic circuit CL12, the accumulation in the memory MGD stops. This signal represents the data group size in the group header memory MEG.
Microprocessor 56 generates based on bytes T1 and T2 or two bytes F1 and F2 representing the size of the last data block. When a data group is repeatedly sent and the data block previously stored in the data group memory MGD contains an uncorrected error, the content of this memory MGD is repeatedly sent. Data blocks that do not contain uncorrected errors are rewritten. Such a process is performed one after another until the data blocks which are repeatedly sent are finished.

The output terminal of the thirteenth logic circuit CL13, to which the output terminal of the data group memory MDG is connected to the input terminal, is the data transmission wire (D) 87 and the wires PAR and D connected to the bus 11.
Connected to output junction J5 consisting of OP and.
The reset input terminal of the ninth counter C9, whose input terminal is connected to the wire DOP, is connected to the bus 11 by a connecting line 88.
Eleventh input terminal connected to the output terminal of counter C9
The second input terminal of the digital comparison circuit CN11 of is a fifteenth memory M1 whose input terminal is connected to the bus 11 by a connecting line 89.
It is connected to the output terminal of 5. The output terminal of this circuit CN11 is connected to the inhibit input terminal of the thirteenth logic circuit CL13, and the enable input terminal of this circuit CL13 is connected to the bus 11 by a connecting line 90.

After the data has been stored in the data group memory MGD, the microprocessor 56 operates the random access memory 54 (5th
A data group is sent via the third logic circuit CL13, the wire 87 and the bus 11 to the drawing. When the transmission from the transmitting station is over,
All of the data files from the database (Figs. 1 and 2) are stored in the random access memory 54 and are made available to the calling terminal 9 (Fig. 5).

Although the present invention has been described with reference to the embodiments, it goes without saying that various modifications can be made without departing from the scope of the claims. The present invention can also be applied to, for example, a data communication system in which a standard video signal is unidirectionally transmitted via a wired program distribution network instead of a wireless television channel. Further, even if the temporal structure of the data packet defined by the synchronizing signal of the video signal is any, it can be applied to the data communication system by the one-way medium for transmitting the modulated carrier signal representing the flow of digital data.

As is known from the above, an object of the present invention is to provide a receiver suitable for an improved Daddon system type one-way data communication system. In this improved one-way data communication method of the Daidon system, digital data can be handled in the form of data groups, and the conventional one-way data communication method that handles digital data in the form of data packets. Compared to the receiver of
As described in the first part of the "Detailed Description of the Invention", the clarity of transmitted digital data is ensured independent of the electrical characteristics of the propagation medium. And
It was confirmed that such an effect could be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram of a one-way data communication system including a plurality of receivers according to the present invention, FIG. 2 is a block diagram showing a transmitter of the communication system shown in FIG. 1 together with a broadcasting network, and FIG. 2 is a block diagram of a data group generator of the transmitter shown in FIG. 2, FIG. 4 is a block diagram of a data packet generator of the device, and FIG. 5 is a block diagram of a receiver according to an embodiment of the present invention. FIG. 7 is a block diagram of the data packet processing circuit of the receiver shown in FIG. 5, and FIG. 7 is a block diagram of the data group management circuit of the receiver. In the drawings, 1 is a database, 2 is a transmitting device, 3 is a video program, and 1 and 3 are examples of a plurality of data sources. Further, 4 is a broadcasting network including a plurality of channels, 5 is a receiver, 7 is a demodulation device, 8 is a data acquisition device, 9 is a call terminal as an example of peripheral equipment, 11 is a bus,
55 is a group and packet processing circuit, 56 is a microprocessor, 57 is a decoding control interface, 58 is a data packet processing circuit, 59 is a data group management circuit, 90 is an aprom operating as a program memory, 51 is a demodulator and demultiplexer , 52 indicates a program interface, and 51 and 52 operate as a demodulator circuit. Further, CL8 is a logic circuit that operates as a first input circuit, MPT is a main memory, C6, R5, CN5, and M9 are means for calculating the number of bytes, and R6, CN6, M10, and the Miro processor 56 are packet continuous. Means for recognizing the sex indication signal IC and the packet structure information SP, P2 is an AND circuit, BDC is a block memory, CL9, M11, CN7, R7, and C7 are output means, and CL10 is a logic that operates as a second input circuit. Circuits, R8, CN8, and M12 are detection circuits for byte TG that specify the format of the data group, CL11 is a logic circuit that operates as a third input circuit, MEG is a group header memory, and CL12 is a fourth input circuit. Logic circuit, MG
D is a data group memory, CL13 is a logic circuit that operates as an output circuit, C8 is a byte counter, CN9, CN10, and the microprocessor 56 is a group repeat byte R.
In addition to the group continuity index byte C analysis means, CEX in FIG. 7 is an exclusive OR circuit which operates as a decoding circuit, P3
And P4 indicate a gate circuit.

Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H04N 7/081 (72) Inventor Jean-Claude Baldo France F-35760 Monjeemon Réuil de la・ Fujieroll 35 (72) Inventor Zielard Syubet F-35031 Rennes Riu de Huamel 2 (56) References JP-A-56-47177 (JP, A) JP-A-55-28691 (JP , A)

Claims (4)

[Claims] 1. In a one-way data communication system, digital data from each data source is represented by a data group, each of these data groups is in the form of a series of data blocks, and each data block is a data field of a data packet. Insert the first data block of each of these data blocks into
A byte that specifies the format of the data groove, a group continuity indicator byte, a byte that indicates the number of data blocks that the data group contains after the first data block, and a size of the last data block of the data group. With a group header consisting of
For each of these data blocks, in addition to the sync signal and the channel designation code signal, the data packet continuity indication signal, the data packet structure information, and whether the data block of this data packet is the first data block in the data group. A receiver including a demodulator circuit, a data acquisition device, a peripheral device, a microprocessor, and a program memory, which receives a data packet broadcasted with a front portion including information indicating whether or not, The data acquisition device includes a group and packet processing circuit that includes a data packet processing circuit and a data group management circuit and is connected to the demodulator circuit, the data packet processing circuit including a first input circuit and the input circuit. Of incoming data packets that are output A main memory for storing each of them, means for counting the number of bytes forming an incoming data packet and stopping the output of the input circuit each time the count reaches a predetermined value, Means for confirming the data packet continuity instruction signal and the data packet structure information, and an AND circuit for supplying the data blocks stored in the main memory to the input terminal and passing these supplied data blocks from the first data block A one-way data communication type receiver comprising: a block memory in which the output of the AND circuit is stored; and means for outputting the output of the block memory. 2. A data group management circuit, comprising: a second input circuit; and a detection circuit for detecting from the output of this input circuit whether or not the byte designating the format of the data group matches a predetermined byte. A third input circuit, a group header memory that stores the output of this input circuit, a fourth input circuit, a data group memory that stores the output of this input circuit, and an output that outputs the output of this data group memory. A circuit, a byte counter having output terminals connected to the third input circuit and the fourth input circuit, for counting the number of bytes forming an incoming data group;
Analyzing means for analyzing the group continuity index byte supplied with the output of the group header memory, wherein the detection circuit detects that the byte designating the format of the data group matches a predetermined byte. The third input circuit is activated, and the third and fourth input circuits are sequentially operated by the count value counted by the byte counter as long as the analyzing unit analyzes that the group continuity index byte is correct. A one-way data communication type receiver according to claim (1). 3. The one-way data communication system according to claim 2, further comprising a decoding circuit controlled by a decoding control interface between the fourth input circuit and the data block memory. Receiving machine. 4. The output of the detection circuit is supplied to a gate circuit that activates the byte counter when it detects that a byte designating the format of a data group matches the predetermined byte. A one-way data communication type receiver according to the range (2) or (3).