JPH0793570B2 - Capstan servo device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capstan servo device, and (1) uses a PG signal obtained by dividing a capstan FG signal even during reproduction by a magnetic recording / reproducing device. (2) to provide a capstan servo device that enables tracking servo by performing tracking servo by (2) obtaining a frequency-divided output of the same frequency as the reference signal even when the FG signal cannot be obtained by an integer multiple of the PG signal. Is.

2. Description of the Related Art In a capstan servo device of a magnetic recording / reproducing apparatus, in order to implement phase servo during recording, the output of a frequency generator (hereinafter referred to as FG) that detects the rotation speed of a capstan motor (hereinafter referred to as FG signal) Called) is used after being divided by a dividing means. This divided output is commonly called the PG signal. The capstan servo device uses this PG signal as a comparison signal for the phase servo, and implements the capstan servo by comparing the phase with a reference signal (for example, a vertical frame synchronization signal 30Hz) to control the tape speed of the magnetic tape at a constant value. There is.

On the other hand, at the time of reproduction, the control signal recorded on the magnetic tape is reproduced, and the reproduction control signal (hereinafter referred to as the CTL signal) is used as a comparison signal to realize the capstan servo by phase comparison with the reference signal, thereby performing the tracking servo. I am doing it.

FIG. 3 is a block diagram of a conventionally known capstan servo device.

In FIG. 3, 1 is a capstan motor, 2 is an FG for detecting the rotation speed of the capstan motor 1, and 3 is a reference signal S2.
Input terminal for inputting 4 is FG signal S1 obtained from FG2
Frequency dividing means 5 for dividing the CTL signal S4 is inputted to the input terminal 6, and PG signal S3 and CTL signal S for outputting the frequency dividing means 4
A switch for switching 4 between recording (R) and reproduction (P) (PG signal S3 from the R side during recording, from the P side during reproduction)
CTL signal S4 is selected), 7 is a phase comparison means for detecting the phase error signal S6 by phase comparison with the reference signal S2 using the signal S5 selected by the switch 6 as a comparison signal, and 8 is an FG signal.
Speed comparing means for detecting the speed error signal S7 by discriminating the frequency of S1 and mixing means 9 for mixing the phase error signal S6 and the speed error signal S7 to obtain a mixed output S8.

With the above configuration, the speed of the capstan motor 1 is controlled by the output S7 obtained by discriminating the frequency of the FG signal S1, and the reference signal S2 and
The phase is controlled by an output S6 that is a phase comparison with the PG signal S3 or the CTL signal S4. That is, the capstan servo device is realized by controlling the speed and phase of the capstan motor 1 by the mixed output S8. The capstan motor 1
When a motor that does not require speed control (for example, a synchronous motor) is used, the speed comparison means 8 and the mixing means 9 are unnecessary. In this case, the output S6 of the phase comparison means 7 may be used to directly control the capstan motor 1. .

However, in the above configuration, (1) CTL signal S4
The tracking servo by PG signal S3 was impossible, even though the tracking servo by. Furthermore, (2)
Since the frequency dividing means 4 can only perform integer frequency division, in order to obtain the PG signal S3 having the same frequency as the reference signal S2, the PG signal
There is a problem that it is necessary to select S1 as an integral multiple of the reference signal S2.

First, the problem (1) will be described. The phases of the CTL signal S4 and the PG signal S3 at the time of reproduction do not coincide with each other and are in an asynchronous relationship. Therefore, tracking servo could not be realized using the PG signal S3.

Regarding the problem (2), one is that the frequency of the PG signal S3 does not always match the frequency of the CTL signal S4 in consideration of tape compatibility. This occurs because the tape is stretched due to environmental changes or changes over time, and variations in the magnetic recording / reproducing apparatus, that is, variations in capstan shaft diameter and pinch roller pressure contact force. Another one is FG signal
This is the case when the frequency of S1 cannot be obtained as an integer multiple from the beginning.

Hereinafter, the problem (2) will be further described.

Generally, the tape speed V _t when the magnetic tape is directly driven by the capstan motor is calculated by the following equation (1).

V _t = π ・ D ・ N ・ F _PG / Z, where π is the circumference ratio, D is the diameter of the capstan shaft, N is the division ratio, F _PG is the frequency of the PG signal, and Z is the number of FG teeth. Is. Note that N · F _PG is the frequency F _FG of the FG signal.

In the formula, V _t takes the specific value from the tape format of a magnetic recording and reproducing apparatus. Since the PG signal is also specified, D, N, Z must be selected so that the value obtained by dividing the product of D and N by Z is constant as shown in the equation.

D ・ N / Z = constant ... Normally, it is more economical to use a standard product for the capstan shaft, but since N and Z are limited to integers, a special product must be used in some cases. If you are lucky enough to use the standard product, there is no problem, but if you do not say that you can not use anything other than the standard product, PG
There is no choice but to set the signal frequency F _PG to a frequency different from 30 Hz. In this case, since the vertical frame synchronization signal cannot be used as a reference signal, a new reference signal generator is provided and an internal reference signal equal to the frequency F _PG of the _PG signal must be generated and used. Therefore, there is a problem that the reference signal must be switched between recording and reproducing.

As is clear from the above description, in the conventional capstan servo device, since the frequency dividing means can only perform integer frequency division, there are many restrictions in the design of the device.

The present invention solves the above problems (1) and (2), and (1) enables tracking servo using a PG signal during reproduction, and (2) enables non-integer frequency division. As a result, there are no design restrictions on the shaft diameter D and the number of teeth Z, and FG
An object of the present invention is to provide a capstan servo device that can obtain a PG signal having a desired frequency from a signal.

Means for Solving the Problems To achieve this object, a capstan servo apparatus of the present invention is a variable frequency dividing means that is reset by a reproduction control signal and variably frequency-divides a captan FG signal,
Difference detecting means for detecting a timing difference between the output of the variable frequency dividing means and the reproduction control signal, and output of the difference detecting means is preset by the output of the variable frequency dividing means and output of the variable frequency dividing means. And a correcting means for correcting the timing of the output of the variable frequency dividing means according to the output of the calculating means, and a frequency dividing of the variable frequency dividing means according to the output of the calculating means. Switching means for switching the ratio, cycle difference detecting means for detecting the cycle difference between the reproduction control signal and the output of the correcting means and correcting the calculated value of the calculating means, and a reference signal using the output of the correcting means as a comparison signal. And a phase comparing means for detecting a phase error signal by comparing the phase error signal with the phase error signal, and the capstan motor is controlled by the phase error signal. Further, instead of the arithmetic means, an arithmetic means for presetting the output of the difference detecting means by the reproduction control signal and performing arithmetic operation in synchronization with the output of the variable frequency dividing means may be used.

The present invention also comprises speed comparing means for discriminating the frequency of the capstan FG signal to detect a speed error signal, and mixing means for mixing the speed error signal and the phase error signal, and the capstan motor is output by the output of the mixing means. Is configured to control.

The present invention is also configured to include a determination means for determining whether or not the cycle of the reproduction control signal is normal, and to use as a reproduction control signal only when the cycle is normal.

With the above-described structure, the present invention switches the frequency division ratio of the variable frequency dividing means according to the arithmetic output obtained by the arithmetic means by the switching means, and controls the correcting means by the arithmetic output to output the output of the variable frequency dividing means. Since the timing can be corrected, non-integer frequency division is possible (integer frequency division is also possible), and the capstan FG signal can be frequency-divided into a desired frequency.
However, by making the output of the correction means a PG signal,
It is possible to realize a capstan servo device having no design restrictions. Further, since the output of the difference detecting means is preset in the calculating means and the variable frequency dividing means is reset by the CTL signal, a PG signal locked to the CTL signal can be created and tracking servo by the PG signal can be realized.

In addition, the cycle difference detection means enables the reproduction control signal and the PG
Since the configuration is such that the period difference from the signal is detected and the calculation value of the calculation means is corrected, the frequency of the PG signal can be made to match the frequency of the reproduction control signal.

Further, since the judging means judges whether the cycle of the reproduction control signal is normal or not and is used, it can be resistant to noise.

Embodiments Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 (A) is a block diagram of a capstan servo system according to an embodiment of the present invention.
(C) is a block diagram showing a new additional function. First
In the figure, 1-3, 5, 7-9 and S1, S2, S4, S6-
S8 is the same as the components and signals of FIG. 3, with the different components and signals being 10-16 and S9-S15.

10 is a variable frequency dividing means that is reset by the CTL signal S4 and frequency-divides the FG signal S1. 11 is a variable frequency dividing output of the variable frequency dividing means 10.
Difference detecting means for detecting the timing difference between S9 and CTL signal S4, 12 is a calculating means for calculating in synchronization with the variable frequency dividing output S9 of the variable frequency dividing means 10, and 13 is according to the calculating output S11 of the calculating means 12. Correction means for correcting the timing of the variable frequency division output S9 of the variable frequency division means 10, 14 is a switching means for generating a switching signal S13 according to the arithmetic output S11 of the arithmetic means 12 and switching the frequency division ratio of the variable frequency division means 10. And the frequency division output from the correction means 13, that is,
The PG signal S12 is obtained. Further, the difference output S10 of the difference detection means 11 is preset (loaded) to the calculation means 12 by the variable frequency division output S9 (or the CTL signal S4) to correct the timing difference between the CTL signal S4 and the variable frequency division output S9. There is. As a result, the PG signal S12 locked to the CTL signal S4 can be obtained by resetting the variable frequency dividing means 10 with the CTL signal S4 and presetting the differential output S10 in the calculating means 12. By inputting and using the PG signal S12 as the comparison signal S to the phase comparison means 7, tracking servo during reproduction can be performed without using the CTL signal S4.

Reference numeral 15 is a cycle difference detecting means for detecting a cycle difference between the CTL signal S4 and the PG signal S12, and is configured to correct the calculated value of the calculating means 12 by the detected cycle difference signal S14. It matches the frequency of S4. This gives P
Even if the frequency of the G signal S12 is different from the frequency of the CTL signal S4, it can be corrected to be equal. This means that if the CTL signal S4 is missing or if the CTL signal from the judging means 16
If S15 is interrupted, the frequency of PG signal S12 changes to CTL signal S4.
This is effective in preventing the frequency from shifting.

Reference numeral 16 is a judging means for judging whether or not the cycle of the CTL signal S4 is normal, and outputting the CTL signal only when it is normal, and noise can be enhanced by using the CTL signal S15 which has passed through this means. CTL signal S15 is variable frequency dividing means 10, difference detecting means 11,
The calculation means 12 and the period difference detection means 15 may be input and used instead of the CTL signal S4.

The operation of the capstan servo device of this embodiment having the above-described structure will be described below. In addition,
Since the speed and phase control operations by the speed comparison means 8 and the phase comparison means 7 are the same as those in the conventional example, only the operation of the main part of the present invention will be described.

FIG. 2 is a waveform diagram showing an operation example of the main part of the present invention. Here, the variable frequency dividing means 10 shows an example in which an up-counter is used as the frequency dividing counter, and the PG signal S12 shows an example in which the cycle is 3.7 times the FG signal S1. Further, the correction means 13 shows an example in which the fineness of correction is 1/10 of the cycle of the FG signal S1. Therefore, the correction means 13 may correct the timing using a clock having a frequency 10 times the frequency of the FG signal, which can be easily realized by using a digital delay circuit. PG signals S12 and F
The period ratio 3.7 of the G signal S1 is 37 when converted into the number of clock pulses. Further, a down counter capable of repeating counting from 9 to 0 is used as the calculating means 12, and a variable frequency division output S9 is used.
An example of calculation in which only 3 is subtracted in synchronism with. This subtracted value is a value obtained by subtracting 37 from 40 and is a difference with respect to the cycle of an integer multiple of the FG signal S1. If an up counter that repeatedly counts from 0 to 9 is used here, 37 to 30
It suffices to perform an operation of adding the difference value 7 obtained by subtracting. It suffices that the calculation speed of the calculation means 12 be completed by the time immediately before the correction means 13 needs the correction value. Also, the times t0 to t1 shown in the figure
The number 2 is a 3.7-fold cycle of the FG signal S1 (this is the cycle of the PG signal S12 and also the cycle of the CTL signal S4).

In FIG. 2, a waveform A is an FG signal S1, a waveform B is a frequency dividing operation of the variable frequency dividing means 10, and waveforms C _N and C ₁ are outputs obtained by decoding the count value N, 1 of the variable frequency dividing means 10 ( Variable frequency division output S9N, S91)
Waveform D is a CTL signal S4, waveform E is a reset pulse created by the variable frequency dividing means 10 by the CTL signal S4 and the FG signal S1 (when the rising edge of the CTL signal S4 is in the “H” period of the FG signal S1). Is a pulse generated by the fall of the FG signal S1 immediately after the CTL signal S4, and the rise of the CTL signal S4 when in the "L" period, and the waveform F is the difference output S10 (variable frequency division) of the difference detecting means 11. CTL signal S4 from the rise of output S9N
Output measured up to the rising edge of
The output of the calculation operation of 12 (operation of subtracting 3 in synchronization with the rising of the variable frequency dividing output S91) is compared with the predetermined value (here, 3) of the calculation output S11 in the switching means 14 (predetermined value). "H" if above, "L" if less, waveform I
Is the output obtained by latching this comparison output at the falling edge of the variable frequency dividing output S9N, that is, the switching signal S13, and the waveform J is the correction means 13
At the output of the variable frequency-divided output S9N corrected by the calculation output S11 of the calculation means 12 (the width of the pulse represents the correction amount), the waveform K is a pulse created by the fall of the correction output, that is, the PG signal S12. Indicates. The differential output S10 is preset in the calculating means 12 at the rise of the variable frequency dividing output S91 (or the CTL signal S4). As a result, the PG signal S12
Can be synchronized with the timing of the CTL signal S4.

Now, the cycle of the PG signal S12 is 3.7 times the cycle of the FG signal S1, so it is -0.3, + compared to the integer division values 4 and 3 before and after that.
There is a difference of 0.7. This is -3 and +7 when converted into the number of clock pulses. Therefore, if the frequency is simply divided by an integer, a higher frequency division output, which is lower than the frequency of the PG signal S12, is obtained, the timing is phase-delayed, and the timing gradually shifts in the advancing direction. It cannot be obtained as a divided output.

Therefore, according to the present invention, in the variable frequency dividing means 10, the switching signal S13
(Waveform I) is used to switch the division ratio between 3 and 4 (divide by 3 when low, divide by 4 when high), and output variable variable frequency S9N (waveform C _N ) earlier than each time from t0 to t12. The output signal S12 at the same timing as t0 to t12 is obtained by correcting the calculated output S11 (waveform G) by the correction means 13.
(Waveform K) is obtained.

For convenience of explanation, it is assumed that the time t0 coincides with the rising edge of the FG signal S1 (waveform A). In practice, it does not matter from which time it starts, which is determined by the calculation output S11. The calculation output S11 at time t0 is 0. The calculating means 12 shows the case of subtraction (waveform G). Correction means 13
Since the fineness of correction was set to 1/10, it is sufficient if 10 types of correction can be made. Therefore, the calculation means 12 has only to output 10 values from 9 to 0, which corresponds to the subtraction shown in the waveform G. As you can see from the waveform diagram, t0 ~ t1, t3 ~ t4, t6 ~
Divide by 3 between t7, t10 and t11, t1 to t2, t2 to t3, t4 to t
5, t5 ~ t6, t7 ~ t8, t8 ~ t9, t9 ~ t10, t11 ~ t12 4
If frequency division is used, the variable frequency division output S can be obtained earlier than each time t0 to t12.
9N (waveform CN) can be obtained. At this time, the difference between the rising of the variable frequency division output S9N and each time is 0,7,4,1,8,5,2,9,6,3,0,7,4 from t0 to t12. . Therefore, if this value is used as the correction value, the PG signal S12 at the desired timing can be obtained. The waveform J shows the correction amount, and each correction amount is a value obtained by subtracting 3 from the previous value. This corresponds to the difference-3 described above. The calculated value is the calculation output S11 shown in the waveform G. Here, the calculation by the calculation means 12 may be performed after each time and before the next correction starts.
In the illustrated example, the variable frequency division output S91 shown in the waveform diagram C1 is used, and calculation is performed in synchronization with the rising of the signal S.

On the other hand, the switching of the frequency division ratio in the variable frequency dividing means 10 may be divided into 4 when the previous calculation output S11 is 3 or more, and divided into 3 when it is less than 3. This is because the switching means 13 compares the calculated output S11 with a predetermined value (3 in this case) to obtain an output, and this comparison output is latched at the falling edge of the variable frequency dividing output S9N to create a switching signal S13. , This switching signal S13
You can switch with. In the illustrated example, the switching signal S1 shown by the waveform I
When 3 is low, the division ratio is N = 3, and when it is high, N = 4. Here, the predetermined value used for the size comparison corresponds to the above-mentioned difference -3. This means that when the previous correction value is less than 3, the next correction value is 7 or more, that is, the next division ratio becomes small.

As described above, calculation is performed by the calculation means 12 in synchronization with the variable frequency division output S9 of the variable frequency division means 10, and switching of the frequency division ratio in the variable frequency division means 10 according to the calculation output S11 and correction means
The timing correction in 13 can be performed, and the PG signal S12 of the desired frequency can be obtained from the correcting means 13.

In the above description, the variable frequency division output S9 of the variable frequency division means 10 is
The timing of the rising edge of N is corrected and the calculation is performed in synchronization with the rising edge of the variable frequency division output S91.
It is not limited to this. Further, when the arithmetic means 13 is configured as hardware, a down counter may be configured as a subtracter, and when configured as software, it is possible by executing a subtraction program by a microcomputer. When embodied by using a microcomputer, not only the calculating means 13 but also the phase comparing means 7 and the speed comparing means 13
Not only this, but the phase comparison means 7, the speed comparison means 8, the mixing means 9, the difference detection means 11, the correction means 13, the switching means 14, the period difference detection means 15 and the determination means 16 can all be processed by software. Needless to say, the correction means 13 is the phase comparison means 7
May be included in the processing.

The non-integer frequency division of the present invention described above is performed by using an example of an operation example, but a more general description is as follows: (1) First, the FG signal for the frequency f _PG of the PG signal S12. _Find the multiplication factor f _FG / f _PG of S1 frequency f _FG . This is 3.7 times the above.

(2) Integer value N when f _FG / f _PG is rounded up to the nearest whole number.
Find ₁ and the integer value N ₂ when truncated. This is the frequency division ratio in the variable frequency dividing means 8, and if it corresponds to the above value
N ₁ = 4, N ₂ = 3 (N ₁ = N ₂ +1).

(3) The clock frequency f used by the correcting means 10 for the frequency f _FG of the FG signal S1 is calculated by subtracting f _FG / f _PG from N ₁ , N _2.
Multiplied by a factor f _CK / f _FG of _CK, the difference M in terms of number of clock pulses ^- to determine the M ^{+. _{M - = (f FG / f}} PG -N 1) · f CK / f
_FG , M ⁺ = (f _FG / f _PG -N ₂ ) · f _CK / f _FG , and corresponding to the above values, M ⁻ = −3, M ⁺ = + 7. It is a subtraction value and an addition value.

The main part of the present invention has been described above, but the present invention uses the non-integer frequency division to realize the capstan FG.
Even if the signal S1 cannot be obtained at an integer multiple of the frequency of the reference signal S2 for phase comparison, the PG signal S12 of the same frequency as the reference signal S2
Can be obtained. As a result, the shaft diameter D of the capstan and the number of teeth Z of the FG can be arbitrarily selected, and the PG signal S12 can be a signal locked to the CTL signal S4. Therefore, the CTL signal S4 is not used. Thus, tracking servo can be realized by the PG signal S12.

EFFECTS OF THE INVENTION As described above, according to the present invention, since the FG signal can be divided by a non-integer frequency (integer frequency division is also possible), the shaft diameter D of the capstan and the number of teeth Z of the FG, which has been impossible in the past, are obtained. Can be arbitrarily selected, and a capstan servo device that is not restricted by the shaft diameter D and the number of teeth Z can be realized, and tracking servo by the PG signal S12 can be realized without using the CTL signal S4. This can be done and can be strengthened against the missing CTL signal S4 and noise, so its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a capstan servo device according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing an operation example of non-integer frequency division of the essential part of the present invention, and FIG. 3 is a conventional capstan servo device. It is a block diagram of. 7 ... Phase comparing means, 8 ... Speed comparing means, 9 ... Mixing means, 10 ... Variable frequency dividing means, 11 ... Difference detecting means, 12 ...
… Computing means, 13 …… correcting means, 14 …… switching means, 15 ……
Period difference detection means, 16 ... Judgment means.

Claims (4)

[Claims] 1. A variable frequency dividing means that is reset by a reproduction control signal and variably frequency-divides a capstan FG signal, and a difference detecting means that detects a timing difference between the output of the variable frequency dividing means and the reproduction control signal. An operation means for performing an operation in synchronization with an output of the variable frequency dividing means while the output of the difference detecting means is preset by the output of the variable frequency dividing means; and the variable frequency dividing according to the output of the arithmetic operation means. Correction means for correcting the output timing of the means, switching means for switching the frequency division ratio of the variable frequency division means according to the output of the arithmetic means, and a cycle difference between the reproduction control signal and the output of the correction means. A phase difference detection means for detecting and correcting the calculation value of the calculation means, and a phase error signal by phase comparison with a reference signal using the output of the correction means as a comparison signal. Capstan servo device comprising a phase comparison means for output, and controlling the capstan motor by the phase error signal. 2. A variable frequency dividing means which is reset by a reproduction control signal and variably frequency-divides a captan FG signal, and a difference detecting means which detects a timing difference between an output of the variable frequency dividing means and the reproduction control signal. An output of the variable division means is preset by the reproduction control signal and an arithmetic means for performing an operation in synchronization with the output of the variable division means; Correction means for correcting the timing; switching means for switching the frequency division ratio of the variable frequency division means according to the output of the calculation means; and the calculation by detecting the cycle difference between the reproduction control signal and the output of the correction means. A phase difference detection means for correcting the calculated value of the means, and a phase error signal by phase comparison with a reference signal using the output of the correction means as a comparison signal. Capstan servo device comprising a phase comparison means for output, and controlling the capstan motor by the phase error signal. 3. A capstan motor comprising: speed comparing means for detecting a speed error signal by discriminating the frequency of the capstan FG signal; and mixing means for mixing the speed error signal and the phase error signal. 3. The capstan servo device according to claim 1, wherein the capstan servo device is configured to control 4. The capstan servo according to claim 1, further comprising a judging means for judging whether the cycle of the reproduction control signal is normal or not, and used as the reproduction control signal only when the cycle is normal. apparatus.