JPH0793038B2 - Semiconductor memory failure analysis device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention analyzes whether a defect in a semiconductor memory is analyzed and whether a defect in a memory body can be repaired by a spare memory cell row and a spare memory cell column. The present invention relates to a failure analysis device for a semiconductor memory that determines whether or not it is.

(Prior Art) In order to increase the yield of semiconductor memory, a redundant circuit including spare memory cells may be provided. If there is a defective memory cell in the semiconductor memory body, a spare memory cell is used instead of this defective memory cell, so that it is supposed to be defective as if no external defective memory cell exists. Is relieving semiconductor memory.
However, since the spare memory cells of the redundant circuit have a limit, if the number of defective memory cells increases, the redundant circuit cannot relieve. Further, even if the number of defective memory cells is not so large, it may not be possible to relieve depending on the arrangement. Therefore, it is necessary to analyze a defect in the semiconductor memory and determine whether or not the defective memory can be relieved by the redundant circuit.

A conventional semiconductor memory failure analysis method will be described with reference to FIG. The semiconductor memory to be analyzed has one spare memory cell row 4 and one spare memory cell column 6. Four
The × 4 bit defect analysis memory 2 indicates the position of the defective memory cell in the memory body of the semiconductor memory. The row inspection memory 8 and the column inspection memory 10 store the inspection results of each row and each column.

An analysis method when the failure analysis memory 2 has three defective bits (indicated by "1") as shown in FIG. 4A will be described. First, the defective bits of the failure analysis memory 2 are counted for each row and each column, and the counted values are stored in the row inspection memory 8 and the column inspection memory 10. Of the count values of the row inspection memory 8 and the column inspection memory 10, the spare memory cell row 4 or the spare memory cell column 6 is used as a substitute for the row or column having the maximum count value, and the failure analysis memory of the row or column used. The defective bit of 2 is set to "0". Since the count value in the first column is "2" in FIG. 4 (a), the spare memory cell row 4 is used instead of this first column, and the failure analysis is performed as shown in FIG. 4 (b). The defective bit in the first column of the memory 2 is set to "0".

Then, the defective bits of the failure analysis memory 2 are counted again for each row and each column, and the counted values are stored in the row inspection memory 8 and the column inspection memory 10 as shown in FIG. Again, based on the count values of the row inspection memory 8 and the column inspection memory 10,
The row or column using the spare memory cell row 4 or the spare memory cell column 6 is determined, and the defective bit of the defective analysis memory 2 of the used row or column is set to "0". Since the count value of the first row is “1” in FIG. 4B, the spare memory cell column 6 is used instead of the first row, and the defective bit of the first row of the failure analysis memory 2 is set to the defective bit. Set to "0".

Then, the defective bits of the failure analysis memory 2 are counted again for each row and each column, and it is judged that the repair is possible if all the counted values become "0".

(Problems to be Solved by the Invention) As described above, in the conventional failure analysis method, the number of defective bits in the failure analysis memory 2 is counted every time the spare memory cell row 4 or the spare memory cell column 6 is used. When the number of bits of the semiconductor memory becomes large, there is a problem that it takes time for failure analysis. Further, in the conventional determination method, since the spare memory cell row and the spare memory cell column are used in the descending order of the count value of the defective bit, if it is determined that the spare memory cell can be rescued but cannot be rescued properly, was there.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor memory failure analysis apparatus capable of appropriately and quickly analyzing whether or not a semiconductor memory can be repaired by a spare memory cell. To do.

[Structure of Invention]

(Means for Solving Problems) The above-described object is to provide a failure analysis memory that stores data indicating whether all bits constituting a memory body of a semiconductor memory are normal bits or defective bits, and a spare memory. A mask memory for storing data indicating a bit replaced by a memory cell row or a spare memory cell column, and a replacement for a defective bit by using the data input from the defect analysis memory and the data input from the mask memory A semiconductor memory failure analysis apparatus comprising: an allocation determining unit that determines allocation of a spare memory cell row and a spare memory cell column, wherein the allocation determining unit includes the spare memory cell row and the spare memory cell column. The repair combination table that stores all combinations of the alternative use order of A defective bit that has not been replaced by using a use flag that stores up to which combination has already been tried, and data that has been input from the defect analysis memory and data that has been input from the mask memory. A defective memory detection circuit that sequentially determines whether or not all the bits are detected, and each time the defective bit detection circuit detects a defective bit that is not replaced, the defective bit is detected as the spare memory cell row or the spare memory cell row. And a combination determination circuit for determining which of the cell columns is to be replaced based on the input data from the repair combination table and the use flag, and a defect analysis device for a semiconductor memory. .

(Operation) For each bit, the defective memory detection circuit sequentially judges whether or not the defective bit has not been replaced, and each time the defective bit detection circuit detects a defective bit that has not been replaced, a combination judgment is made. The circuit allocates a spare spare memory cell row or spare memory cell column.
The combination determination circuit determines whether to allocate the spare memory cell row or the spare memory cell column using the repair combination table and the use flag.

(Embodiment) FIG. 1 shows a semiconductor memory defect analysis apparatus according to an embodiment of the present invention. In the failure analysis memory 2, "1" is written at the position of the defective bit in the memory body of the semiconductor memory to be analyzed. The defective mask memory 14 is a memory in which mask data indicating whether the row or the column in the memory body is replaced by the spare memory cell row 4 or the spare memory cell column 6 is written. "1" is written in the position of the memory cell being replaced.

The defect address search circuit 16 sequentially outputs addresses to the defect analysis memory 2 and the defect mask memory 14 for the defect analysis search. The defect analysis memory 2 and the defect mask memory 14 output the contents of the address from the defect address search circuit 16 to the mask calculation circuit 18.

The mask calculation circuit 18 and the defective memory detection circuit 20 detect whether or not each memory cell of the memory body is a defective bit based on the output signals of the defect analysis memory 2 and the defective mask memory 14, and detect the defective bit. Detect the address. That is, the mask operation circuit 18 obtains the logical product of the output signal of the defect analysis memory 2 and the inverted signal of the output signal of the defect mask memory 14 and outputs it. The defective memory detection circuit 20 outputs the address to the combination determination circuit 22 when the output signal from the mask operation circuit 18 is "1".

The combination determination circuit 22 determines whether the detected defective memory is relieved by the spare memory cell row 4 or the spare memory cell column 6. In making this determination, the rescue combination table 24 is referred to. The repair combination table 24 stores all combinations of the use order of the spare memory cell row 4 and the spare memory cell column 6. The combination determination circuit 22 reads the combination of the currently used use order from the repair combination table 24 and determines the next use order. When a combination in a certain usage order is used, the next combination is used for the determination. The usage flag 26 can be used to know how far the combination is currently used.

The determination result by the combination determination circuit 22 is output to the mask data writing circuit 28. The mask data write circuit 28 writes mask data in the defective mask memory 14 according to the row or column used for relief. At the same time, the use flag 26 is set to the flag in the order of use.

The determination circuit 30 determines whether the memory body can be repaired by the spare memory cell row 4 and the spare memory cell column 6.
That is, when the defective memory cell is not detected by the defective memory detection circuit 20 even when the final address is reached, the determination circuit 30 determines that the repair is possible. Even if a defective memory cell is detected by the defective memory detection circuit 20, if there is an unused combination in the repair combination table 24, the judgment circuit 30 tries again whether or not the repair is possible with the combination. The mask memory 14 is cleared and the defective address search circuit 16 is reset so as to search from the beginning.
If the defective memory cell is detected by the defective memory detection circuit 20 and all the combinations stored in the repair combination table 24 are used, the determination circuit 30 determines that the repair is impossible.

Next, the operation of this embodiment will be described based on the flowchart of FIG. 2 with reference to FIG.

First, as shown in FIG. 3A, all the defective mask memories 14 are cleared and "0" is written (step S1). Next, the defective address search circuit 16 sequentially outputs addresses from the 0th row and 0th column to search for defective addresses (step S
2) The mask operation circuit 18 and the defective memory detection circuit 20 detect whether or not there is a defective bit (step S3).

In the specific example of FIG. 3, there are defective bits at 0th row and 1st column, 1st row and 0th column, and 3rd row and 1st column. Therefore, since the first 0th row and 0th column is not a defective bit, the process proceeds from step S3 to step S4. In step S4, it is determined whether the address being searched is the final address, and if it is not the final address, the step
Return to S2.

Next, when the first defective bit in the 0th row and 1st column is detected in steps S2 and S3, the combination determination circuit 22 refers to the use flag 26 to check all the relief circuits (spare memory cell row 4, spare memory cell row 4). It is determined whether or not the column 6) is used (step S5). When the spare memory cell row 4 or the spare memory cell column 6 is used as the use flag 26, each flag of the use flag 26 is set.

If all the relief circuits are not used, the combination determination circuit 22 refers to the relief combination table 24 to make a column / row relief determination (step S6). The column / row repair determination is to determine whether the mask data to be written next is a column or a row, and is determined by referring to the combination determination circuit 22.

The repair combination table 24 stores all possible combinations of the use order of the spare memory cell row 4 and the spare memory cell column 6. In this specific example, since one spare memory cell row 4 and one spare memory cell column 6 are used, the repair combination table 24 stores two combinations of “RC” and “CR”. Has been done. "RC" means that the spare memory cell row (ROW) 6 is used first and the spare memory cell row (COLUM)
N) 4 is shown to be used later.

What is "CR"? The spare memory cell row (COLUMN) 4 is used first,
It shows that the spare memory cell row (ROW) 6 is used later.

It should be noted that the spare memory cell row 4 has two rows and the spare memory cell column 6
If there are two columns, the contents of the rescue combination table 24 are the following six types of combinations. That is, "CCRR", "CR
CR, CRCR, RCCR, RCRC, and RRCC. However, “R” indicates that the spare memory cell row is used, and “C” indicates that the spare memory cell column is used.

In this embodiment, since the first combination is "RC", it is determined in step S6 that the spare memory cell column 6 is used, and "0" is written in the column address memory 7 for storing the used column address. Be done. Next, as shown in FIG. 3B, mask data indicating that the spare memory cell column 6 is used is written in the defective mask memory 14 by the mask data writing circuit 28 (step S7), and the process returns to step S2.

Similarly, if the search for the defective bit is continued in steps S2 and S3, the defective bit in the 1st row and 0th column is detected next. Then, in steps S5, S6, and S7, the spare memory cell row 4 is used as a relief circuit, mask data as shown in FIG. 3C is written in the defective mask memory 14, and "0" is written in the row address memory 5. Is written.

Further, when the defective bits are searched in steps S2 and S3, defective bits in 3 rows and 1 column are detected, but all the relief circuits (spare memory cell row 4, spare memory cell column 6) have already been detected.
Is used, the process moves from step S5 to step S8. In step S8, it is determined whether or not all the combinations stored in the repair combination table 24 have been used. At present, not all combinations have been used, so the process moves to step S1 to search for a defective bit from the beginning as shown in FIG. 3 (d).

The last time, we used the combination of "RC", so we will use the next remaining combination "CR". Therefore, when the defective bit in column 0 and row 1 is detected first, the spare memory cell row 4 is first used as a relief circuit (FIG. 3 (e)), and then the defective bit in column 1 and row 0 is detected. And the spare memory cell column 6 is used (FIG. 3 (f)). By doing so, the defective bits of 3 rows and 1 column that were not masked last time are masked by the defective mask memory 14, and all the defective bits are relieved. Therefore, the defective bit is not detected until the final address is reached, and the determination circuit 30 determines that the repair is possible (step S4).

If a defective bit is detected even if all the relief circuits are used for all the combinations, it is determined in step S8 that all the combinations have been used, and it is determined that the relief is impossible.

As described above, according to the present embodiment, it is not necessary to perform counting or complicated arithmetic processing for each row and column with respect to the defective bit stored in the failure analysis memory. It is only necessary to perform a read process or a judgment process party of "0" or "1". Therefore, when the spare memory cell row and the spare memory cell column are allocated to the semiconductor memory having a large number of bits, the processing time can be shortened.

In addition, in the manufacturing process of a semiconductor memory, generally, with respect to a semiconductor memory in which a defect is detected by one type of inspection, a defect analysis device allocates a spare memory cell row and a spare memory cell column, and then performs another type of inspection. A method is taken to reallocate if a new bad bit is found. When a plurality of inspections are sequentially performed in this way, the number of defective bits may increase but not decrease, so it is meaningless to retry the allocation in which the defective bits could not be rescued by the previous defect analysis. is there.
According to the present embodiment, since the repair combination table 24 and the use flag 26 are provided, when the second and subsequent allocations are performed, the combination used in the failure analysis up to the previous time is stored in the use flag 26. Therefore, the failure analysis may be continued as it is, and the failure analysis may be performed only for the combinations that have not been tried in the failure analysis up to the previous time. In this respect, the processing time can be shortened.

Furthermore, according to the present embodiment, all combinations of spare memory cell rows and spare memory cell columns are sequentially tried until it is determined that the repair is possible. There is no risk of misjudgment.

The present invention is not limited to the above embodiment, and various modifications can be made.
For example, in the above embodiment, one row of spare memory cell rows and one column of spare memory cell columns are used, but a plurality of rows and a plurality of columns of spare memory cell rows and spare memory cell columns may be used.

〔The invention's effect〕

As described above, according to the present invention, it is possible to appropriately and quickly analyze whether or not the semiconductor memory can be repaired by the spare memory cell. Therefore, it is possible to contribute to improvement of throughput in the inspection process, improvement of production capacity, reduction of equipment, and cost reduction.

[Brief description of drawings]

1 is a block diagram of a semiconductor memory failure analysis apparatus according to an embodiment of the present invention, FIG. 2 is a flow chart showing the operation of the semiconductor memory failure analysis apparatus, and FIG. 3 is a flowchart of the semiconductor memory failure analysis apparatus. FIG. 4 is a diagram for explaining the operation,
The figure is a diagram for explaining a conventional failure analysis method. 2 ... Defect analysis memory, 14 ... Defect mask memory, 16 ...
… Defective address search circuit, 18 …… Mask operation circuit, 20
…… Bad memory detection circuit, 22 …… Combination determination circuit, 24
…… Repair combination table, 26 …… Use flag, 28 ……
Mask data writing circuit, 30 ... Judgment circuit.

Claims (1)

[Claims] 1. A failure analysis memory for storing data indicating whether all bits constituting a memory body of a semiconductor memory are normal bits or defective bits,
To replace a defective bit by using a mask memory for storing data indicating a bit replaced by a spare memory cell row or a spare memory cell column, and data input from the defect analysis memory and data input from the mask memory And a spare memory cell row and spare memory cell column allocation determining means for determining the allocation of the semiconductor memory, the allocation determining means, the allocation determining means, the spare memory cell row and the spare memory cell column And a use flag for storing up to which combination of the combination stored in the repair combination table, the repair combination table storing all combinations of Data and the data input from the mask memory, A defective memory detection circuit that sequentially determines whether or not there is a defective bit for all bits, and each time the defective bit detection circuit detects a defective bit that has not been replaced, this defective bit is set to the spare memory cell. A defect determination circuit for a semiconductor memory, comprising: a combination determination circuit that determines whether to substitute the row or the spare memory cell column based on the input data from the repair combination table and the use flag. apparatus.