JPH0793008B2 - High speed low power delay clock generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and more particularly to a clock generation circuit of the type used in VLSI memory devices.

[0002]

2. Description of the Related Art A dynamic read / write type semiconductor memory device uses a number of internally generated clocks to control a series of events for reading or writing data in a memory cell array. Chip enable and matrix address strobe

[Outer 1] An external clock such as is used to start a series of multiple internal clocks with different delay times.
These internal clocks must reach the full Vdd supply voltage rather than Vdd-Vt and must drive a rather large load circuit. Of course, the regression in processing speed and power is the first major issue.

Dynamic MOS memories containing 256 Kbits and 1 Mbit devices used in VLSI scale transistor size in addition to the above operational requirements, ie transistor thickness including gate oxide thickness. It is necessary to reduce the physical size of each part of the. With a gate oxide thickness of 200Å and a supply voltage of +5 V, the electric field across the gate oxide causes breakdown due to breakdown. In particular, the booted nodes required in such clock generation circuits are subject to the difficulty of creating an excess electric field across the gate oxides of the transistors connected to such booted nodes.

As described above, in the conventional clock generation circuit, it is difficult to properly maintain the zero level and there is a problem in processing speed and power consumption. It also had the drawback of creating an electric field in the insulating layer in the device.

A dynamic RAM device of the type which can use the clock generation circuit of the present invention is disclosed in US Pat. No. 4,239,9 issued to McAlexander White and Lao.
No. 93 and US Pat. No. 4,081,701 issued to White McAdams and Redwin,
A conventional clock generation circuit is disclosed in US Pat. No. 4,239,991 issued to Nagaihon et al. And US Pat. No. 4,239,99 issued to Hong, Reese and Redwin.
No. 0 explained. All of these have been transferred to Texas Instruments.

[0006]

OBJECTS AND SUMMARY OF THE INVENTION It is an object of the present invention to provide improved overvoltage protection for gate oxides of field effect transistors and other similar devices having clock generation circuits that include high level booted nodes. Is to provide.

To achieve the above object, a clock generation circuit according to the present invention has an output transistor, an input transistor, a decoupling transistor, and a discharge circuit including a discharge transistor and a protection transistor, each of the transistors being a source. A decoupling transistor having a drain path and a gate, the input transistor having a source-drain path connected between a supply voltage and an input node, and having a gate connected to receive an input clock voltage; Has its source-drain path connected in series between said input node and the gate of said output transistor, whose gate is connected to said supply voltage, said output transistor having its source-drain path connected to said supply voltage. Connected to the output node to generate the clock The path further comprises means for booting the gate of the output transistor to a voltage at a level higher than the supply voltage after a change of state of the input clock voltage, the boot means being coupled directly to the gate of the output transistor together with the decoupling transistor. The discharge circuit is connected between the gate of the output transistor and the reference potential to discharge the gate of the output transistor according to the state change of the discharge clock voltage that occurs after the gate of the output transistor is booted. The gate of the discharge transistor receives the discharge clock voltage, and the gate of the protection transistor is connected to the supply voltage, which is a clock generation circuit for generating a high level clock voltage.

According to an embodiment of the present invention, the dynamic R
In clock generation circuits for AM and similar devices, it is necessary to boot certain nodes above the supply voltage to provide the high level gate voltage to the output transistors. In order to prevent the gate oxide of the transistor connected to the booted node from exceeding the voltage, a transistor connected in series is added, and the gate is supplied with the supply voltage so that the gate oxide of any transistor There will never be a full booted voltage.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, there is illustrated a clock generation circuit of the type used in VLSI type semiconductor memory devices. Typically, this memory device is disclosed in U.S. Pat. No. 4,239,439 issued to McAlexander, White and Lao, assigned to Texas Instruments.
A 256 Kbit dynamic read / write memory using a one-transistor type cell generally shown in No. 993. Within the memory device shown in these patents, a number of high level clocks need to be generated on a chip. The clock voltage is at the supply Vdd, or approximately 50 to 1 at voltage levels very close to it.
A capacity of 00 pfd has to be driven and the timing is a few nanoseconds.

The circuit of FIG. 1 has the input clock φ shown in FIG.
In response to 1, it performs the function of generating the delayed output clock φ3. Precharge clock

[Outside 2] Is used to set the appropriate conditions before the active cycle begins. Output φ3 is φ for time ΔT
It has a leading edge (leading end) delayed from the start of 1 and a trailing edge (tail end) whose end is determined by the clock φ2.

The gates of the two sets of input transistors 10 and 11 are φ1 and

[Outside 3] Is connected to the node 12 and inputs to the nodes 12 and 13. These nodes are

[Outside 4] Is kept at Vss by Vd when φ1 goes high.
d-Vt. The input voltage at nodes 12 and 13 is used to create a voltage to control the gates 14 and 15 of output transistor 16 and pull-down transistor 17. Transistor 17 is a precharge clock

[Outside 5] The output node 18 is pulled to Vss during the period when is at a high level, and the transistor 16 pulls the output node 18 to Vdd after a delay period after the leading edge of φ1. The gate 14 of the transistor 16 is the booted node 19 which is the gate of the transistor 20.
It is also connected to the gate. Decoupling transistor 21
Connects the input node 12 to the node 19. The gate of this transistor 21 is connected to the delayed clock node 22, which also controls the gate of the transistor 17. The node 19 is pre-discharged by the φ2 clock applied to the gate of the transistor 23, and when φ2 goes high again, the output φ3 is terminated and the node 19 is discharged through the transistor 23. Node 22

[Outside 6] Is at a high level, Vdd-through transistor 24
Since it is precharged to Vt, when φ1 goes high, the transistor 21 becomes conductive and the charge on the node 12 passes to the node 19. Transistor 25 too

[Outside 7] The node 26 is precharged during the period of

[Outside 8] It will not be discharged unless it is pulled down by.
When φ1 goes high, transistors 28 and 2
Node 13 goes high after a short period of delay (in nanoseconds) required to charge the gate of 9. When the transistor 28 starts to conduct, the voltage at the node 26 begins to drop, and this negative going (changing in the negative direction) spike is caused by the capacitive element 27.
The transistor 29 is connected so that the transistor 29 is not affected until the transistor 28 discharges the node 26. When transistors 28 and 29 are both conducting, node 22 discharges, pulling gate 15 low, shutting off transistor 21 and decoupling node 19 from the input. The transistor 30 connected in series with the transistor 20 is also turned off by discharging the node 22. As a result, the gate of the transistor 20 becomes high level by the input clock voltage φ1, so that the node 31
Will also be at a high level. The positive going (positive going) voltage connected on node 31 is at node 1
9 and pulls this node above Vdd as shown in FIG. Therefore, the output node 18 and the output clock φ3 rise to the full Vdd level. φ
2 goes high, node 19 turns on transistor 23
And, it is discharged through the transistor 33 and the pull-down device 17 to terminate φ3.

One of the undesirable features of the circuit of FIG.
The output .phi.3 exhibits a voltage transition at the start of the delay period .DELTA.T. Such a transition is referred to as a "front pouch" and provides undesired operating conditions, especially if the next circuit is voltage sensitive. The rise in voltage is caused by the transistor 16 becoming conductive because the gate voltage of the transistor 16 becomes a high level, which causes not only unintended waste of power in the transistor 17 but also an output voltage effect.

Referring now to FIG. 3, a reference clock generation circuit is illustrated. In this circuit, the high level of φ1 causes the charge provided from node 12 to be stored on node 38 and then transferred to drive node 19 via transistor 39 when needed. The gate of the transfer transistor 39 has a node 40 connected to Vdd via a transistor 41 driven by φ1.
Connected to. Node 40 is also connected to ground through transistor 42. The gate of transistor 42 is connected to node 26. The capacitive element 43 functions as a boot for the voltage of the node 40 when the driving node 19 starts to become high level. The booting capacitive element 32 is connected to the node 19 in FIG.
8 is connected.

In the circuit of FIG.

[Outside 9] When the input clock φ1 goes high, the node 38 is charged through the decoupling transistor 21 because the node 22 is precharged when goes high. When the node 38 is charged, the capacitive element 32 is also charged. Since node 26 is precharged to Vdd-Vt by transistor 25, node 40 is held at ground potential through transistor 42. After being delayed by the delay circuit, this node 26 goes low and φ1
Becomes high level, the node 40 and the capacitive element 43
Will be charged to Vdd-Vt via the transistor 41. Node 22 follows the state of node 26 after a very long delay equal to the delay Δt in transistor 29. Since node 40 goes to Vdd-Vt, the charge from node 38 will be sent to drive node 19 through transistor 39. At the same time transistors 17 and 30
Turns off and the voltage rises at nodes 31 and 18.
When the voltage of the node 31 rises, the node 38 becomes the capacitive element 3
It is booted to a potential higher than Vdd through 2 through 2. This charge is transferred onto node 19 via transistor 39. When the voltage at nodes 31 and 19 rises, node 40 is booted through capacitive element 43, which improves the conductivity of transistor 39, which equalizes the voltages at nodes 38 and 19.

The electric charge wasted by this operation is only the current passing through the transistor 41, and this current is very small because it drives only the gate of the transistor 39 and the capacitive element 43. Since the resistor divider is no longer in operation, the occurrence of a "front porch" in the output waveform can be completely prevented. This allows the prior art circuit to
In order to maintain a suitable zero level, a ratio between the first and last devices had to be maintained, but in this reference example the device size of transistors 17 and 30 is the same as the first device 16, 20. You don't have to worry about the size of.

Referring to FIG. 5A, transistor 45 is connected to node 13 and the gate of this transistor is clocked.

[Outside 10] Is connected to provide an interlocking circuit with another clock. All remaining circuits are exactly the same as in FIG. In this way, as shown in FIG. 5B,

[Outside 11] Is delayed by one timing after node goes low
2 can be pulled down to provide another interlocking control. clock

[Outside 12] Is after φ1 and is effectively

[Outside 13] Occurs before.

A second advantage of the circuit of this reference is that only one type of transistor is needed. That is, instead of transistors with several different thresholds, such as the "neutral" enhancement and depletion types, which require several injections in the manufacturing process, the circuits of FIGS. 3 and 4 provide a + 5V supply. Only standard enhancement type transistors with a threshold of about + 0.8V for voltage are used. As a result, the cost required for the manufacturing process can be reduced.

In order to drive the load capacitance element having a given value, the clock circuit of the present invention is compared with the conventional circuit.
It has also been found that requiring 0% reduced power is sufficient.

Referring to FIG. 6, there is illustrated a clock generation circuit of an embodiment of the present invention in the form used in a VLSI type semiconductor memory device. Typically this device is a 256K bit dynamic read / write memory using the one-transistor cell generally shown in the above-referenced US Pat. No. 4,239,993. As with the above reference example, a number of high level clocks must be generated on the chip. The clock voltage should drive a capacitive element of approximately 50 to 100 pfd at a voltage level that is at or near the supply Vdd. The timing delay time is preferably on the order of nanoseconds. U.S. Pat. No. 4,23
9,990 and 4,239,991 show general forms of clock generator circuits used in the memory device of US Pat. No. 4,239,993.

In FIG. 6, the basic low level clock φ
Is the corresponding precharge clock

[Outside 14] Together, it drives two push-pull input stages consisting of a pair of transistors 10 and 11. These clock voltages are shown in FIG. Clock in general

[Outside 15] Is a precharge cycle clock, while clock φ is

[Outside 16] Or one of the active cycle clocks derived from one of the inputs to the device such as chip select. Input stage 1
The voltages at output nodes 12 and 13 provided by 0 and 11 are used to drive the circuits that control the gates 14 and 15 of the two large push-pull output transistors 16 and 17 to produce a high level output on node 18. is doing. When the φ clock causes the gate 15 to go high, the node 18 drops to the Vss level due to the transistor 17 conducting. Nodes 12 and 13 also

[Outside 17] Kept at a low level by. When φ becomes high level as shown in the timing chart of FIG. 7, the gate 14, which is also the node of the gate of the transistor 20, is charged to Vdd−Vt through the decoupling transistor 21. Since the gate of this transistor is at Vdd, node 19
Will be charged but isolated from the input. Then node 22 (also gate 15) is discharged and transistor 1
The gate 14 of node 6 is provided with a sufficient drive voltage to provide an appropriate high level output to node 18
9 is booted above Vdd. Clock as shown in Figure 7

[Outside 18] When the voltage goes high, Vd is applied to the transistor 23 and the gate.
Node 19 is discharged by a series connected transistor 24 having d. This portion of the circuit is an important part of this embodiment because during the time node 19 is at a level above Vdd, the gate oxide of transistor 23 must be protected from excess voltage which is prone to failure by breakdown. Is. This is especially important when the insulating oxide, as required when scaled to VLSI devices, is about 200Å, which is very thin. When this part is operated above the nominal supply voltage and temperature, the pressure on the gate oxide increases,
This reduces reliability and performance. A device 2 connected in series with the transistor 23 in order to reduce the effect of an electric field on the gate oxide of the transistor 23.
4 causes a portion of the voltage on node 19 to drop, so that the electric field is at ground potential at a lower voltage than node 19 as shown in FIG. A single node that serves as a path for discharging does not have a voltage higher than Vdd passing through the node. That is, the voltage at node 25 will never be higher than Vdd-Vt, and the voltage between nodes 19 and 25 will never be higher than Vdd-Vt.

The node 22 in FIG.

[Outside 19] Node 26 is precharged to Vdd-Vt by transistor 26 when is high, so node 27 is precharged as well.

[Outside 20] During this period, the node 13 is maintained at a low potential and the transistor 2
8 and 29 are off

[Outside 21] These nodes remain high when is at ground potential. The next time .phi. Goes high, node 13 goes high, and after a predetermined delay period, node 22 will turn on transistor 28 as described in U.S. Pat. No. 4,239,990.
And 29 to be discharged. This turns off transistor 30, causing the voltage at node 19 to go to transistor 2
Since it is driven by φ through 1 and the transistor 20 is turned on, the node 31 reaches Vdd. When node 31 goes to Vdd, node 19 is booted by capacitive element 32 until it goes above Vdd.

The transistor 33 is at its gate

[Outside 22] This transistor terminates the output pulse at node 18 upon receipt of the clock. This same clock

[Outside 23] Discharges the booted node 19 as described above.

Another embodiment of the present invention is shown in FIG. In this, all the circuits before the transistors 16 and 17 are the same as those in FIG. In addition, a booting voltage input by the capacitive element 35 is added. Clock by adding this

[Outside 24] Serves to boot the output voltage on node 18 to a level above Vdd. This type of booted clock is described in the above-mentioned US Pat. No. 4,239,993 x-
Used for address voltage. clock

[Outside 25] Is just a slight delay of the output voltage on node 18 and is derived from that output voltage. This delay is much shorter than the amplitude of the output voltage on node 18 shown in FIG. Transistor 3 in series to prevent excessive pressure on the gate oxide of transistor 17.
The gate of 6 is set to Vdd. The pure electric field appearing in the gate oxide of transistor 17 is therefore below Vdd-Vt. Transistors 36 and 17 are of sufficient size to generate a suitable zero level while pre-discharging capacitive element 32 if necessary.

By providing the clock oscillating circuit having the above-mentioned configuration, it is possible to minimize the waste of power and the decrease in the operation processing speed, maintain the zero level, and set appropriate conditions for other circuits. be able to. Further, this structure is advantageous in that it eliminates defects caused by the formation of an electric field in the insulating oxide that occurs when the device is constituted by a field effect transistor and a device similar thereto. These benefits of the present invention are
We believe it is essential for the clock generation circuit used in the device.

Although the present invention has been described with reference to the described embodiments, this description is not intended to be limiting in spirit. Various modifications of the described embodiment, as well as other embodiments of the invention, will be apparent from this description. Therefore, it is believed that the appended claims cover all modifications and embodiments that come within the true spirit of the invention.

The following items are further disclosed in connection with the above description.

(1) Connected between an input node and a holding node, and an input transistor, a transfer transistor, a ground transistor, a control transistor, a drive transistor and a hold-down transistor each having an electric path of source / drain and a gate. The source-drain electrical path of the input transistor and the source-drain of the transfer transistor connected between the holding node and the drive node and means for precharging the gate of the input transistor before applying the clock input voltage. An electrical path and a gate of the control transistor connected to the control node and a source-drain electrical path of the control transistor connecting the control node to the supply voltage and a gate of the control transistor connected to receive the clock input voltage Source-drain electrical path of the grounding transistor connecting the control node to ground and the gate of the grounding transistor which is precharged before the clock voltage is applied and the source-drain electrical connection of the driving transistor connecting the output node to the supply voltage. Gate of the drive transistor connected to the drive path and the drive node, and an electrical path of the source-drain connecting the output node to the ground, the gate of the hold-down transistor precharged before the clock input voltage is applied, and the delay period. After a delay period after the input clock voltage is applied to an input node having a holddown transistor and a delay means grounded to pull down the voltage of the gate of the ground transistor, a high level output clock voltage is provided to the output node after a delay period. Clock generator circuit.

(2) The circuit according to the first paragraph, wherein the circuit has a capacitance means for connecting the output node to the holding node so as to boot the voltage of the bolding node when the voltage of the output node rises.

(3) The circuit according to the first item, which has capacitance means for connecting the drive node to the control node for booting the voltage of the control node when the voltage of the drive node rises.

(4) In the above circuit, the circuit according to the first paragraph, which performs the function of lowering the voltage of the gate of the ground transistor just before the delay means lowers the voltage of the gate of the hold-down transistor.

(5) In the above circuit, the delay means is also connected to reduce the voltage of the gate of the input transistor after the delay.

(6) The circuit according to item 1, wherein all the transistors in the circuit are insulated gate field effect transistors having the same threshold voltage formed on a single integrated circuit.

(7) An input transistor in which each transistor has a source-drain electrical path and a gate,
Source-drain electrical path connected between the input node and the holding node and having the transfer transistor, the ground transistor, the control transistor, the drive transistor and the hold-down transistor, and the gate of the input transistor before the clock input voltage is applied. A source connected between the holding node and the driving node, and an input transistor having a means for precharging
A control having a transfer transistor having a drain electrical path and a gate connected to a control node, a source-drain electrical path connecting the control node to a supply voltage, and a gate connected to receive a clock input voltage. A ground transistor having a transistor and a source-drain electrical path connecting the control node to ground and a gate that is precharged before the clock input voltage is applied and a source-drain electrical connection connecting the output node to the supply voltage. Holddown having a drive transistor having a path and a drive transistor connected to the drive node, a source-drain electrical path connecting the output node to ground, and a gate precharged before the clock input voltage is applied. Delay after generation of transistor and clock input voltage After a period of time, the input clock voltage is applied to the input node in a dynamic read / write semiconductor memory device or similar device having a hold-down transistor and a delay means connected to pull down the voltage of the gate of the ground transistor. After a delay period after
A clock generation circuit that provides a high level output clock voltage to an output node.

(8) The circuit according to item 7, wherein the circuit has a capacitance means for connecting the output node to the holding node and booting the voltage of the holding node when the voltage of the output node rises.

(9) The circuit according to item 7, wherein the circuit has a capacitance means for connecting the drive node to the control node and booting the voltage of the control node when the voltage of the drive node rises.

(10) The circuit according to the seventh paragraph, wherein the delay means functions to pull down the gate of the ground transistor just before the voltage of the gate of the holddown transistor is pulled down in the above circuit.

(11) The circuit according to item 7, wherein the delay circuit is also connected to lower the voltage of the gate of the input transistor after the delay period in the circuit.

(12) The circuit according to item 7, wherein all the transistors in the circuit are insulated gate field effect transistors having the same threshold voltage formed in a single integrated circuit.

(13) An output transistor, an input transistor, a decoupling transistor and a pair of discharge transistors, each having a source-drain electrical path and a gate, and a clock input voltage connected to the gate of the transistor input transistor. A source-drain electrical path of the input transistor connected between the voltage supply and the input node; and means for connecting the source-drain electrical path of the decoupling transistor in series between the input node and the output transistor. The gate of the decoupling transistor connected to the voltage supply, the source-drain electrical path of the output transistor connected between the voltage supply and the output node, and the delay period in response to the clock voltage input. The voltage of the output transistor above the voltage level higher than the supplied power 1 near the reference potential having a discharge clock voltage and an electric path of a source-drain connected in series of a pair of discharge transistors connected between the gate of the output transistor and the gate of the output transistor and the reference potential. A discharge transistor having a gate and the other discharge transistor having the supply voltage, the discharge clock voltage having a means for discharging the gate of the output transistor generated after the voltage of the output transistor is increased. A clock generation circuit that generates a high-level clock voltage.

(14) The circuit according to item 13, wherein the transistor in the circuit is an insulated gate field effect transistor formed in an integrated semiconductor device.

(15) In the above circuit, the booting means are first and second transistors each having a source-drain electrical path and a gate, and the source-drain electrical path is the The first transistor is connected in series between the supply voltage and the reference potential, the gate of the first transistor is connected to the gate of the output transistor, and the second transistor is connected to the gate of the output transistor.
Of the first and second transistors and the source-drain electrical paths of the first and second transistors connected to turn off after the input clock goes high. A circuit according to paragraph 14, having a capacitance means for connecting a node between them to the gate of the output transistor.

(16) The circuit has a third transistor, and the gate of the second transistor is connected to the gate of the third transistor in the circuit.
The circuit of paragraph 15 wherein the source-drain electrical path of said transistor is connected between said output node and a reference potential.

(17) An output transistor and a pair of discharge transistors, each of which has a source-drain electrical path and a gate, and connecting means for connecting the input node to the gate of the output transistor and the voltage supply and Means for booting the voltage at the gate of the output transistor to a voltage level higher than the supply voltage after a delay period responsive to the source-drain electrical path of the output transistor connected to the output node and the clock input. A source-drain electric path connected in series between the pair of discharge transistors connected between the output transistor and the reference potential, and a gate of the discharge transistor connected near the reference potential having a discharge clock voltage. With the gate of the other discharge transistor having the supply voltage above The discharge clock voltage generates a high level clock voltage at the output node in response to an input clock applied to the input node having a means for discharging the gate of the output transistor generated after the gate of the output transistor is boosted. Clock generator circuit.

(18) The circuit according to item 17, wherein the transistor is an insulated gate field effect transistor formed in an integrated semiconductor device.

(19) In the above circuit, the means for booting is the first and second transistors each having a source-drain electric path and a gate, and the source-drain.
The drain electrical path is connected in series between the supply voltage and the reference potential, the gate of the first transistor is connected to the gate of the output transistor, and the gate of the second transistor is high in the input clock. A node between the source and drain paths of the first and second transistors and the first and second transistors, which are connected to turn off after reaching a level, is connected to the gate of the output transistor. The circuit of paragraph 18.

(20) In the circuit, the circuit has a third transistor, the gate of the second transistor is connected to the gate of the third transistor, and the source-drain electrical path of the third transistor is connected. The circuit according to paragraph 19, which is connected between the output node and a reference potential.

(21) A second transistor connected in series between the boosting node and the source-drain electrical path of the discharge transistor, the second transistor having a gate connected to the supply voltage. A circuit for discharging the boosting node by the discharge transistor without applying a voltage level higher than the supply voltage to the electric path from the gate to the source-drain of the discharge transistor having the above-mentioned.

[Brief description of drawings]

FIG. 1 is an electrical circuit diagram of a clock generation circuit according to the prior art.

FIG. 2 is a timing diagram showing the voltages appearing at various nodes of the circuit of FIG. 1 as a function of time.

FIG. 3 is an electrical circuit diagram of a clock generation circuit of a reference example.

FIG. 4 is a timing diagram showing the voltages appearing at various nodes of the circuit of FIG. 3 as a function of time.

5A is a circuit diagram of another reference example of the circuit of FIG. 5B is a timing diagram showing the voltage versus time of some signals of the circuit of FIG. 3 to which the circuit of FIG. 5A is applied.

FIG. 6 is an electrical circuit of a clock generation circuit according to an embodiment of the present invention.

7 is a timing diagram showing the voltage for various nodes of the circuit of FIG. 6 as a function of time.

8 is a circuit diagram similar to FIG. 6 according to another embodiment of the present invention.

[Explanation of symbols]

 10, 11 Input transistor 16 Output transistor 17 Pull-down transistor 27, 32, 43 Capacitance element 39 Transfer transistor

Claims (1)

[Claims] 1. A clock generation circuit for generating a high-level clock voltage, the clock generation circuit comprising an output transistor, an input transistor, a decoupling transistor, and a discharge circuit including a discharge transistor and a protection transistor. Each of the transistors has a source-drain path and a gate, and the input transistor has a source-drain path connected between a supply voltage and an input node, the gate of which receives the input clock voltage. Connected, the source-drain path of the decoupling transistor is connected in series between the input node and the gate of the output transistor, the gate of which is connected to the supply voltage, and the output transistor is Its source-drain path is between the supply voltage and the output node The clock generation circuit further comprises means for booting the gate of the output transistor to a voltage higher than the supply voltage after the state of the input clock voltage changes, the boot means together with the decoupling transistor. The discharge circuit is directly coupled to the gate of the output transistor and discharges the gate of the output transistor according to the state change of the discharge clock voltage that occurs after the gate of the output transistor is booted. A clock generation circuit connected to a reference potential, wherein the gate of the discharge transistor receives the discharge clock voltage and the gate of the protection transistor is connected to the supply voltage.