JPH0787378B2 - Delta modulator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delta modulator of an analog-digital converter which has reduced distortion.

2. Description of the Related Art A delta modulator is a type of analog-to-digital converter, and pays attention to the difference between each sample when sampling at regular time intervals, encodes this information, and is generated due to this encoding. The quantization error is corrected by subsequent samples.

Hereinafter, the conventional delta modulator as described above will be described with reference to the drawings. FIG. 3 is a block diagram showing the configuration of a conventional delta modulator. Generally, a delta modulator has an analog signal input terminal 201, as shown in FIG.
It is composed of a subtractor 202, a comparator 203, a local demodulator 204, and a delta modulation signal output terminal 205, and whether the potential increases compared with the potential sampled one sampling period before the analog input signal,
The information indicating whether the number is decreasing is output by a 1-bit code.

The analog signal input to the analog signal input terminal 201 is input to the subtractor 202. The subtractor 202 is a local demodulator 20 which is the analog signal and a potential sampled one sampling period before.
The difference from the output of 4 is obtained and output to the comparator 203. Comparator 203
If the signal input to is larger than a certain reference potential, the analog input signal is increasing, and the comparator 203 outputs "1" to the delta modulation signal output terminal 205. Comparator 2
If the signal input to 03 is smaller than the reference potential, the analog input signal has decreased, and the comparator 203 outputs "0" to the delta modulation signal output terminal 205. The codes of "1" and "0" become the delta modulation signal. On the other hand, the local demodulator 204 demodulates the delta modulation signal output from the comparator 203 and outputs an analog signal to the subtractor 202.

FIG. 4 is a circuit diagram showing an example of the above-mentioned conventional delta modulator. The analog signal input from the analog signal input terminal 206 has a direct current component removed through a capacitor 207, and is output from a local demodulator 215 through a resistor 208 to a resistor 209.
Is added to the signal passed through and D of the D flip-flop 213 is added.
Input to the terminal. However, since the inverted output (NQ terminal) of the D flip-flop 213 is used for the input of the local demodulator 215, the resistors 208 and 209 have the same effect as the subtractor. Next, the D flip-flop 213 compares the analog input signal with the potential sampled one sampling period before according to the input potential. If the potential of the D terminal is higher than the threshold level, "1" is output to the Q terminal and "0" is output to the NQ terminal. If the potential of the D terminal is lower than the threshold level, "0" is output to the Q terminal and "1" is output to the NQ terminal. The signal output from the Q terminal of the D flip-flop 213 is a delta modulation signal and is output to the delta modulation signal output terminal 214. On the other hand, the “1” and “0” inverted delta modulation signals output from the NQ terminal are input to the local demodulator 215. The local demodulator 215 has a resistor 211 and a capacitor 210.
The capacitor 210 is charged and discharged through the resistor 211 by inputting the potentials corresponding to “1” and “0”.
When the time constant τ of the resistor 211 and the capacitor 210 is much larger than the sampling period T, the local demodulator 215 becomes an integrating circuit and the integrated result is the inverted potential of the analog input signal sampled one sampling period before. Become.

However, the conventional delta modulator described above has a problem that distortion occurs due to the characteristics of the D flip-flop. The occurrence of distortion will be described below.

FIG. 5 shows (a) a clock signal when the analog input signal is zero, (b) a D terminal input signal of an ideal delta modulator D flip-flop, and (c) an ideal delta modulator D flip-flop. Output signal of the Q terminal of the above, (d) D terminal input signal of the D flip-flop in the conventional delta modulator (point B in FIG. 4), (e) Output of the Q terminal of the D flip-flop in the conventional delta modulator It is a wave form diagram which shows an example of a signal (point C in FIG. 4). When the analog input signal is zero, the output delta modulation signal ideally repeats "1" and "0" at each rising edge of the clock signal supplied to the D-flop flop as shown in FIG. 5 (c). Become a signal. When the input signal of the D terminal of the D flip-flop is higher than the threshold level V _TH at the rising edge of a certain clock, “1” is output from the Q terminal and “0” is output from the NQ terminal. It When "0" is output from the NQ terminal, the local modulator discharges with a time constant determined by the resistance and capacitor of the local demodulator, and the input signal at the D terminal of the D flip-flop begins to fall and has a potential lower than V _TH. Becomes At the next rising edge of the clock, since the potential of the D terminal of the D flip-flop is lower than V _TH, "0" is output from the Q terminal and "1" is output from the NQ terminal. When "1" is output from the NQ terminal, the local demodulator is charged, and the input potential of the D terminal of the D flip-flop begins to rise and becomes higher than V _TH . Due to such repetition, the Q of the D flip-flop is ideally operated.
“1” and “0” are repeatedly output from the terminal.

However, in the conventional D flip-flop, in the actual D flip-flop, there is a delay Δt from the rising of the clock signal to the output to the Q terminal or the NQ terminal, so that the D flip-flop from the D terminal of the delta modulation signal The condition that 1 "and" 0 "are not output alternately occurs. As shown in FIG. 5 (d), when the input signal of the D terminal of the D flip-flop is higher than the threshold level V _TH at the rising edge of a certain clock, the delay Δt
"0" after being delayed by Δt from the NQ terminal due to the existence of
Is output. Therefore, the potential of the input signal at the D terminal of the D flip-flop begins to drop with a delay of Δt. At this time, even when the next clock rises, a state occurs in which the input signal of the D terminal is still higher than V _TH . When the input signal of D terminal is higher than V _TH, it becomes N again.
"0" is output from the Q terminal, and the potential of the D terminal continues to drop. At the rising edge of the next clock, the input signal at the D terminal becomes lower than V _TH and "1" is output from the NQ terminal with a delay of Δt. However, at the rising edge of the next clock, "1" is output again due to the delay Δt. "Is output from the NQ terminal. That is, in the D flip-flop, there is a delay from the rising of the clock to the output to the NQ terminal, so the output of the Q terminal which is a delta modulation signal is "1", "0"
Does not alternate, but repeats like "1", "1", "0", "0", which is not ideal operation.

In the above example, the case where the analog input signal is zero has been described, but when the input signal is not zero, this “1”, “1”,
Repetition of "0" and "0" causes distortion. When the potential at the point A in the circuit diagram of the conventional delta modulator of FIG. 4 is close to the threshold level V _TH of the D flip-flop 213, “1”, “1”, “0”, “0”. Is likely to occur, and a sine wave is input to the analog signal input terminal using a D flip-flop of 5V when the power supply voltage is 5V, V _TH 2.5V, NQ terminal output is "1" and 0V when it is "0". If you enter
At point A, the point at which the absolute value of the slope of the sine wave is the largest is the potential of 2.5 V, so that distortion occurs at this point and second-order harmonic distortion occurs in the delta modulation signal.

The present invention solves such conventional problems and provides a high-performance delta modulator in which distortion is reduced.

In order to achieve this object, the delta modulator of the present invention has a DC voltage level of the output signal of the offset circuit between the analog signal input terminal and the comparator, and a DC voltage level of the output signal of the local demodulator. The DC offset is controlled to be higher than the voltage level.

The present invention has the above-described configuration, by controlling the DC offset, the absolute value of the slope when the potential of the input signal of the comparator rises is made different from the absolute value of the slope when the potential falls, and the input signal of the comparator is changed. When the potential is decreasing, the absolute value of the slope is small and the comparator input signal becomes high potential with respect to the comparator reference potential several times in succession. Therefore, even if the comparator outputs “1” continuously due to delay, the delta modulation signal is originally “1” several times continuously, so the relative error due to one continuous is small. Therefore, the strain generation becomes small.

When the potential of the input signal of the comparator is rising, the absolute value of the slope becomes large, the probability of becoming higher than the reference potential of the comparator between the sampling period and the delay becomes high, and “ The probability of outputting 0 "decreases. Therefore, the occurrence of distortion can be reduced, and a high-performance delta modulator can be realized.

Example Hereinafter, a delta modulator according to an example of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a delta modulator according to an embodiment of the present invention. Since the delta modulator of this embodiment shown in FIG. 1 has basically the same configuration as the conventional delta modulator, the same components are designated by the same reference numerals and detailed description thereof will be omitted.

In FIG. 1, 207 is a capacitor for removing the DC component of the analog input signal, and 101 is a DC offset control for making the DC voltage level of the analog input signal higher than the DC voltage level of the output signal of the local demodulator 215. A resistor, 102 is a DC voltage source, and 103 is a bias circuit.

Like the conventional delta modulator shown in FIG. 4, the embodiment of the present invention also adds the output of the local demodulator 215 and the analog input signal. However, since the resistor 101 and the DC voltage source 102 exist. A current flows through the resistors 208 and 209, and the local demodulator 215 is charged and discharged by the capacitor 210 of the local demodulator 215.
The absolute value of the slope of the change over time when the output potential of increases and decreases. That is, D of the D flip-flop 213
Regarding the input potential of the terminal, the absolute value of the slope when it rises is large, and the absolute value of the slope when it descends is small.

FIG. 2 is an example of (a) a sampling clock signal of a comparator, (b) a comparator input signal, and (c) an output delta modulation signal when the analog input signal in the delta modulator of this embodiment is zero. It is a waveform diagram showing. As can be seen from FIG. 2 (b), by controlling the DC offset, the absolute value of the slope when the potential of the comparator input signal rises and the absolute value of the slope when it falls are different. When the potential of the comparator input signal is falling, the absolute value of the slope is small and the comparator input signal becomes high potential with respect to the comparator reference potential several times in succession. Therefore, even if the comparator outputs “1” continuously due to delay, the delta modulation signal is originally “1” several times continuously, so the relative error due to one continuous is small. Therefore, the strain generation becomes small. In addition, when the potential of the comparator input signal rises, the absolute value of the slope increases and the probability of becoming higher than the comparator reference potential during the sampling period T and the delay Δt (T−Δt) increases. The probability of outputting "0" continuously decreases. Therefore, the occurrence of distortion due to the delay of the D flip-flop 213 can be reduced, and a high-performance delta modulator can be realized.

As described above, by controlling the DC bias of the analog input signal, it is possible to obtain a high-performance delta modulator with reduced distortion.

In this embodiment, the bias of the analog input signal is controlled by connecting to the constant voltage source via the resistor 101 immediately after the capacitor 207 for removing the DC component of the analog input signal, but the D terminal input part of the D flip-flop 213 is controlled. Even if the bias control is performed by connecting to a constant voltage source via a resistor, the same effect can be obtained.

EFFECTS OF THE INVENTION As described above, the delta modulator of the present invention can reduce the distortion generated due to the delay characteristic of the element by the offset circuit that controls the DC offset of the analog input signal. .

[Brief description of drawings]

FIG. 1 is a circuit diagram of a delta modulator in one embodiment of the present invention, FIG. 2 is (a) a sampling clock signal when the analog input signal is zero, and (b) a D flip-flop of the delta modulator of the present invention. D terminal input signal of the delta modulator, (c) Waveform diagram of the Q terminal output signal of the D flip-flop of the delta modulator of the present invention, FIG. 3 is a block diagram showing a conventional delta modulator, and FIG. 4 is a conventional example. FIG. 5 is a circuit diagram of the delta modulator. FIG. 5 shows (a) a sampling clock signal when the analog input signal is zero, (b) an ideal D terminal input signal of a D flip-flop of the delta modulator, and (c) an ideal signal. Delta Modulator D
FIG. 6 is a waveform diagram of a Q terminal output signal of a flip-flop, (d) a D terminal input signal of a D flip-flop of a delta modulator in a conventional example, and (e) a Q terminal output signal of a D flip-flop of a delta modulator in a conventional example. . 101: Offset circuit resistor, 102: DC voltage source, 20
6 ... Analog signal input terminal, 212 ... Sampling clock input terminal, 213 ... D flip-flop, 214 ... Delta modulation signal output terminal, 215 ... Local demodulator, 201 ... Analog signal input terminal, 202 ... … Subtractor, 203… Comparator, 204…
... Local demodulator, 205 ... Delta modulation signal output terminal, T ...
… Sampling clock cycle, V _TH …… D flip-flop threshold level, Δt… D flip-flop clock = NQ delay time.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP 48-6609 (JP, A) JP 1-123531 (JP, A) JP 63-246034 (JP, A) JP 1- 273426 (JP, A) JP47-40661 (JP, B1) JP52-14073 (JP, B2)

Claims (1)

[Claims] 1. An offset circuit for controlling a DC offset of an analog signal, a subtractor for taking a difference between an output of the offset circuit and a local demodulation signal, and a comparison for sampling an output of the subtractor and converting it into a delta modulation signal. And a local demodulator for demodulating the output of the comparator into an analog signal, the analog signal so that the DC voltage level of the output signal of the offset circuit is higher than the DC voltage level of the output signal of the local demodulator. A delta modulator characterized by controlling the DC offset of.