JPH0786900A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Problem] To provide a semiconductor device having an output circuit with high performance, multifunction, and low power consumption. [Structure] A plurality of output circuit units 1 are connected in parallel. The characteristic variation amount detection circuit 2 detects the amount of characteristic variation of the elements forming each output circuit unit 1. The correction control circuit 3 controls the number of operating output circuit units 1 based on the detection result of the characteristic variation amount detection circuit 2. Therefore, the number of operating output circuit units 1 is controlled according to the amount of characteristic variation of the elements forming each output circuit unit 1. Therefore, the total sum of the output currents of the output circuit sections 1 becomes constant regardless of the characteristic variation of the elements forming the output circuit sections 1. As a result, it is possible to always obtain an ideal output current characteristic regardless of the characteristic variation of the element, and it is possible to reduce noise generated due to an excessive output current flowing. In addition, the slew rate can be controlled by adjusting the signal delay time of each output circuit unit 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an output circuit.

In recent years, semiconductor devices are required to have higher performance, higher functionality, and lower power consumption. In order to meet such demand, an output circuit with higher performance, more functions, and lower power consumption is required.

[0003]

2. Description of the Related Art As semiconductor devices have become more multifunctional and have lower power consumption, there are an increasing number of examples in which a plurality of circuits having different operation levels are mixed to form one device.

To connect circuits having different operation levels,
Although it is necessary to provide an interface for level conversion, there are a method of using this interface as an independent circuit and a method of giving an output circuit an interface function.

In the method of (1), conventionally, a plurality of interfaces having different operation levels (conversion levels) are provided in advance, and an interface having a required operation level is selected and used.

Therefore, when the number of transfer circuits (the number of channels) increases due to the high performance and multi-functionalization of semiconductor devices, interfaces having different operation levels are required for each of the transfer circuits. However, since not all the transfer circuits are used, the number of unused interfaces also increases as the number of transfer circuits increases. Then, the power consumption increases by the unused interface. Also, since the chip area increases by the area where the unused interface is formed,
This also hinders high integration of semiconductor devices.

[0007] Further, due to the higher performance and multi-functionality of semiconductor devices, the number of cases where three or more operation levels coexist in one device is increasing. In that case, the above problem becomes more prominent. It will be.

On the other hand, also in the above method, conventionally, a plurality of output circuits having different operation levels (output levels) are provided in advance, and the output circuit having a required operation level is selected and used. Specifically, a plurality of CMOS inverters having different power supply voltages are provided in advance. Then, a CMOS inverter having a power supply voltage corresponding to a required output level is selected and used as an output circuit. Therefore, the method (1) also causes the same problem as that of the method (1).

Further, due to the higher performance of semiconductor devices, it has become necessary to increase the operating speed (higher operating frequency).
In order to cope with this, the method of (1) requires an interface having a high driving capacity, and the method of (2) requires an output circuit having a high driving capacity. By the way, also in the interface, it is the output section that determines the driving capability, and the output section is generally composed of a CMOS inverter. Therefore, the method (1) still requires an output circuit having a high driving capability, as in the method (1).

However, unnecessarily increasing the driving capability of the output circuit causes malfunction of the device. That is, when the driving capability of the output circuit is increased and an excessive output current flows in a short time, noise is generated due to fluctuations in the ground (low-potential-side power supply) level. This noise increases as the number of output circuits increases, so
When the number of transfer circuits increases as described above, the number of transfer circuits becomes extremely large and causes malfunction of the device.

Further, in general, the output circuit is made with a considerable margin with respect to the IOL standard (the standard of the minimum value of the output current) in consideration of the variation in the manufacturing process and the characteristic variation of the transistor due to the temperature condition. There is. That is, the output circuit is designed to obtain an output current that is equal to or higher than the IOL standard even when the characteristics of the output circuit deteriorate due to variations in the characteristics of the transistor. Therefore, when there is no characteristic variation of the transistor (in the case of normal characteristic) or when the characteristic is improved due to the characteristic variation, an unnecessarily large output current flows. Then, the above-mentioned problem of noise becomes more prominent.

[0012]

As described above, the above-mentioned problems have become apparent in the output circuit due to the high performance, multi-functionality, and low power consumption of the semiconductor device.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having a high-performance, multi-functional and low-power-consumption output circuit.

[0014]

According to a first aspect of the present invention, a CMOS inverter, MOS transistors connected between a plurality of high potential side power supplies having different voltages and the CMOS inverter, and MOS transistors thereof are provided. The gist of the invention is to have a control circuit for turning on only one of the transistors.

According to a second aspect of the present invention, each PMOS transistor connected to a plurality of high-potential-side power supplies having different voltages, an NMOS transistor in which the PMOS transistor and the drain are connected to each other, and each of the PMOS transistors are connected. Each of the pull-up resistors for pulling up the gate to the corresponding high-potential-side power supply side, and the selection connecting means for selecting the gate of any one of the PMOS transistors and connecting it to the gate of the NMOS transistor are provided. That is the summary.

FIG. 1 is a diagram for explaining the principle of the invention described in claim 3. A plurality of output circuit units 1 are connected in parallel. The characteristic variation amount detection circuit 2 detects the amount of characteristic variation of the elements forming each output circuit unit 1. The correction control circuit 3 controls the number of operating output circuit units 1 based on the detection result of the characteristic variation amount detection circuit 2.

According to the invention described in claim 4, the signal delay time of each output circuit section 1 is set to a different value. FIG. 2 is an explanatory view of the principle of the invention described in claim 7.

Each interface 14 has an input circuit 11
And a level conversion circuit 12 and an output circuit 13. The plurality of interfaces 14 are connected in parallel. The register 15 controls each of the interfaces 14.

[0019]

Therefore, according to the first aspect of the present invention, when the control circuit turns on one MOS transistor, the voltage of one high-potential-side power supply is supplied to the CMOS inverter via the MOS transistor. It Therefore, the CMOS inverter functions as an output circuit having the high-potential-side power supply voltage as the output level.

According to the second aspect of the present invention, the selection connecting means selects the gate of one PMOS transistor and connects it to the gate of the NMOS transistor to form a CMOS inverter. The CMOS inverter is supplied with the voltage of the high-potential-side power supply to which the PMOS transistor is connected. Therefore, the CM
The OS inverter functions as an output circuit whose output level is the power supply voltage on the high potential side.

According to the third aspect of the present invention, the number of operating output circuit units 1 is controlled according to the characteristic variation amount of the elements forming each output circuit unit 1. Therefore, the total sum of the output currents of the output circuit sections 1 becomes constant regardless of the characteristic variation of the elements forming the output circuit sections 1. As a result, it is possible to always obtain an ideal output current characteristic regardless of the characteristic variation of the element, and it is possible to reduce noise generated due to an excessive output current flowing.

Further, according to the invention described in claim 4, since the signal delay time of each output circuit section 1 is set to a different value, the slew rate can be controlled by adjusting the signal delay time. become.

According to the seventh aspect of the present invention, each interface 14 is controlled by the register 15, and each interface 14 is driven in parallel, or the internal circuits 11 to 13 of each interface 14 are controlled. It is possible to provide a semiconductor device including a high-performance, multi-functional, low power consumption output circuit.

[0024]

(First Embodiment) A first embodiment embodying the invention described in claim 1 will be described below with reference to FIG.

The output circuit 51 of this embodiment comprises a CMOS inverter 52, PMOS transistors 53 and 54, and a control decoder 55. The control decoder 55 decodes the control signal to generate complementary control signals CNT1 and CNT2. The control signal is sent from inside or outside the circuit.

The source of the PMOS transistor 53 is connected to the high potential power source VDD1 and the PMOS transistor 54
Is connected to the high potential power supply VDD2. The control signal CN is applied to the gate of the PMOS transistor 53.
T1 is applied, and the control signal CNT2 is applied to the gate of the PMOS transistor 54. The drains of the transistors 53 and 54 are connected to the source of the PMOS transistor 52a forming the CMOS inverter 52. The high-potential-side power supply voltage VDD1 is set higher than the high-potential-side power supply voltage VDD2 (VDD1> VDD2).
). In addition, the NMO that constitutes the CMOS inverter 52
The source of the S transistor 52a is connected to the low potential power source VSS (ground).

Then, the internal signal of the circuit is output to the outside through the CMOS inverter 52. Therefore, the control signal
If CNT1 is at H level and control signal CNT2 is at L level, PM
The OS transistor 53 is off and the PMOS transistor 5 is
4 turns on. Then, the high-potential-side power supply voltage VDD2 is supplied to the CMOS inverter 52 via the PMOS transistor 54. Therefore, the output level of the CMOS inverter 52, that is, the output level of the output circuit 51, corresponds to the high-potential-side power supply voltage VDD2.

On the contrary, when the control signal CNT2 is at H level and the control signal CNT1 is at L level, the output level of the output circuit 51 corresponds to the high potential side power supply voltage VDD1. As described above, in the output circuit 51 of the present embodiment, the control signals from the control decoder 55 are supplied to the respective complementary control signals of appropriate levels.
By generating CNT1 and CNT2, the output level of the output circuit 51 can be switched to one corresponding to each power supply voltage VDD1 and VDD2. That is, according to this embodiment, one output circuit 51 can obtain two output levels (respective power supply voltages VDD1 and VDD2).

On the other hand, the conventional output circuit is composed of a CMOS inverter whose power supply voltage is fixed, and one output circuit can obtain only one output level. Therefore, according to the present embodiment, the number of output circuits can be reduced as compared with the conventional one. Further, in that two output levels can be obtained, the output circuit 51 of the present embodiment.
Can be said to have more functions and higher performance than conventional output circuits.

By the way, if the control signals CNT1 and CNT2 are clipped and used, the output circuit 51 of this embodiment can obtain only a single output level like the conventional output circuit. In that case, the circuit including the output circuit 51 of the present embodiment functions as a circuit having a built-in level conversion circuit.

(Second Embodiment) By the way, in the above output circuit 51, the high-potential-side power supply voltage VDD1 is set higher than the high-potential-side power supply voltage VDD2 (VDD1> VDD2). Therefore, the operation level of the internal circuit is the high-potential-side power supply voltage V
If it corresponds to DD2 (H level of internal signal =
In the case of VDD2), when the PMOS transistor 53 is turned on and the high-potential-side power supply voltage VDD1 is supplied to the CMOS inverter 52, both transistors 52a and 52b of the CMOS inverter 52 are turned on. Then, a through current flows through the path of the high potential side power source VDD1 → PMOS transistor 53 → CMOS inverter 52 → Low potential side power source VSS. That is, when the output circuit 51 is connected to an external circuit having an operation level higher than that of the internal circuit (H level of internal signal = VDD2, output level =
In the case of VDD1), there is a problem that power consumption increases due to the through current.

The invention described in claim 2 is made to solve this problem. Hereinafter, a second embodiment of the invention as defined in claim 2 will be described with reference to FIG.
In the present embodiment, the same components as those of the output circuit 51 shown in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

The output circuit 61 of this embodiment comprises a control decoder 55 and transmission gates 62 and 63.
And pull-up resistors 64 and 65, PMOS transistors 66 and 67, and NMOS transistor 68.

The source of the PMOS transistor 66 is connected to the high potential side power supply VDD1 and the PMOS transistor 67 is connected.
Is connected to the high potential power supply VDD2. Further, the gate of the PMOS transistor 66 is pulled up to the high potential side power source VDD1 by the pull-up resistor 64, and the gate of the PMOS transistor 67 is pulled up to the high potential side power source VDD2 by the pull-up resistor 65. The drains of the transistors 66 and 67 are connected to the drain of the NMOS transistor 68,
The output of the output circuit 61 is obtained from the drains of the transistors 66 to 68. The source of the NMOS transistor 68 is the low-potential-side power supply VSS (ground)
And an internal signal is applied to the gate.
An internal signal is applied to the gates of the transistors 66 and 67 via the transmission gates 62 and 63.

Then, each transmission gate 6
On and off of the reference numerals 2 and 63 are controlled by the control signals CNT1 and CNT2. For example, when the control signal CNT2 is at H level and the control signal CNT1 is at L level, the transmission gate 6
2 is on and transmission gate 63 is off. Then, the internal signal is applied to the gate of the NMOS transistor 68 and also to the gate of the PMOS transistor 66 via the transmission gate 62. In other words, each transistor 66, 68 causes C
A MOS inverter is constructed. Therefore, the internal signal is output to the outside through the CMOS inverter. Since the source of the PMOS transistor 66 is connected to the high-potential-side power supply VDD1, the output level of the CMOS inverter, that is, the output level of the output circuit 61 is
It corresponds to the high potential side power supply VDD1.

At this time, when the operation level of the internal circuit corresponds to the high-potential-side power supply voltage VDD2 (when the internal signal is at H level = VDD2), when the internal signal goes to H level, the PMOS transistor 66 is turned on. The gate is pulled up to the high potential side power source VDD1 by the pull-up resistor 64, and the PMOS transistor 66 is turned off. On the other hand, P
The MOS transistor 68 turns on. Therefore, no through current flows from the high potential side power source VDD1 to the low potential side power source VSS.

That is, according to the output circuit 61 of this embodiment, when the output circuit 61 is connected to an external circuit having an operation level higher than that of the internal circuit (H level of internal signal = VDD2
Then, even if the output level is VDD1), the output circuit 5
A through current like 1 does not flow. Therefore, the output circuit 61 of the present embodiment consumes less power than the output circuit 51.

On the contrary, when the control signal CNT1 is at H level and the control signal CNT2 is at L level, the transmission gate 6
3 is on and transmission gate 62 is off. Then, the internal signal is applied to the gate of the NMOS transistor 68 and also to the gate of the PMOS transistor 67 via the transmission gate 63. That is, each transistor 67, 68 causes C
A MOS inverter is constructed. Therefore, the internal signal is output to the outside through the CMOS inverter. Here, since the source of the PMOS transistor 67 is connected to the high potential side power supply VDD2, the output level of the CMOS inverter, that is, the output level of the output circuit 61 is
It corresponds to the high potential side power supply VDD2.

As described above, also in the output circuit 61 of the present embodiment, the control decoder 55 generates the respective control signals CNT1 and CNT2 having the appropriate levels of complementarity, so that the output level of the output circuit 61 is changed to the respective power sources. Voltage VDD1, V
You can switch to the one that supports DD2. That is, according to this embodiment, one output circuit 61 can obtain two output levels (respective power supply voltages VDD1 and VDD2).

Therefore, according to the output circuit 61 of this embodiment, the same effect as that of the output circuit 51 can be obtained. (Third Embodiment) A third embodiment of the invention as set forth in claim 3 will be described below with reference to FIGS.

FIG. 5 is a block circuit diagram of the output circuit of this embodiment. The output circuit 81 of this embodiment includes a pulse generation circuit 82, delay chains 83 and 84, a delay time detection circuit 85, an encoding circuit 86, a correction control circuit 87, auxiliary output circuit sections 88a to 88n, and a regular output circuit. It is composed of a part 89.

The pulse generation circuit 82 generates the signal DS output to the delay chains 83 and 84 and the clock CKO output to the encoding circuit 86. Each of the delay chains 83 and 84 delays the signal DS and delay time detection circuit 8
Output to 5.

As will be described later, each delay chain 8
3, 84 are composed of a plurality of CMOS inverters having the same transistor size and connected in the same number in cascade. However, for the delay chain 84,
A capacitive load is provided at the output of each CMOS inverter. Therefore, the load of the delay chain 84 is larger than that of the delay chain 83.

The load drive capability of the CMOS inverter depends on the characteristics of the transistors that form the CMOS inverter. That is, the better the characteristics of the transistor, the higher the load driving capability of the CMOS inverter. The higher the load driving capability of the CMOS inverter, the shorter the signal delay time of the CMOS inverter. Therefore, when the characteristics of the transistor deteriorate due to variations in manufacturing process or temperature conditions, the load driving capability of the CMOS inverter decreases, and the signal delay time of the CMOS inverter increases. Also, the worse the characteristics of the transistor, the greater the influence of the load on the signal delay time of the CMOS inverter. Therefore, when the characteristics of the transistor deteriorate, the signal delay time becomes longer as the load of the CMOS inverter increases.

Regarding each of the delay chains 83 and 84, the delay chain 84 is the delay chain 8
The load is heavier than 3. Therefore, in order to make the signal delay times of the delay chains 83, 84 the same, the load drive capability of each CMOS inverter forming the delay chain 84 must be higher than that of the delay chain 83. However, each delay chain 83, 84 is a CMOS of the same transistor size.
It is composed of an inverter. Therefore, the delay chain 84 has a longer signal delay time than the delay chain 83 due to the large load. further,
The change in signal delay time due to the change in transistor characteristics is
The delay chain 84 is larger than the delay chain 83 due to the larger load. That is, when the characteristics of the transistor deteriorate, each delay chain 83,
Although the signal delay times of 84 both become longer, the increase of the signal delay time of the delay chain 84 becomes larger than that of the delay chain 83.

In this way, each delay chain 83, 84
There is a difference in the signal delay time from the beginning, and the difference in the delay time becomes larger as the characteristics of the transistor deteriorate.
The delay time detection circuit 85 includes the delay chains 83 and 8
Based on the respective signals DS output from 4, the delay time difference between the delay chains 83 and 84 caused by the above causes is detected and converted into a pulse width, and the signal PS converted into the pulse width is detected.
Is output.

The encoding circuit 86 converts the signal PS converted into the pulse width into the clock CKO from the pulse generation circuit 82.
The signal CS is coded by counting by, and the coded signal CS is generated.

The correction control circuit 87 decodes the encoded signal CS and selects and operates the auxiliary output circuit portions 88a to 88n corresponding to the signal CS. Each of the auxiliary output circuit units 88a to 88n has the same circuit configuration as the regular output circuit unit 89, and is connected in parallel with the regular output circuit unit 89. Then, the internal signal of the circuit is output to each output circuit unit 8
It is output to the outside through 9,88a to 88n. Therefore, the sum of the output currents of the output circuit sections 89, 88a to 88n becomes the output current of the output circuit 81. The output current of the regular output circuit unit 89 is set so that it is at the limit of the IOL standard when the transistors forming the regular output circuit unit 89 have normal characteristics.

Next, the operation of the present embodiment thus constructed will be described. Each delay chain 83, 84 and each output circuit section 89, 88a-88n are formed in the vicinity on the chip. Therefore, when the characteristics of the transistors that form the regular output circuit unit 89 change due to variations in the manufacturing process and temperature conditions, the characteristics of the transistors that form the delay chains 83 and 84 also change.

Although the delay time difference between the delay chains 83 and 84 changes in accordance with the characteristic variation of the transistor, as described above, the delay time difference increases as the transistor characteristic deteriorates.

The delay time detection circuit 85 detects the delay time difference between the delay chains 83 and 84 and converts it into a pulse width. The pulse width is encoded by the encoding circuit 86. The correction control circuit 87 uses the encoded signal CS
Auxiliary output circuit section 8 corresponding to the signal CS
8a to 88n are selected and operated.

Therefore, as the characteristics of the transistors deteriorate and the delay time difference between the delay chains 83 and 84 increases, the number of auxiliary output circuit units 88a to 88n that operate increases.

When the characteristics of the transistor deteriorate, the output current of the regular output circuit section 89 decreases. The output current of the regular output circuit unit 89 is determined so that the standard IOL is reached when the transistors forming the regular output circuit unit 89 have normal characteristics. Therefore, when the characteristics of the transistor deteriorate, the output current of the regular output circuit unit 89 falls below the IOL standard.

However, as the characteristics of the transistor deteriorate, the number of auxiliary output circuit sections 88a to 88n that operate increases, so that the decrease in the output current of the normal output circuit section 89 is compensated. Therefore, the output current of the output circuit 81 is always kept close to the IOL standard even if the transistor characteristics deteriorate.

As a result, even when the characteristics of the transistor are deteriorated, the generation of noise due to the fluctuation of the ground (low-potential-side power supply) level due to an excessive output current flows can be minimized.

On the contrary, when the characteristics of the transistor become better than the normal characteristics, the auxiliary output circuit portions 88a to 88n do not operate. Therefore, if the transistor has normal characteristics,
The output current of the regular output circuit unit 89 becomes the output current of the output circuit 81, which is close to the IOL standard. for that reason,
Even when the transistor has a normal characteristic, the generation of the noise is suppressed to the minimum.

When the characteristics of the transistor become better than usual, the normal output current of the output circuit section 89 exceeds the IOL standard. However, the output current of the regular output circuit unit 89 is set so as to be close to the IOL standard when the transistors forming the regular output circuit unit 89 have normal characteristics. Therefore, even if the characteristics of the transistor become better than usual, the increase in the output current of the regular output circuit unit 89 is negligible.

On the other hand, in the conventional output circuit, as described above, even when the transistor has the normal characteristics, the output current exceeding the IOL standard is made to flow. for that reason,
In the conventional output circuit, when the characteristics of the transistor become better than usual, an extremely large output current will flow.

Therefore, even if the characteristics of the transistor become better than usual, the output current of the output circuit 81 of this embodiment becomes smaller than that of the conventional output circuit. Therefore, even when the characteristics of the transistor become better than usual, the output circuit 81 of this embodiment can suppress the generation of the noise as compared with the conventional output circuit.

As described above, in the output circuit 81 of the present embodiment, the characteristic variation of the transistors forming the output circuit portions 89, 88a to 88n is controlled by the delay chain 83,
It is detected by 84 and the delay time detection circuit 85. The encoding circuit 86 and the correction control circuit 87 control the number of auxiliary output circuit sections 88a to 88n that operate according to the characteristic variation of the transistor.

As a result, the output current of the output circuit 81 is kept close to the IOL standard when the characteristics of the transistor are deteriorated or in the case of the normal characteristics, and the generation of the noise is minimized. Further, even when the characteristics of the transistor become better than usual, the generation of the noise can be suppressed to a low level.

That is, according to this embodiment, an ideal output current characteristic can always be obtained regardless of variations in the manufacturing process and variations in transistor characteristics due to temperature conditions, and an excessive output current flows. The noise generated can be reduced.

By the way, in the present embodiment, the slew rate characteristic of the output circuit 81 is changed by making the signal delay time of each auxiliary output circuit section 88a to 88n longer than the signal delay time of the regular output circuit section 89. be able to. That is, the slew rate control can be performed by adjusting the signal delay time of each of the auxiliary output circuit units 88a to 88n.

Next, an embodiment in which the above embodiment is embodied up to the gate level will be described with reference to FIGS.
An example in which four auxiliary output circuit units 88a to 88d are provided is given here.

FIG. 6 is a circuit diagram in which the pulse generation circuit 82, the respective delay chains 83 and 84, the delay time detection circuit 85 and the encoding circuit 86 are embodied up to the gate level. The pulse generation circuit 82 includes a NOR 91 and an inverter 9
2- and 4-bit counter 93 and DR flip-flop 94
It is a known ring oscillator composed of and.
This pulse generating circuit 82 is provided with an external test signal TST.
It operates in accordance with the above, and generates a signal DS and a clock CKO to be output to each delay chain 83, 84. Each delay chain 83, 84 is composed of a plurality of CMOS inverters 95 of the same transistor size, which are cascade-connected by the same number. However, the capacitive load C is applied to the output of each CMOS inverter of the delay chain 84.
Is provided. The delay time detection circuit 85 is composed of an inverter 96 and an Ex-NOR 97. The encoding circuit 86 includes NORs 98 and 99, 4-bit counters 100 and 101, and 4-bit D flip-flops 10.
2, 103. Then, the encoded signal is output from each of the D flip-flops 102 and 103.
The signals P1 to P4 and N1 to N4 as CS are output.

7 and 8 are circuit diagrams in which the correction control circuit 87 is embodied up to the gate level. The correction control circuit 87 includes NORs 104 to 107 and inverters 108 to 1
11 and NANDs 112 to 115.
Then, the correction control circuit 87 uses the signals P1 to P4 and N1 to N4 from the encoding circuit 86 to control the signals L1a to L4a and H1a.
H4a, L1b to L4b, and H1b to H4b are generated.

FIG. 9 shows each auxiliary output circuit section 88a-88d.
9 is a circuit diagram in which the normal output circuit unit 89 is embodied up to the gate level. Each auxiliary output circuit section 88a to 88d
Is each CMOS inverter 116 and each NOR 117,1
It is composed of 18 and. In each NOR 117,
Each control signal L1a-L4a, H1a-from the correction control circuit 87
H4a is input. Further, the NOR 118 includes control signals L1b to L4b and H1b to H4b from the correction control circuit 87.
Has been entered. The regular output circuit section 89 is composed of a CMOS inverter 116 and an inverter 119 having the same transistor size as the CMOS inverter 116 that constitutes each of the auxiliary output circuit sections 88a to 88d. Each of the auxiliary output circuit units 88a to 88d is a regular output circuit unit 89.
And are connected in parallel. And the internal signal of the circuit is
It is output to the outside through each output circuit unit 89, 88a to 88d.

Each circuit shown in FIGS. 6 to 9 (pulse generation circuit 82, each delay chain 83, 84, delay time detection circuit 85, encoding circuit 86, correction control circuit 87, each auxiliary output circuit section 88a). ~ 88d, regular output circuit section 8
9) are general ones, and their operations are well known, so the description thereof is omitted here.

FIG. 10 is a circuit diagram of an embodiment in which the signal delay time of each of the auxiliary output circuit units 88a to 88d is set longer than the signal delay time of the normal output circuit unit 89 in order to perform the slew rate control. is there. Each auxiliary output circuit section 88a-8
A signal delay circuit 120 is provided on the 8d input signal line.

(Fourth Embodiment) A fourth embodiment of the invention as defined in claim 7 will be described below with reference to FIG.

The output circuit 201 of this embodiment has n CMs.
The OS inverters 202a to 202α, n PMOS transistors 203a to 203α, each inverter 204, and a register 205 are included.

Each of the CMOS inverters 202a to 202α
Are connected in parallel, and the internal signals of the circuit are CMOS
It is output to the outside through the inverters 202a to 202α. The sources of the PMOS transistors forming the CMOS inverters 202a to 202α are connected to the high-potential-side power supply VDD through the PMOS transistors 203a to 203α.
It is connected to 1 to VDDn. The data Q1 to Qn of the register 205 are input to the gates of the PMOS transistors 203a to 203α via the inverter 204, respectively. Only one of the data Q1 to Qn in the register 205 is at the H level, and the other data is at the L level. Further, the sources of the NMOS transistors forming the CMOS inverters 202a to 202α are connected to the ground line as the low potential side power source.

Therefore, for example, the data of the register 205
Of Q1 to Qn, only data Q2 is H level and other data Q0,
PM corresponding to data Q2 when Q1 and Q3 to Qn are at L level
Only the OS transistor 203b turns on. Then, the high-potential-side power supply voltage VDD2 is supplied to the CMOS inverter 202b via the PMOS transistor 203b. At this time, the other CMOS inverters 202a-20
The high-potential-side power supply voltages VDD1 to VDDn are not supplied to 2α. Therefore, the output level of the output circuit 201 corresponds to the high-potential-side power supply voltage VDD2.

As described above, in the output circuit 201 of this embodiment, one C of the CMOS inverters 202a to 202α corresponding to the data Q1 to Qn of the register 205 is selected.
High-potential power supply voltage VDD corresponding to only MOS inverter
1 to VDDn are supplied. Therefore, by appropriately setting the data Q1 to Qn of the register 205, the output circuit 20
The output level of 1 can be switched to one corresponding to each power supply voltage VDD1 to VDDn. That is, according to this embodiment, one output circuit 201 can obtain n output levels (power supply voltages VDD1 to VDDn).

On the other hand, the conventional output circuit is composed of a CMOS inverter whose power supply voltage is fixed, and one output circuit can obtain only one output level. Therefore, according to the present embodiment, the number of output circuits can be reduced as compared with the conventional one. Further, in that n output levels can be obtained, the output circuit 20 of the present embodiment is provided.
It can be said that 1 is more multifunctional and has higher performance than the conventional output circuit.

(Fifth Embodiment) A fifth embodiment of the invention as defined in claim 7 will be described below with reference to FIGS.

FIG. 12 is a circuit diagram of the interface of this embodiment. FIG. 13 is a circuit diagram of a conventional interface. As shown in FIG. 13, the conventional interface 221 includes an input circuit 222, a level conversion circuit 223, and an output circuit 224.

The input circuit 222 is composed of a NAND 225. The level conversion circuit 223 includes the inverters 226 to 228 and the NMOS transistor 22.
9, 230 and PMOS transistors 231, 232.

The output circuit 224 is connected to the NAND 233 and NO.
R234, CMOS inverter 235 and each inverter 2
36 and 237. The NAND22
5 and the respective inverters 226 and 227 are supplied with power from the high potential side power supply VDD2. Also, NAND
233 and each inverter 228, 236, 237 and NOR
234, CMOS inverter 235, NMOS transistors 229 and 230, and PMOS transistor 23
Power is supplied to 1 and 232 from the high potential side power supply VDD1.

Then, the NAND 225 of the input circuit 222
An input signal DIN is input via the input terminal 238, and an external control signal CTL is input via the control signal input terminal 239.

The output signal of the NAND 225 of the input circuit 222 is output to the output circuit 2 via the level conversion circuit 223.
24, the CMOS inverter 2 of the output circuit 224
The output signal DOUT is output from 35 through the output terminal 240.

The control signal CTL from the outside is also input to the inverter 237 of the output circuit 224 via the control signal input terminal 239. The interface 221 configured in this way is capable of supplying the high-potential-side power supply voltage V
The input signal DIN having a level corresponding to DD2 can be converted into the output signal DOUT having a level corresponding to the high-potential-side power supply voltage VDD1. Since the interface 221 is a general interface, detailed description of its configuration and operation will be omitted.

As shown in FIG. 12, the interface 301 of this embodiment comprises a conventional interface 221, an additional output circuit 302 and a register 303. The additional output circuit 302 includes a NAND 304 and a NOR 3
05, CMOS inverter 306, and each inverter 30
7, 308, an NMOS transistor 309, and a PMOS transistor 310. Power is supplied to each of the gates 304 to 310 from the high potential side power supply VDD1.

The input side of the NAND 305 is connected to the output node C of the inverter 236 of the output circuit 224 of the conventional interface 221 and the output node A of the inverter 228 of the level converter 223. The input side of the NOR 305 has an output circuit 224.
Of the inverter 237 is connected to the node C.

The input / output of this interface 301 is common with that of the interface 221. That is, the input terminal 238 of the interface 221, the control signal input terminal 239, and the output terminal 240 are
It functions as a corresponding terminal of the interface 301. The register 303 controls the operation of the interface 221 and the additional output circuit 302 according to the external data CI input to the control terminal 241. That is, the interface 301 shares the input circuit 222 and the level converter 223 with the interface 221,
The input circuit 222 and the level converter 223 function as an interface in which the output circuits 224 and 302 are driven in parallel.

Therefore, the output current obtained from the output terminal 240 of the interface 301 is the output current of each output circuit 224.
It is the sum of the output currents of 302. As a result, the interface 301 of this embodiment is the same as the conventional interface 22.
The output current is larger than that of 1, and the driving capability for the external circuit connected to the output terminal 240 can be increased.

The effect of this embodiment is that the additional output circuit 30
In addition to 2, it can be further improved by providing an additional output circuit 311 having the same circuit configuration. That is, the gist of the present embodiment is that a plurality of additional output circuits 302 and 311 are provided by one set of the input circuit 222 and the level converter 223.
Are simultaneously driven, and in particular, the drive control is performed by the register 303. This allows
In this embodiment, as compared with the case where a plurality of conventional interfaces 221 are simply provided in parallel, it is possible to obtain a high driving capability with a small circuit scale.

FIG. 14 shows the high-potential-side power supply voltages VDD1 and VDD2 supplied to the output circuit 224 of the interface 221.
FIG. 6 is a circuit diagram of a main part for explaining an operation of controlling the signal by a register 303.

When the high-potential-side power supply voltage VDD1 is equal to or higher than the high-potential-side power supply voltage VDD2 (VDD1 ≧ VDD2), the high-potential-side power supply voltage VDD is supplied to the CMOS inverter 235 and the NAND 233.
2 is supplied to the NOR 234 and the high-potential-side power supply voltage VDD2
Consider the case where is supplied. In this case, when the output terminal 240 is fixed to the L level (= OV) and the high potential side power supply VDD1 is turned off (or 0V), each MOS transistor 235 forming the CMOS inverter 235 is formed.
Both a and 235b may turn on, and a through current may flow.

In such a case, the register 303 changes the voltage supplied to the NAND 233 to the high-potential-side power supply voltage VDD1 to turn on the PMOS transistor 235a and turn off the NMOS transistor 235b. Then, a current path shown by an arrow β is generated, and a through current does not flow in the CMOS inverter 235. Therefore, the power consumption of the interface 221 is reduced.

As for the interface 301,
Similarly to the above, it is possible to prevent a shoot-through current generated in the CMOS inverter 306 of the additional output circuit 302 and reduce power consumption.

As described above, by using the register 303 to control the high-potential-side power supply voltages VDD1 and VDD2 supplied to the gates in the interfaces 221, 301, low power consumption can be achieved.

The present invention is not limited to the above embodiment, but may be carried out as follows. 1) In the output circuit 51 shown in FIG. 3 and the output circuit 61 shown in FIG. 4, PMOS transistors 53, 54, 6
6 and 67 are replaced with NMOS transistors. However,
In that case, the PMOS transistors 53, 54, 6
Since a voltage drop corresponding to the threshold voltages of 6 and 67 occurs, the output levels of the output circuits 51 and 61 do not reach the high-potential-side power supply voltages VDD1 and VDD2. However, each output circuit 5
By setting the high-potential-side power supply voltages VDD1 and VDD2 in accordance with the output levels required for 1, 61 and the threshold voltages of the PMOS transistors 53, 54, 66, 67, practically no problem will occur. can do.

2) In the output circuit 51 shown in FIG. 3 and the output circuit 61 shown in FIG. 4, two high-potential-side power supplies VDD1
, VDD2 is not switched, but three or more high-potential-side power supplies are switched so that three or more output levels can be obtained.

3) The pulse generating circuit 82 shown in FIG. 6 is replaced with another oscillator circuit instead of the ring oscillator. Further, in the output circuit 81 shown in FIG. 5, the pulse generation circuit 82 is omitted and the signal DS and the clock CKO are supplied from the outside.

4) In the output circuit 81 shown in FIG. 5, a plurality of regular output circuit sections 89 are provided, and when the characteristics of the transistor become better than usual, the number of operating regular output circuit sections 89 is reduced. To control. In this case, even if the characteristics of the transistor become better than usual, the output circuit 8
The output current of 1 can be kept close to the IOL standard. Therefore, the output circuit 81 can have higher performance.

5) Output circuit sections 88a to 88 shown in FIG.
The d and 89 are not the CMOS inverter 116 but the open drain type. 6) The fourth embodiment and the fifth embodiment are used in combination. In this case, a higher performance interface can be realized by the synergistic effect of each embodiment.

[0098]

As described above in detail, according to the present invention, there is an excellent effect that it is possible to provide a high-performance, multi-functional and low power consumption output circuit.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the invention according to claim 3;

FIG. 2 is a diagram illustrating the principle of the invention according to claim 7;

FIG. 3 is a circuit diagram of a first embodiment embodying the invention described in claim 1.

FIG. 4 is a circuit diagram of a second embodiment embodying the invention described in claim 2.

FIG. 5 is a block circuit diagram of a third embodiment in which the invention according to claim 3 is embodied.

FIG. 6 is a partial circuit diagram of an embodiment in which the third embodiment is embodied to the gate level.

FIG. 7 is a partial circuit diagram of an embodiment in which the third embodiment is embodied to the gate level.

FIG. 8 is a partial circuit diagram of an embodiment in which the third embodiment is embodied to the gate level.

FIG. 9 is a partial circuit diagram of an embodiment in which the third embodiment is embodied to the gate level.

FIG. 10 is a partial circuit diagram of another embodiment in which the third embodiment is embodied to the gate level.

FIG. 11 is a circuit diagram of a fourth embodiment embodying the invention described in claim 7;

FIG. 12 is a partial circuit diagram of a fifth embodiment embodying the invention described in claim 7;

FIG. 13 is a partial circuit diagram of a fifth embodiment of the invention as set forth in claim 7;

FIG. 14 is a partial circuit diagram of a fifth embodiment of the invention as set forth in claim 7;

[Explanation of symbols]

1 Output Circuit Section 2 Characteristic Variation Detection Circuit 3 Correction Control Circuit 11 Input Circuit 12 Level Convert Circuit 13 Output Circuit 14 Interface 15 Register 52, 95 CMOS Inverter 53, 54, 66, 67 PMOS Transistor 55 As Control Circuit and Selective Connection Means Control decoder 68 NMOS transistor 64,65 Pull-up resistor 62,63 Transmission gate 83,84 Delay chain 85 as a selective connecting means 85 Delay time detection circuit 81 Encoding circuit C Capacitive load VDD1, VDD2 High potential side power supply

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H03H 11/28 8628-5J H03K 17/16 L 9184-5J 19/0175 (72) Inventor Kazuo Ohno 2-1844, Kozoji-cho, Kasugai-shi, Aichi Within Fujitsu Viersai Co., Ltd.

Claims (7)

[Claims] 1. A CMOS inverter (52), MOS transistors (53, 54) connected between a plurality of high-potential-side power supplies (VDD1, VDD2) having different voltages and the CMOS inverter (52), A semiconductor device comprising: a control circuit (55) for turning on only one of the MOS transistors (53, 54). 2. A plurality of high potential side power supplies (VDD) having different voltages.
Each PMOS transistor (6 connected to 1, VDD2)
6, 67), an NMOS transistor (68) whose drains are connected to the respective PMOS transistors (66, 67), and a high-potential-side power source (VDD1) corresponding to the gates of the PMOS transistors (66, 67). Each of the pull-up resistors (64, 65) for pulling up to the VDD2 side and the gate of any one of the PMOS transistors (66, 67) is selected to select the NMOS.
A semiconductor device comprising: selective connecting means (55, 62, 63) connected to a gate of a transistor (68). 3. A plurality of output circuit sections (1) connected in parallel, and a characteristic fluctuation amount detection circuit (2) for detecting a characteristic fluctuation amount of an element forming each output circuit section (1), Based on the detection result of the characteristic fluctuation amount detection circuit (2),
A semiconductor device comprising: a correction control circuit (3) for controlling the number of the output circuit sections (1) that operate. 4. The semiconductor device according to claim 3,
A semiconductor device, wherein the signal delay times of the output circuit sections (1) are set to different values. 5. The semiconductor device according to claim 3,
The characteristic fluctuation amount detection circuit (2) includes two delay chains (83, 84) having different loads.
And a delay time detection circuit (85) for detecting the signal delay time difference of each delay chain (83, 84) and converting the signal delay time difference into a pulse width, and the delay time detection circuit (85) An encoding circuit (81) for encoding the pulse width by counting it with a clock (CKO) is provided, and the correction control circuit (3) includes a signal (CS) encoded by the encoding circuit (81). ) Is decoded and the corresponding output circuit section (1) is selected and operated. 6. The semiconductor device according to claim 4,
Each of the delay chains (83, 84) is composed of a plurality of CMOS inverters (95) of the same transistor size, which are cascaded by the same number, and one delay chain (84) has the respective CMOS inverters (95). A semiconductor device, wherein a capacitive load (C) is provided on the output of the semiconductor device. 7. An interface (14) comprising an input circuit (11), a level conversion circuit (12) and an output circuit (13) connected in parallel, and controlling each interface (14). A semiconductor device comprising a register (15).