JPH0785598A - Device for reproducing data - Google Patents

Abstract

PURPOSE:To easily extract a clock with an irreducible minimum band width by preliminarily equalizing an input signal, extracting a timing component with ternary identification and extracting a synchronizing clock. CONSTITUTION:After a regenerative signal is integrated by an integration circuit 52, resulting signal is equalized to an equalization reference of PR1 by an analog equalizer 53. By a ternary equalization identifier 56, +1 is detected by comparing with a threshold value (+), and -1 is detected by comparing with the threshold value (-). By an edge extraction circuit 57, edge extraction is performed. By a timing pulse obtained from the circuit 56, the synchronizing clock is extracted in a PLL circuit 58. Then, an output from the analog equalizer 53 is supplied to an A/D converter 59, and the regenerative signal after equalized by the analog equalizer 53 is A/D converted. Then, the data differenced by an I-D operation circuit 60 are adjusted to the equalization reference of PR4 by correcting a characteristic with a digital equalizer 61, and the reproducing data are obtained by two parallel Viterbi demodulation circuit 62.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing apparatus used in, for example, a digital magnetic recording / reproducing apparatus, and more particularly to a structure for performing equalization.

[0002]

2. Description of the Related Art Conventionally, in a digital magnetic recording / reproducing apparatus such as a digital VTR (digital video tape recorder), an integral detecting method is mainly used as an equalizing method of a reproducing signal.

FIG. 9 shows a schematic structure of a reproduction equalization circuit in which the above-mentioned integral detection method is used. The reproduction equalization circuit referred to here performs not only reproduction signal equalization but also data reproduction (data identification), and corresponds to, for example, a data reproduction circuit (or data reproduction device) provided in a digital magnetic recording / reproduction device. To do.

In FIG. 9, this reproduction equalization circuit (data reproduction device) passes a reproduction signal from, for example, a magnetic recording medium supplied to an input terminal 1 through an integration circuit 2 and an analog equalizer 3. , The Nyquist first criterion is equalized to eliminate intersymbol interference, and a threshold value from the terminal 4 and the output from the analog equalizer 3 are compared in magnitude by using a comparator as the binary discriminator 5. Then, the digital data of 1 and 0 is restored by this comparison.

Further, in addition to the latch circuit 8, an edge extraction circuit 6 and a PLL (phase lock loop) circuit 7 are added after the binary discriminator 5.

The output of the binary discriminator 5 is sent to the edge extraction circuit 6, and in the edge extraction circuit 6, the above-mentioned 2
After the output of the value discriminator 5 is differentiated by the gate delay, the exclusive OR (EX-OR) is taken and the edge changed from 1 to 0 and the edge changed from 0 to 1 are added (that is, the edge is extracted. ). The next PLL circuit 7 outputs a clock synchronized with the timing pulse obtained by the edge extraction circuit 6, and the synchronous clock from the PLL circuit 7 is sent to the clock input terminal of the latch circuit 8.

The data input terminal of the latch circuit 8 is
The output of the binary discriminator 5 is sent. Therefore, in the latch circuit 8, the output of the binary discriminator 5 (comparator) is latched by the synchronous clock of the PLL circuit 7 so that reproduced data can be obtained. This reproduction data is taken out from the output terminal 9.

Here, the unit pulse response satisfying the first Nyquist criterion has a waveform as shown in FIG. 10A, and therefore such an output is obtained when the unit pulse is recorded and reproduced. Therefore, it is necessary to adjust the equalizer (the analog equalizer 3 described above).

The frequency characteristic at this time is as shown in FIG. Here, the roll-off coefficient is 0 to 1
Therefore, the required frequency band is the narrowest when the roll-off coefficient is zero. However, as shown in FIG. 10B, it is impossible to realize an ideal low-pass filter that has a linear value of 1 up to the Nyquist frequency and has a value of 0 or more up to the Nyquist frequency with hardware. Further, the frequency characteristic with the roll-off coefficient of 1 is easy to realize, but at this time, the necessary band is widened and the high frequency component deteriorated in the magnetic recording / reproducing system is emphasized.
Will be deteriorated. Therefore, a value of around 0.5 is generally used as the roll-off coefficient.

Further, the eye pattern at this time is as shown in FIG.
(C) is obtained. When the amplitudes are thus standardized to 1 and 0, the binary discriminator 5
In, the value is binarized with 0.5 as a threshold.

[0011]

By the way, recently, partial response class 4 (hereinafter referred to as PR4)
Digital VTRs that use as an equalization standard are being actively researched.

In the PR4, the response to the unit pulse is equalized so as to spread over (1, 0, -1) and 3 bits as shown in FIG.

Here, the frequency characteristic satisfying the equalization criterion of PR4 is such a characteristic that it becomes 0 (null point) at direct current and Nyquist frequency as shown in FIG. 11 (b). In FIG. 11B, the characteristic of the roll-off coefficient of 0 which is the minimum bandwidth is such a characteristic that it peaks at a half of the Nyquist frequency and becomes 0 at the Nyquist frequency and above.

The eye pattern at this time is as shown in FIG.
(C) of FIG. In PR4, in order to avoid the propagation of detection error, a precoder
By the interleaved NRZI (Interleaved Non
Record after converting to a code called Return to Zero Inverse). When the threshold value is detected, the threshold value is ± 0.5, and the value is ternarized into 1, 0, −1, and ± 1 is set to 1 and 0 is set to 0, whereby decoding is performed.

The reason why the combination of the interleaved NRZI and PR4 has received attention is that it has the following merits.

(1) Since the frequency characteristic of the minimum bandwidth can be realized, recording and reproduction can be performed with a narrow bandwidth. (2) Since the characteristics of the magnetic recording / reproducing system and the frequency characteristics of the equalization reference are very similar, equalization is easy and noise is not emphasized much. (3) A good error rate can be obtained by using two simple 2-state Viterbi decoders for NRZI in parallel.

On the other hand, the biggest problem of PR4 is that it is difficult to extract the synchronous clock.

That is, as can be seen from the eye pattern of FIG. 11 (c), in PR4, there are two types of waveforms where the amplitude changes from +1 to 0 and when the waveform changes from +1 to -1, the threshold value of +0.5. Cross. Similarly, the threshold value of -0.5 is crossed in two kinds of cases where the waveform changes from -1 to 0 in amplitude and -1 to +1 in amplitude. Therefore, even if the timing component is extracted from the threshold value of ± 0.5 when the signal is ternarized, the jitter in the phase direction becomes very large. That is, the clock cannot be directly extracted from the reproduction signal satisfying the equalization standard of PR4.

Therefore, in the conventional digital magnetic recording / reproducing apparatus using PR4, the reproducing equalizing circuit has a structure as shown in FIG. 12 or 13.

Both the configurations shown in FIGS. 12 and 13 are
After performing integral equalization on the first Nyquist standard in advance, binarization is performed to extract a clock, and using this clock, the reproduction signal before equalization (FIG. 12) or after equalization (FIG. 13) is analog / digital-converted. This is a method of performing A / D conversion by the (A / D) converter 10. 12 and 13, constituent elements similar to those in FIG. 9 are designated by the same reference numerals. In addition, in FIGS. 12 and 13, the same constituent elements are designated by the same reference numerals.

First, in the configuration of FIG. 12, the input terminal 1
The reproduction signal from is sent to the A / D converter 10. The A / D converter 10 converts the reproduction signal (analog signal) into a digital signal by using the synchronous clock from the PLL circuit 7. The digital signal from the A / D converter 10 is passed through the 1 + D arithmetic circuit 11 that adds the one-code period delayed signal to the current signal, and the digital equalizer 12 outputs the P signal.
The data is equalized according to the equalization standard of R4, and then decoded (data identification) by a 2-parallel Viterbi decoder 13 which is a parallelization of a 2-state Viterbi decoder, and is output from an output terminal 14 as reproduced data. It should be noted that "D" in the 1 + D arithmetic circuit 11 indicates a 1-bit delay operator.

In the configuration of FIG. 13, the output from the analog equalizer 3 is supplied to the A / D converter 10, and the digital signal from the A / D converter 10 is a 1-code period delayed signal. 1-D arithmetic circuit 1 that subtracts from the current signal
5 and 1 + D arithmetic circuit 11, digital equalizer 12 performs equalization to PR4 equalization standard, and thereafter it is decoded by 2-parallel Viterbi decoder 13 and taken out from output terminal 14 as reproduced data. “D” in the 1-D arithmetic circuit 15 also indicates a 1-bit delay operator.

As described above, the configuration of FIG. 12 includes the 1 + D arithmetic circuit 11, and the configuration of FIG. 13 includes the 1-D arithmetic circuit 15 and the 1 + D arithmetic circuit 11.

Here, the transmission characteristic of PR4 is (1 + D)
Although it can be expressed as × (1-D), FIG.
As shown in (b) of the above, it is required to become the null point at the Nyquist frequency. By the operation "1 + D", which adds the reproduction signal delayed by 1 bit to the current reproduction signal,
This null point can be made exactly. In the case of FIG. 12, the differential characteristic of magnetic recording and reproduction and the digital equalizer 1
2 substitutes the operation "1-D". On the other hand, in the configuration of FIG. 13, since the integration is performed, the calculation of “1-D” is also necessary. However, in the configuration of FIG. 13, the digital equalizer 12 may be omitted only by the calculation of (1 + D) × (1-D). It should be noted that the 1 + D arithmetic circuit 11 in FIG. 12 is omitted and the function is assigned to the digital equalizer 12, and the digital equalizer 12 is configured as a fixed type or an adaptive type. There are many possible methods, but these belong to the prior art.

However, as described above, even in the digital magnetic recording / reproducing apparatus using the PR4 in the reproducing equalization circuit, when the integral equalization is performed on the Nyquist's first standard to extract the clock, the roll still occurs. Since the OFF is inevitably around 0.5, a band above the Nyquist frequency is required as shown in FIG. Therefore, one of the merits of PR4 that the required bandwidth is narrow cannot be utilized, and the demand for the tape head system becomes strict.
This leads to an increase in cost and a decrease in reliability.

As a method of easily extracting the clock from these points and narrowing the required bandwidth, the partial response class 1 (hereinafter referred to as P
R1) is used as an equalization standard. In the PR1, the response to the unit pulse is shown in FIG.
(A), it is equalized so as to spread over (1, 1) and 2 bits.

This is equivalent to the second standard of Nyquist, and the frequency characteristic of the minimum bandwidth satisfying the equalization standard of PR1 becomes 0 at the Nyquist frequency as shown in FIG. 14 (b). Since this frequency characteristic is achievable, the required bandwidth is the same as PR4, which is narrower than Nyquist's first standard.

The eye pattern for PR1 is as shown in FIG. Therefore, in the case of threshold detection, it is 2 at the crossing points +1.7 and +0.3.
Three threshold values are discriminated between ± 1 and 0 with one threshold. Since the intersections at this threshold are only the transitions of 2 and 1 and the transitions of 0 and 1, respectively, the jitter in the phase direction is very small compared to PR4. Therefore, with PR1, the clock can be directly extracted from the equalized reproduced signal.

FIG. 15 shows a configuration example of the reproduction equalization circuit using PR1. In FIG. 15, the reproduction equalization circuit satisfies the equalization standard of PR1 by passing the reproduction signal from the magnetic recording medium supplied to the input terminal 21 through the integration circuit 22 and the analog equalizer 23. Equalize to.
The output of the analog equalizer 23 and the ternary discriminator 25 and A
It is sent to the / D converter 28.

The ternary discriminator 25 may use two binary discriminators made up of comparators. +1 is detected by comparison with the threshold (+) and -1 is detected by comparison with the threshold (-). . In the next edge extraction circuit 26, the ternary classifier 25
Edge extraction is performed by taking the OR (logical sum) of the outputs of the two binary discriminators that make up. This edge extraction circuit 26
PLL circuit 27 by the timing pulse obtained from
The synchronous clock is extracted with and this synchronous clock is sent to the clock input terminal of the A / D converter 28.

The signal input terminal of the A / D converter 28 is supplied with the output from the analog equalizer 23, and
The / D converter 28 A / D converts the reproduction signal after the equalization by the analog equalizer 23. This A / D converter 28
The digital signal from is decoded by the Viterbi decoder 29 and is taken out from the output terminal 30 as reproduced data.

Although the digital equalizer is not provided in the configuration of FIG. 15, it may be provided for more precise equalization.

Here, since the PR1 makes a two-state transition, it is possible to realize a Viterbi decoder with a simple circuit configuration similar to NRZI. However, PR
In the case of 4, the two-state NRZI Viterbi decoder may be used in two parallels, whereas PR1 cannot perform such simple parallelization. Therefore, it is difficult to realize a Viterbi decoder in a digital VTR that records and reproduces at a high data rate.

Further, in the case of PR1, since a direct current component is required, it is necessary to adopt a direct current reproducing system such as quantization feedback or devise a recording modulation code to eliminate the direct current component. It is disadvantageous compared to PR4, which does not require ingredients.

Therefore, in view of the above, the present invention can easily extract a clock with a minimum required bandwidth, and a good error rate can be obtained by a Viterbi decoder which can be easily realized as a high speed circuit. Therefore, if it is applied to, for example, a digital VTR, the requirement for the tape head system can be relaxed, and the cost can be reduced or the reliability can be improved, and if the same magnetic recording / reproducing system is used, higher density digital recording / reproducing can be performed. It is an object of the present invention to provide a data reproducing device that can be used.

[0036]

The data reproducing apparatus of the present invention has been proposed in order to achieve the above-mentioned object, and is a transmission line after being subjected to precoding processing using a predetermined partial response method. Based on the first equalization means for equalizing the input signal transmitted via the first response equalization standard of partial response class 1 and the signal equalized to the first equalization reference of partial response class 1 A synchronous clock extracting means for extracting a synchronous clock, a converting means for converting the supplied signal into digital data based on the synchronous clock, and a signal converted into the digital data corresponding to the predetermined partial response method. Data recognition is performed from the second equalization means for equalizing to the equalization reference and the signal equalized to the equalization reference corresponding to the predetermined partial response method. It is characterized in that it has a data identification means for performing.

More specifically, the first data reproducing apparatus of the present invention uses the partial response class 4 as the predetermined partial response method and performs the precoding process via the transmission line. An integrating circuit for integrating the transmitted input signal, an analog equalizer for equalizing the integrated signal to a partial response class 1 equalization standard, and a signal for equalizing the partial response class 1 A timing component extraction circuit that identifies three values and extracts a timing component; a clock generation circuit that generates a clock synchronized with the extracted timing component;
An A / D converter (conversion means) for converting the partial response class 1 equalized signal into digital data based on the synchronous clock, and a one-code period delayed signal of the digital data converted signal are currently available. And a digital equalizer for equalizing to the partial response class 4 equalization reference.

The second data reproducing apparatus of the present invention is
Integrating means for integrating the input signal transmitted through the transmission line after precoding using class 4 of the partial response as the above-mentioned predetermined partial response method, and the integrated signal of the partial response An analog equalizer that equalizes to the class 1 equalization standard, a timing component extraction circuit that extracts a timing component by ternary identifying the partial response class 1 equalized signal, and the extracted timing component A clock generating circuit for generating a clock synchronized with the above, an A / D converter (conversion means) for converting the input signal into digital data based on the synchronous clock, and the partial response of the signal converted into the digital data. And a digital equalizer for equalizing to the class 4 equalization standard.

That is, in the first and second equalization circuits, the first equalization means is composed of the integration circuit and the analog equalizer, and the synchronous clock is composed of the timing component extraction circuit and the clock generation circuit. Extraction means is configured.

Here, the timing component extraction circuit is
It comprises a ternary classifier having a fixed threshold value generator for generating a predetermined fixed threshold value, and ternary classifying the signal equalized to class 1 of the partial response using the fixed threshold value. is there. The timing component extraction circuit has an envelope detection circuit for detecting the upper and lower envelopes of the partial response class 1 equalized signal, and the upper and lower envelope detection outputs, respectively. It is also possible to use a ternary classifier for performing ternary classification of the signal equalized to the class 1 of the partial response by using a threshold value based on Alternatively, the timing component extraction circuit has an automatic gain control circuit that automatically controls the gain of the signal equalized to class 1 of the partial response, and a fixed threshold value generator that generates a predetermined fixed threshold value. It is also possible to use a ternary discriminator for discriminating ternary values of the partial response class 1 equalized signal after the automatic gain control using the fixed threshold value.

The digital equalizer is a digital filter that uses fixed filter coefficients or a digital filter that uses adaptive filter coefficients according to a predetermined algorithm.

Before the three-value discrimination in the synchronous clock extraction circuit, a 1 + D operation circuit for adding a one-code period delayed signal to the current signal can be inserted, and the 1 + D arithmetic circuit can be inserted.
The D operation circuit can be inserted after the A / D converter.

Further, as the data discriminating means, it is possible to use one in which two-state Viterbi decoders are arranged in parallel, one comprising a four-state Viterbi decoder, and one comprising a ternary discriminator.

Next, the third data reproducing apparatus of the present invention is
In the first equalizing means, the predetermined partial
The input signal transmitted through the transmission line after being precoded using the Extended Partial Response as the response method is equalized to the partial response class 1 equalization standard, and The second equalizing means converts the signal converted into the digital data into the extended
Equalize to the partial response equalization criteria.

[0045]

According to the present invention, an input signal transmitted through a transmission line after precoding is performed by using a predetermined partial response method (partial response class 4 or extended partial response). On the other hand, the synchronization clock is extracted by performing pre-equalization based on the partial response class 1 equalization standard and further extracting the timing component by ternary identification.
An input signal or a signal equalized to the partial response class 1 equalization standard by this synchronous clock is converted into digital data, and then the signal converted into this digital data is adapted to a predetermined partial response system. Equalization standards (class 4 of partial response and equalization standard of extended partial response) are equalized, and data is discriminated from the equalized signal.

[0046]

Embodiments of the present invention will be described below with reference to the drawings.

The data reproducing apparatus of the embodiment of the present invention, as shown in FIGS. 1, 2 and 6 to 8 described later, has a predetermined partial response method (class 4 of partial response or extended partial response). )
First equalizing means (integrator circuit 52) for equalizing the input signal transmitted to the input terminal 51 through the transmission line after precoding using , An analog equalizer 53) and a synchronous clock extracting means (a ternary discriminator 56, an edge extracting circuit 57, a PLL) for extracting a synchronous clock based on a signal equalized to the class 1 equalization standard of the partial response. A circuit 58), an A / D converter 59 for converting the supplied signal into digital data based on the synchronous clock, and an equalization standard corresponding to the predetermined partial response system for the signal converted into the digital data. Second equalizing means (1-D arithmetic circuit 60 or digital equalizer 61) for equalizing the same with the equalization standard corresponding to the above-mentioned predetermined partial response method. It is characterized in that it has the a signal data identification means for performing data identification from (2 parallel Viterbi decoder 62, etc.).

FIG. 1 shows a schematic structure of a data reproducing apparatus (a reproducing equalizing circuit in a broad sense) of a first embodiment of the present invention applied to, for example, a digital magnetic recording / reproducing apparatus.

That is, in the data reproducing apparatus according to the first embodiment of the present invention shown in FIG. 1, the magnetic tape is subjected to the precoding process using the partial response class 4 as the predetermined partial response method. An integrating circuit 52 for integrating a reproduction signal transmitted to an input terminal 51 via a transmission path formed of a magnetic recording medium, and an analog for equalizing the integrated signal to a partial response class 1 equalization standard. , A ternary discriminator 56 for ternary discriminating the partial response class 1 signal, an edge extraction circuit 57 for extracting an edge from the output of the ternary discriminator 56, and the edge A PLL circuit 58 for extracting a clock synchronized with the timing pulse obtained from the extraction circuit 57, and equalizing to the partial response class 1 1-D for equalizing signals and A / D converter 59 for converting the digital data based on the synchronizing clock, the signals converted into the digital data to the equalization criteria class 4 of the partial response
It has an arithmetic circuit 60 and a digital equalizer 61, and a two-parallel Viterbi decoder 62 as a data discriminating means for discriminating data from a signal equalized according to the equalization standard of class 4 of the partial response.

That is, in the data reproducing apparatus according to the first embodiment, the integrating circuit 52 and the analog equalizer 53 constitute the first equalizing means. Further, the ternary discriminator 56 and the edge extracting circuit 57 constitute the timing component extracting circuit, the PLL circuit 58 constitutes a clock generating circuit, and the timing component extracting circuit and the clock generating circuit constitute the synchronous clock. Extraction means is configured.

In FIG. 1, the reproduction signal from the magnetic recording medium supplied to the input terminal 51 is integrated by the integrating circuit 52 and then input to the analog equalizer 53, where the analog equalizer 53 performs PR1. Are equalized to the equalization standard. The reproduced signal equalized to the PR1 equalization standard by the analog equalizer 53 is sent to the ternary discriminator 56 and the A / D converter 59.

The ternary discriminator 56 uses two binary discriminators made up of comparators. +1 is detected by comparison with the threshold (+) and -1 is detected by comparison with the threshold (-). To do. In the next edge extraction circuit 57, the ternary classifier 56
Edge extraction is performed by taking the OR (logical sum) of the outputs of the two binary discriminators that make up. This edge extraction circuit 56
PLL circuit 58 by the timing pulse obtained from
The synchronous clock is extracted with and this synchronous clock is sent to the clock input terminal of the A / D converter 59.

The signal input terminal of the A / D converter 59 is supplied with the output from the analog equalizer 53, and
The / D converter 59 A / D converts the reproduction signal after the equalization by the analog equalizer 53.

Since the reproduction signal data from the A / D converter 59 is integrated here, the 1-D arithmetic circuit 60
You need to make a difference. The 1-D arithmetic circuit 60
The data that has been subtracted is corrected by the digital equalizer 61 to have a characteristic strictly adjusted to the equalization standard of PR4, and is reproduced by the two parallel Viterbi decoding circuit 62 in which two Viterbi decoders for NRZI are parallelized. Data is obtained, and this reproduced data is taken out from the output terminal 63.

In the first embodiment shown in FIG. 1, the A / D
The converter 59 performs A / D conversion on the reproduction signal after equalization. As the configuration of the second embodiment of the present invention, the reproduction signal before equalization is A / D converted as shown in FIG. A configuration is also possible. In FIG. 2, the same components as those in FIG. 1 are designated by the same reference numerals.

That is, the data reproducing apparatus (reproducing equalizing circuit) of the second embodiment has an integrating circuit 52 and an analog equalizer 53 similar to those in FIG. 1, a ternary discriminator 56, an edge extracting circuit 57, A PLL circuit 58, an A / D converter 59 for converting the reproduced signal from the input terminal 51 into digital data based on the synchronous clock, a signal converted into the digital data of the partial response class 4 and the like. Digital equalizer 61 for equalizing to equalization standard
And a two-parallel Viterbi decoder 62 similar to FIG.

In the second embodiment shown in FIG. 2, the reproduction signal supplied to the input terminal 51 is the integrating circuit 52.
And is also sent to the signal input terminal of the A / D converter 59. The A / D converter 59 converts the reproduced signal (analog signal) into a digital signal using the synchronous clock from the PLL circuit 58. The digital signal from the A / D converter 59 is equalized to the PR4 equalization standard by the digital equalizer 61 via the 1 + D arithmetic circuit 64, and then decoded by the two-parallel Viterbi decoding circuit 62 and output terminal 63. Is reproduced as reproduction data.

In the first and second embodiments, the configuration of the first embodiment shown in FIG. 1 is the same as that of the conventional example shown in FIG.
3 is shown corresponding to the structure of FIG. 3, and the structure of the second embodiment shown in FIG. 2 is shown corresponding to the structure of FIG. 1 and 13 and FIGS. 2 and 12, the configurations are similar at first glance, but the equalization by the analog equalizer is the first standard of Nyquist in the conventional example, but the present embodiment The configuration of the example is different in that it is based on the equalization reference of PR1, and the extraction of the timing pulse is binary identification in the conventional example, whereas it is ternary identification in the present embodiment. Is different.

There are many possible variations of the configurations of the first and second embodiments of the present invention described above, depending on the combination of the respective constituent elements and the method of making them. The method of constructing these modifications will be described below.

First, as for the structure of the ternary value discriminator 56, there can be mentioned the structures shown in FIGS.

That is, the ternary value discriminator 56 used in FIGS. 1 and 2 may be configured to give a fixed voltage as the threshold value (+) and the threshold value (−), for example. This is realized by setting two threshold values only by the variable resistors VR1 and VR2 as shown in FIG.

In FIG. 3, a reproduction signal equalized to the PR1 equalization reference is supplied from the analog equalizer 53 to the terminal 80. This signal is sent to comparators 81 and 82 as binary discriminators. The comparator 8
Reference numerals 1 and 82 denote variable resistors VR1 and VR2, respectively.
A fixed voltage is applied as the threshold value (+) and the threshold value (−), and the equalized reproduction signal is compared with the threshold value (+) or the threshold value (−). The comparator 81 compares the threshold value (+) with +1 (upper edge).
Is detected, and the comparator 82 detects -1 (lower edge) by comparison with the threshold value (-). The detection outputs of these comparators 81 and 82 respectively correspond to the terminal 8
It is sent to the edge extraction circuit 58 in the subsequent stage via 3, 84.

In contrast to the configuration of FIG. 3 described above, as shown in FIG. 4, a configuration in which ternary discrimination is performed by an optimum threshold value according to the change in the amplitude of the equalized reproduction signal can be considered. The ternary discriminator shown in FIG. 4 detects the upper and lower envelopes of the equalized reproduction signal, and sets the ratio of each voltage to the ground level as a threshold value.

That is, in FIG. 4, the equalized reproduction signal from the analog equalizer 53 supplied to the terminal 80 is sent to the upper envelope detection circuit 86 and the lower envelope detection circuit 87, and the comparator 81 and Sent to 82. In the comparator 81, the ratio of the upper envelope detection voltage in the upper envelope detection circuit 86 by the variable resistor VR5 and the ground level is set to the threshold value (+). Further, in the comparator 82,
The lower envelope detection circuit 8 by the variable resistor VR6
The ratio of the lower envelope detection voltage at 7 to the ground level is set as the threshold (-). As a result, the comparators 81 and 82 are provided with the optimum threshold value according to the change in the amplitude of the equalized reproduction signal. The terminals 8 to which the detection outputs of these comparators 81 and 82 correspond, respectively.
It is sent to the edge extraction circuit 58 in the subsequent stage via 3, 84.

The ternary classifier 56 is shown in FIG.
It is also possible to adopt a configuration as shown in. In the configuration of FIG. 5, the reproduced signal after equalization is reproduced by AGC (automatic gain contr).
ol: Automatic gain control) By controlling the gain through the amplifier and then discriminating between three values, it is possible to follow the change in the amplitude of the reproduced signal even if the threshold value itself is a fixed value given only by the variable resistor (the amplitude of the reproduced signal. Is not affected by).

That is, in FIG. 5, the equalized reproduction signal supplied from the analog equalizer 53 to the terminal 80 is sent to the comparators 81 and 82 after gain control is performed by the AGC circuit 85. The comparator 81, 8
2 is given a fixed voltage as a threshold value (+) and a threshold value (−) by the corresponding variable resistors VR3 and VR4. With this configuration, even if the threshold value itself is a fixed value given only by the variable resistance, it is possible to perform ternary discrimination capable of following the change in the amplitude of the reproduction signal (not affected by the amplitude of the reproduction signal). In the case of the example of FIG. 5, in the configuration of FIG. 1, the output of the AGC circuit 85 is the A / D converter 59.
You may enter it in.

A fixed transversal filter can be used as the digital equalizer 61 configured as shown in FIGS. That is, the digital equalizer 61 can be a fixed equalizer.

Further, this transversal filter is set to L
It is also possible to use an adaptive equalizer using an MS (least mean square) algorithm or the like. That is, the digital equalizer 61 can be an adaptive equalizer.

Further, although it is limited to the configuration of FIG. 1, the digital equalizer 61 can be omitted if the analog equalizer 53 is strict.

Next, in each of the configurations shown in FIGS. 1 and 2, a 1 + D arithmetic circuit using an analog delay line can be inserted between the integrating circuit 52 and the analog equalizer 53. By incorporating this analog 1 + D arithmetic circuit, the circuit configuration becomes somewhat complicated, but it becomes possible to exactly create a null point at the Nyquist frequency. The analog 1 + D arithmetic circuit is equivalent to the integrating circuit 5
It can also be inserted before 2 or after the analog equalizer.

In the configuration of FIG. 2, a digital 1 + D arithmetic circuit 64 is inserted between the A / D converter 59 and the digital equalizer 61 in order to create a null point exactly. The 1 + D arithmetic circuit 64 can be omitted. Furthermore, from the configuration of FIG.
Even when the + D arithmetic circuit 64 is omitted, the analog 1 + D arithmetic circuit is equivalent to the integrating circuit 52 and the analog equalizer 5.
It is also conceivable to insert it between 3 and 4.

In the case of the configuration of FIG. 1 as well, a digital 1 + D arithmetic circuit can be inserted after the A / D converter 59 in order to precisely create a null point.

Next, in each of the above-described configurations of this embodiment, a 2-state Viterbi decoder (Viterbi decoder) for NRZI is used for 2 parallels (2 parallel Viterbi decoding circuit 62) as a discriminator for reproduced data. However, if there is a margin in the operating speed of the circuit, it is possible to use only one 4-state Viterbi decoder (Viterbi decoder) for PR4.

If the error rate may be sacrificed to some extent, a ternary classifier for detecting a threshold value may be used instead of the Viterbi decoder in order to simplify the circuit.

FIG. 6 shows a configuration in which the components of the above-described various modifications are combined based on the configuration of FIG.

That is, in FIG. 6, the case where the analog 1 + D arithmetic circuit 70 is inserted between the integrating circuit 52 and the analog equalizer 53 and the case where the analog 1 + D arithmetic circuit 70 is not inserted based on the configuration of FIG. , None) When the ternary classifier is configured as the ternary classifier 71 having a fixed threshold value, a threshold value based on the envelope detection voltage, or an AGC circuit as shown in FIGS. 3 to 5, the digital equalizer 72 is used. When the fixed equalizer or the adaptive equalizer is used or omitted, the reproduction data discriminator 73 is replaced by the 2-parallel Viterbi decoding circuit 62 (2-state Viterbi decoder in 2 parallel) or 4-state Viterbi decoder of FIG. The structure which combined the component of various modifications, such as a case where it was used as a three-value classifier, is shown.

According to the configuration of FIG. 6, analog 1 + D
Two cases with / without the arithmetic circuit 70, three cases with fixed threshold value / threshold value based on envelope detection voltage / AGC circuit addition in the three-value discriminator 71, and fixed with the digital equalizer 72. Equalizer / adaptive equalizer / 3 in case of omission
And 3 in the case of 2-parallel / 4-state Viterbi decoder / 3-value discriminator of the 2-state Viterbi decoder in the reproduction data discriminator 73.
From the streets, a total of 54 configurations (= 2 × 3 × 3 × 3) of modified examples can be considered.

Further, FIG. 7 shows a configuration in which the components of the above-described various modifications are combined based on the configuration of FIG.

That is, also in this FIG. 7, based on the configuration of FIG. 2, similar to FIG.
When 0 is inserted and when it is not inserted (Yes, No), when the three-value classifier is configured as the above-mentioned three-value classifier 71,
When the 1 + D arithmetic circuit 74 is inserted after the A / D converter 59 and when it is not inserted (Yes / No), the digital equalizer 7
5 shows a configuration in which the components of various modified examples such as the case where the fixed equalizer or the adaptive equalizer is used, the case where the digital equalizer 72 is used, the case where the reproduction data discriminator 73 is used, and the like are combined. ing.

According to the configuration of FIG. 7, analog 1 + D
The above two types in the arithmetic circuit 70 and the above three types in the ternary classifier
, The case where the 1 + D arithmetic circuit 74 is inserted and the case where the 1 + D arithmetic circuit 74 is not inserted (presence or absence), the case where the fixed equalizer / adaptive equalizer in the digital equalizer 75 is used, and the reproduction data From the above three ways in the discriminator 73, a total of 72 ways (= 2
A modified example of (3 × 2 × 2 × 3) is conceivable.

From the above-mentioned FIGS. 6 and 7, a total of 72 + 54 = 126 different modified configurations can be considered in this embodiment.

Next, a third embodiment of the present invention will be described. There is a so-called Extended Partial Response (hereinafter referred to as EPR) as an equalization standard that requires a narrower band than the above-mentioned equalization standard. Where n
EPRn has intersymbol interference over bits, and the response to a unit pulse is as follows.

EPR4: (1,1, -1, -1, -1) EPR5: (1,2,0, -2, -1) EPR6: (1,3,2, -2, -3, -1)

This is the "D" of the 1-bit delay operator.
When expressed using, it becomes as follows. EPR4: (1-D) x (1 + D) ² EPR5: (1-D) x (1 + D) ³ EPR6: (1-D) x (1 + D) ⁴

Here, like the PR4 corresponding to the EPR3, it is impossible to extract the clock from the reproduced signal after the equalization, but the present invention is also effective for these EPRs, and the PR1 It is possible to extract the clock after equalization to the equalization standard.

FIG. 8 shows a configuration in which the present invention is applied to EPR4. In FIG. 8, the same components as those in FIG. 1 are designated by the same reference numerals.

In FIG. 8, the difference from FIG. 1 is that after A / D conversion (1-D arithmetic circuit 6
After 1), a 1 + D arithmetic circuit 64 is added,
The only difference is that the Viterbi decoder is not paralleled in two.
The digital equalizer 61 of FIG. 8 is adjusted to the EPR4 equalization standard.

In addition, in this third embodiment, the EPR
If it is 5, there will be two 1 + D arithmetic circuits, and EPR6
In that case, three 1 + D arithmetic circuits are required.

Also in the case of the third embodiment (EPR), A
As in the case of the first and second embodiments (PR4), there are many possible combinations of the signals to be D / D converted, the ternary discriminator for PR1, the 1 + D arithmetic circuit, the digital equalizer, and the like. . That is, for example, various modifications are possible as in FIGS. 6 and 7.

As described above, according to each embodiment of the present invention, the Viterbi decoder which can easily extract the clock with the minimum required bandwidth and is easy to realize as a high-speed circuit is required. Good error rate with minimal bandwidth. Further, when applied to a digital magnetic recording / reproducing apparatus such as a digital VTR, for example, requirements for a tape head system can be relaxed, and cost can be reduced or reliability can be improved. Further, if the same magnetic recording / reproducing system is used, higher density digital recording / reproducing becomes possible.

In each of the above-described embodiments, the magnetic recording medium at the time of digital magnetic recording and reproduction is taken as an example of the transmission path, but the same effect can be obtained in a transmission line such as a cable or wireless communication. it can.

[0092]

As described above, according to the present invention, a predetermined partial response method (class 4 of partial response or extended partial response) is used to perform a precoding process, and then, through a transmission line. It is necessary to perform pre-equalization on the supplied input signal according to the equalization standard of partial response class 1, and to extract the synchronization component by extracting the timing component by ternary identification. The clock can be easily extracted with a minimum bandwidth. After that, this partial response class 1 equalized signal is equalized to an equalization standard (partial response class 4 or extended partial response equalization standard) corresponding to a predetermined partial response method. Since the data is discriminated from the equalized signal, a Viterbi decoder which can be easily realized as a high-speed circuit can be used and a better error rate can be obtained. Therefore, for example, a digital VT
When applied to a digital magnetic recording / reproducing apparatus such as R, the requirements for the tape head system can be relaxed, the cost can be reduced or the reliability can be improved. High density digital recording / reproducing becomes possible.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a schematic configuration of a data reproduction device (reproduction equalization circuit) according to a first embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a schematic configuration of a data reproduction device (reproduction equalization circuit) according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a specific configuration of a ternary classifier when a fixed threshold is used.

FIG. 4 is a circuit diagram showing a specific configuration of a ternary classifier with envelope detection.

FIG. 5 is a circuit diagram showing a specific configuration of a ternary classifier with an AGC circuit.

FIG. 6 is a block circuit diagram for explaining a configuration in the case where various modifications are combined in the data reproducing apparatus of the first embodiment.

FIG. 7 is a block circuit diagram for explaining a configuration in the case where various modifications are combined in the data reproducing device of the second embodiment.

FIG. 8 is a block circuit diagram showing a schematic configuration of a data reproduction device (reproduction equalization circuit) of a third embodiment.

FIG. 9 is a block circuit diagram showing a schematic configuration of a conventional reproduction equalizer circuit (data reproducing device) of an integral detection system.

FIG. 10 is a characteristic diagram for explaining the first Nyquist criterion.

FIG. 11 is a characteristic diagram for explaining a class 4 equalization standard of a partial response.

FIG. 12 is a block circuit diagram showing a schematic configuration of a reproduction equalization circuit (data reproduction device) using a conventional partial response class 4 equalization standard.

FIG. 13 is a block circuit showing a schematic configuration of a conventional reproduction equalization circuit (data reproduction apparatus) that uses a partial response class 4 equalization standard after extracting a synchronization clock after the Nyquist first standard equalization. It is a figure.

FIG. 14 is a characteristic diagram for explaining a class 1 equalization standard of a partial response.

FIG. 15 is a block circuit diagram showing a schematic configuration of a reproduction equalization circuit (data reproduction device) using a conventional partial response class 1 equalization standard.

[Explanation of symbols]

 52 ... Integrator circuit 53 ... Analog equalizer 56 ... Three-value discriminator 57 ... Edge extraction circuit 58 ... PLL circuit 59 ... -A / D converter 60 ... 1-D arithmetic circuit 61 ... Digital equalizer 62 ... 2 parallel Viterbi decoder 64 ... 1 + D arithmetic circuit

Claims (15)

[Claims] 1. A first equalization method for equalizing an input signal, which has been precoded by using a predetermined partial response method and then transmitted through a transmission line, to a partial response class 1 equalization standard. Equalization means, synchronization clock extraction means for extracting a synchronization clock based on a signal equalized to the partial response class 1 equalization standard, and the supplied signal converted to digital data based on the synchronization clock And a second equalizing means for equalizing the signal converted into the digital data to an equalization standard corresponding to the predetermined partial response method, and an equalization corresponding to the predetermined partial response method. A data reproducing device, comprising: a data identifying means for identifying data from a signal equalized based on a reference. 2. The first equalizing means integrates an input signal transmitted through a transmission line after precoding is performed using a partial response class 4 as the predetermined partial response method. And an analog equalizer that equalizes the integrated signal to a partial response class 1 equalization standard, and the synchronous clock extraction means equalizes the partial response class 1 The signal processing apparatus has a timing component extraction circuit that identifies a signal in three values and extracts a timing component, and a clock generation circuit that generates a clock synchronized with the extracted timing component. An analog / digital converter for converting the equalized signal into digital data based on the synchronous clock, 2. The data reproducing apparatus according to claim 1, wherein the second equalizing means has a 1-D calculating means for subtracting the one-code period delayed signal from the current signal. 3. The first equalizing means integrates an input signal transmitted through a transmission line after precoding is performed using a partial response class 4 as the predetermined partial response method. And an analog equalizer for equalizing the integrated signal to a partial response class 1 equalization standard, and the synchronous clock extraction means equalized to the partial response class 1 The signal conversion device has a timing component extraction circuit for identifying a signal in three values and extracting a timing component, and a clock generation circuit for generating a clock synchronized with the extracted timing component, wherein the conversion means converts the input signal into the synchronization clock. An analog / digital converter for converting into digital data based on the above-mentioned second equalizing means. 2. The data reproducing apparatus according to claim 1, further comprising a digital equalizer that equalizes the signal converted into the data to the equalization standard of the partial response class 4. 4. The timing component extraction circuit includes a ternary classifier that performs ternary classification of the signal equalized to class 1 of the partial response by using a predetermined fixed threshold value. The data reproducing apparatus according to claim 2 or 3. 5. The timing component extraction circuit detects the upper and lower envelopes of the partial response class 1 equalized signal, and a threshold value based on the upper and lower envelope detection results, respectively. 4. The data reproducing apparatus according to claim 2, further comprising a ternary discriminator for discriminating ternary values of the signal equalized to the class 1 of the partial response using. 6. The timing component extraction circuit automatically controls the gain of a signal equalized to the class 1 of the partial response, and uses the predetermined fixed threshold value to perform the partial response after the automatic gain control. The data reproducing apparatus according to claim 2 or 3, further comprising a ternary classifier that classifies the signal equalized to class 1 according to (3). 7. The second equalizing means is provided with a digital equalizer for equalizing the signal converted into the digital data to the partial response class 4 equalization standard. Item 2. The data reproducing device according to item 2. 8. The data reproducing apparatus according to claim 3, wherein the digital equalizer is a digital filter using a fixed filter coefficient. 9. The data reproducing apparatus according to claim 3, wherein the digital equalizer is a digital filter using an adaptive filter coefficient according to a predetermined algorithm. 10. The synchronous clock extraction circuit according to claim 3,
4. The data reproducing apparatus according to claim 2, wherein a 1 + D arithmetic circuit for adding the one-code period delayed signal to the current signal is inserted before the value identification. 11. A 1 + D for adding a one-code period delayed signal to the current signal after the analog / digital converter.
The data reproducing apparatus according to claim 2 or 3, wherein an arithmetic circuit is inserted. 12. The data identifying means comprises two parallel Viterbi decoders in two states.
Alternatively, the data reproducing apparatus described in 3 above. 13. The data reproducing apparatus according to claim 2 or 3, wherein the data identifying means comprises a 4-state Viterbi decoder. 14. The data reproducing apparatus according to claim 2, wherein the data discriminating means comprises a ternary discriminator. 15. The first equalizing means uses the extended partial response method as the predetermined partial response method.
The input signal transmitted through the transmission line after being precoded using the partial response is equalized to the partial response class 1 equalization standard, and the second equalization means is the digital equalizer. 2. The data reproducing apparatus according to claim 1, wherein the signal converted into data is equalized according to the equalization standard of the extended partial response.