JPH0784076B2 - Print data control circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dot matrix printer control circuit, and more particularly to a print data control circuit which is a data signal control circuit for a dot line memory for temporarily storing a print dot image. .

[Conventional technology]

Conventionally, in this type of dot matrix printer, control of print data is performed by a microprocessor. For example, as shown in FIG. 2 (a), the second
Consider the case of writing a dot pattern of characters as shown in FIG.

That is, this is a case where the half-width character of FIG. 9B is inserted in the frame of FIG. 9A and the printing as shown in FIG.

The data signal of the microprocessor generally used at present can usually take only a specific number of bits such as 4 bits, 8 bits and 16 bits. Therefore, in the circuit configured by the microprocessor, the memory connected to the microprocessor is configured so that a specific number of bits such as 4 bits, 8 bits and 16 bits can be accessed by one read and write. For example, considering the case where the microprocessor has a 16-bit data signal, both the normal character pattern generator and the dot line memory are configured so that the data signal is 16 bits.

However, since the size of the dot pattern of the character to be printed is not specified, it may be 8 dots wide × 16 bits long like the half-width alphabet “A” shown in FIG. 2 (b).

In this case, when data is read from the character pattern generator, only 8 bits out of 16 bits are significant signals and the other 8 bits are meaningless. Therefore, if the 16-bit data read from this character pattern generator is written to the dot line memory as it is, meaningless data is also written, so the dot image on the dot line memory is as shown in Fig. 2 (C). It doesn't.

Therefore, in the microprocessor, the operation shown in FIG. 2 (D) is performed. First, the dot pattern shown in FIG. 7B is read from the character pattern generator (see FIG.
(See reference) This data "FFOO (hexadecimal notation of binary number)" is logically operated to make the meaningless part of the data zero (see FIG. 4D). Next, significant data is shifted to the position where it is written (see (D) in the figure).
The case of bit shift is taken as an example.

Next, the data in the dot line memory of FIG. 9A is read (see FIG. 9D), and the read data and “FOOF” are read.
(Binary hexadecimal notation) "(see FIG. 3D). Finally, the data of the character generator and the data of the dot line memory are logically ORed to obtain the data. Is written to the dot line memory.

As a result, 8 bits of the 16-bit data read from the dot line memory are replaced with the character dot pattern 8 bits and stored again in the dot line memory.

[Problems to be Solved by the Invention]

As described above, in the conventional print data control method, the dot pattern read from the character pattern generator is operated by the operation of the microprocessor.

As a result, the transfer time of the character dot pattern from the character pattern generator to the dot line memory depends on the time required for the microprocessor to operate, which limits the performance of the printed dot image generation. As a result, it causes a decrease in printing speed.

[Object of the Invention]

The present invention has been made in view of the above point, and it is possible to improve the printing speed by speeding up the process of reading the dot pattern from the character pattern generator to the process of writing the dot pattern to the dot line memory. It is an object of the present invention to provide a print data control circuit.

[Means for Solving the Problems]

The present invention generates the first pattern data stored in the dot line memory corresponding to the bit number of the data signal of the microprocessor and the character pattern generator 16 corresponding to the bit number of the data signal of the microprocessor. In the print data control circuit 18 for obtaining the print dot image by synthesizing the second pattern data, the pattern data storage means (the third register 9) for storing the first pattern data, and the second pattern data. Is generated by setting the effective portion of the second pattern data to be printed to "1" and corresponding to the bit number of the data signal of the microprocessor. Position data storage means (second register 3) for storing position designation data with the unnecessary portion set to "0"
It has and.

Moreover, the shift circuit 4 that shifts the second pattern data from the first register 2 by an amount corresponding to the bit position of the effective portion of the position designation data, the logical negation value of the position designation data, and the first pattern data storage A first AND circuit 8 which ANDs the first pattern data from the means, and the first pattern data from the third register 9 and the second pattern data shifted by the shift circuit. A logical operation circuit 5 for performing an operation, a second AND circuit 6 for ANDing the output of the logical operation circuit and the position designation data, and a logic for the first AND circuit 8 and the second AND circuit 6. A configuration is adopted in which a logical sum circuit 10 is provided which outputs the logical sum to the dot line memory 20 while taking the sum. This aims to achieve the above-mentioned object.

[Operation] According to the present invention, the composite operation of the print dot image is
This is performed by the arithmetic processing means of the print data control circuit.

At this time, the microprocessor only performs the second pattern data generation from the character pattern generator and the write trajectory of the combined print dot image to the dot line memory, and does not perform any calculation processing of the combined image.

〔Example〕

An embodiment of the present invention will be described below with reference to the accompanying drawings.

First, an example of a control circuit of a dot or matrix printer to which the embodiment is applied will be described with reference to FIG. In FIG. 4, the control circuit includes a microprocessor 13, a communication control circuit 14, a main memory 15, a character pattern generator 16, a print address control circuit 17, a print data control circuit 18,
It is composed of a timing control circuit 19, a dot line memory 20, and a shift register 21. The output signal of the microprocessor 13 is an address signal a that gives the address of the memory and register to be read and written, a control signal b that gives the read and write identification and timing, and data to the memory and register when writing. , And a data signal c to which data is given from the memory and the register at the time of reading is connected so as to be transmitted and received between the respective circuits, and the microprocessor 13 controls the whole.

In the above apparatus, the communication control circuit 14 functions as an interface with the upper position, and the print data mainly represented by the character code from the upper apparatus, for example, shown in FIG. 2 (B). In this case, the character code of the alphabet "A" is transmitted.

The microprocessor 13 receives this and stores it in the main memory 15, which is a working memory. Next, the microprocessor 12 reads the character code of "A" from the main memory 15, calculates the address of the character pattern generator 16 in which the character pattern corresponding to the character code is stored, and the dot of the character "A" is calculated. Lead the pattern. After that, the microprocessor 13 writes the dot pattern of the character "A" in the dot line memory 20. The address signal a of the microprocessor 13 is a print address control circuit 17, and the data signal c is a dot line memory via a print data control circuit 18.
Given to 20 each. In this case, the combination of the pattern data as shown in FIG. 2 is performed by the print data control circuit 18 based on the write trajectory of the microprocessor 13 with respect to the dot line memory, as will be described later.

The timing control circuit 19 generates control signals necessary for reading and writing the dot line memory 20.
The shift register 21 converts the read data of the dot line memory 20 into a serial signal suitable for transmission to the printing mechanism unit 22.

Then, in the print mechanism unit 22, the print head (not shown) is driven based on the input serial signal, and the second
The printing shown in FIG. 6C is performed.

Next, an embodiment of the above-mentioned print data control circuit 18 will be described with reference to FIG. In the figure, the address signal a and the control signal b of the microprocessor 13 are input to the decoder circuit 1. By the address signal a and the control signal b, the first register 2 and the second register 2 Latch pulse signals d and e for the register 3 and a start pulse signal f for triggering dot line memory access in the timing control circuit 12 are generated.

The first register 2 and the second register 3 to which the first data signal c which is the data signal of the microprocessor 13 is input
Are the first pulses when the latch pulse signals d and e are generated.
It has a function of latching the data of the data signal c.

The output signal g of the first register 2 is input to the shift circuit 4 and the logical operation circuit 5, respectively. The output signal g input to the shift circuit 4 is a signal that sets the shift number of the output signal h with respect to the input signal c in the shift circuit 4, and the signal g in the logical operation circuit 5 is a signal that selects the type of logical operation. Is.

As described above, the shift circuit 4 is a circuit that shifts and outputs the input data according to the set shift number. In this case, the output signal h of the shift circuit 4 is input to one input terminal of the logical operation circuit 5.

The output signal i of the second register 3 is the first AND circuit 6
Is input to one of the input sides and the logical NOT circuit 7. The output signal j of the logical NOT circuit 7 is input to one input side of the second AND circuit 8.
The other input signal of the first AND circuit 6 is the output signal k of the logical operation circuit 5. In the first AND circuit 6,
The data set in the second register 3 and the logical operation circuit 5
Of the output signal k of FIG.

Next, the second data signal 1 which is the data signal of the dot line memory 20 is input to the third register 8, and the timing control circuit 12 transfers the data read from the dot line memory 20 to the dot line memory 20. It is designed to be latched by a latch pulse signal m generated in synchronization with 20 leads. The output signal n of the third register 9 is output to one input side of the logical operation circuit 5 and one input side of the second AND circuit 8, respectively.

Next, the output signal o of the first AND circuit 6 and the output signal p of the second AND circuit 8 are connected so as to be input to the OR circuit 10. The output signal q of the OR circuit 10 is input to the buffer circuit 11, and the output signal of the buffer circuit 11 is the second data signal l. The buffer circuit 11 has a function of passing the input signal q as the output signal 1 by the buffer enable signal r generated by the timing control circuit 12 in synchronization with the writing of the dot line memory 20.

Next, the timing control circuit 12 starts reading or writing of data with respect to the dot line memory 20 by the activation pulse signal f generated by the decoder circuit 1, and controls the latch pulse signal m, the buffer enable signal r, and the dot line memory 20. The signals s are generated respectively.

Next, the overall operation of the above embodiment will be described with reference to FIGS. The process of logical operation is shown in FIG. 3, and the flowchart of the operation is shown in FIG. It is also assumed here that the input / output data signal of the microprocessor 13 is 16 bits, and the data signals of the character pattern generator 16 and the dot line memory 20 are also 16 bits. Furthermore, a part of the dot pattern of the character read from the character pattern generator 16 (here, 1 word)
Of these, significant patterns are 15 to 12 bits and 11 to 8 bits, and 7 to 0 bits are meaningless. Hereinafter, these will be referred to as A1, A2, and C, respectively (see FIG. 3).

First, the shift number corresponding to the address or location to be written is set in the first register 2 (see step SA in FIG. 5). For example, if the writing location is from the 4th bit, the shift number "4" is stored in the first register 2.
(Binary) ”is set.

Further, similarly, position designation data corresponding to a place to be written is set in the second register 3 (see step SB). For example, in the example shown in FIG. 2, since the data to be written is from the 4th bit to the 8th bit, "OFFO (hexadecimal notation of binary number)" is set in the second register 3 (see (See Figure 3).

Therefore, "OFFO (binary hexadecimal representation)" is input to the first AND circuit 6, and "FOOF (binary hexadecimal representation)" is input to the second AND circuit 8. Each will appear (see FIG. 3).

Next, the microprocessor 13 activates the timing control circuit 12 to read the corresponding dot pattern data from the dot line memory 20 (see step SC in FIG. 5). These dot pattern data are
Hereinafter, four bits will be referred to as B1, B2, B3, and B4 in order from the 15th bit (see FIG. 3). The read dot pattern data (B1, B2, B3, B4) is latched in the third register 9 (see step SD in FIG. 5).

As described above, the first, second and third registers 2, 3, 9
When each data is stored in
As a result, while the data (A1, A2, C) to be lined to the dot line memory 20 is generated as the first data signal c, the timing control circuit 12 is written to the dot line memory 20 (( (See Step SE in Fig. 5). Then, the shift circuit 4 generates 4-bit shifted data (C, A1, A2, C) (see third), which is input to the logical operation circuit 5.

On the other hand, since the output signal n of the third register is input to the logical operation circuit 5, the output signal k of the logical operation circuit 5 is the operation result of that shown in FIG. The sum is as shown in the figure.

Then, since and of FIG. 3 appear at the input terminal of the first AND circuit 1 of the next stage, the output signal o thereof is as shown in FIG. Since the same figure appears at the input terminal of the second AND circuit 8, its output signal p becomes as shown in the figure. Since the respective output signals of the first AND circuit 6 and the second AND circuit 8 are respectively input to the OR circuit 10, the same figure appears at the input terminal of the OR circuit 10 and its output The signal q is as shown in the figure (see step SF in FIG. 5).

The data obtained in this way (B1, B2VA1, B2VA2, B
4) passes through the buffer circuit 11 by the buffer enable signal m generated in synchronization with the write timing of the dot line memory 20 and is written in the dot line memory 20 (see step SG in FIG. 5).

As described above, according to this embodiment, necessary data is stored in the register of the print data control circuit in advance, and then the print data control circuit calculates the composite data based on the start command from the microprocessor. Since it is decided to write to the dot line memory, the microprocessor does not need to calculate the combined data.

Therefore, the dot pattern read from the character pattern generator and the dot pattern in the dot line memory are quickly combined and written to the dot line memory, and the printed dot image is generated at high speed. The printing speed will be improved.

The present invention is not limited to the above-described embodiment, and for example, the logical operation portion in the print data control circuit in FIG. 1 can be variously modified in design so as to achieve the same operation.

As described above, according to the present embodiment, since the calculation for obtaining the print dot image is performed by the print data control circuit, the generation of the print dot image becomes faster and the print speed is improved. It is possible to provide an excellent print data control circuit that does not exist in the past.

〔The invention's effect〕

Since the present invention is configured and functions as described above, according to this, since various logical operations are performed by using the position designation data, the dot line memory requests character pattern data having an unnecessary portion by a simple combination of operations. The pattern data can be matched. Therefore, the process of removing the unnecessary portion of the character pattern data caused by making the number of bits of the data signal of the microprocessor correspond can be implemented by a plurality of circuits that perform logical operations. Furthermore, since each AND circuit correlates the pattern data required by the dot line memory with the character pattern data from the character generator and synthesizes them, the actual writing process to the dot line memory is completed in one step. It's fast. In this way, the microprocessor can be released from the processing from the reading of the character pattern data from the character generator to the writing to the dot line memory. Therefore, the processing time in the editing process of the character pattern can be shortened, the throughput can be improved, and the printing speed can be increased. In this way, by providing a superior print data control circuit that has never before been possible, the printing speed can be improved by speeding up the process of reading the dot pattern from the character pattern generator to the process of writing it to the dot line memory. can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a print data control circuit of the present invention, FIG. 2 is an explanatory view of a conventional print data control system, and FIG. 3 is an operation explanatory view of a print data control circuit according to the embodiment. FIG. 4 is a block diagram of the control circuit of the dot matrix printer according to the embodiment, and FIG. 5 is a flowchart showing the operation of the embodiment. 1 ... Decoder circuit, 2 ... First register, 3 ... Second register, 4 ... Shift circuit, 5 ... Logical operation circuit, 6 ... First AND circuit, 7 ... Logical NOT Circuit, 8 ... second AND circuit, 9 ... third register, 10 ... OR circuit, 11 ... buffer circuit, 12 ... timing control circuit, 13 ... microprocessor, 14 ... communication Control circuit, 15 ... Main memory, 16 ...
… Character generator, 17 …… Print address control circuit, 18 …… Print data control circuit, 19 …… Timing control circuit, 20 …… Dot line memory, 21 …… Shift register, 22 …… Printing mechanism, a… … Address signal, b …… Control signal, c …… First data signal, d …… Latch pulse signal, e …… Latch pulse signal, f …… Starting pulse signal, g …… First register output signal , h ... shift circuit output signal, i ... second register output signal, j ... logical NOT circuit output signal, k ... logical operation circuit output signal, l ... second data signal, m ... Latch pulse signal, n ... Output signal of third register, o ... Output signal of first AND circuit, p ... Output signal of second AND circuit, o ... First Output signal of logical product circuit, p ... Output signal of second logical product circuit, q ... Output signal of logical sum circuit, r ... Buffer enable signal, s ... Dot line Mori of the output signal.

Claims (1)

[Claims] 1. A first pattern data stored in a dot line memory corresponding to the number of bits of a microprocessor data signal and a character pattern generator corresponding to the number of bits of a microprocessor data signal. A print data control circuit for synthesizing the second pattern data to obtain a print dot image, and first and second pattern data storage means for storing the first and second pattern data, respectively, Position data storing means for storing the position designation data by setting "1" as an effective portion of the second pattern data to be printed and "0" as an unnecessary portion caused by corresponding to the bit number of the data signal of the microprocessor. And the second pattern data from the second pattern data storage means is an effective part of the position designation data. A shift circuit that shifts by an amount corresponding to the bit position of the first pattern, and a first AND circuit that ANDs the logical negation value of the position designation data and the first pattern data from the first pattern data storage means. A logical operation circuit for performing a logical operation between the first pattern data from the first pattern data storage means and the second pattern data shifted by the shift circuit, and the output of the logical operation circuit and the position A second logical product circuit that obtains a logical product with specified data; and a logical sum of the first logical product circuit and the second logical product circuit, and the logical sum is used as the print dot image in the dot line memory And a logical sum circuit for outputting to the print data control circuit.