JPH0783215B2 - Peak detection circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a peak detection circuit used in, for example, an automatic gain control circuit integrated into an integrated circuit.

[Technical background of the invention]

For example, in a video tape recorder, an automatic gain control circuit (hereinafter referred to as an AGC circuit) is used to keep the amplitude of an FM signal obtained through a video head constant. This circuit is generally composed of an automatic gain control amplifier, a peak detection circuit that obtains a detection output according to this amplification when this output amplitude exceeds a certain value, and a reduction filter that smooths this detection output. The output voltage of the AGC amplifier is kept constant by supplying it to the gain control terminal of the AGC amplifier to control the gain.

FIG. 3 shows an example of the above-mentioned peak detection circuit.
The transistors Q1 and Q2 and the current source 11 form a differential amplifier, and signals from the first and second level shift circuits are supplied to the bases of the transistors Q1 and Q2, respectively. The first level shift circuit includes a transistor Q4 and a current source 12, and a second level shift circuit
The level shift circuit of is transistor Q5, current source 13, resistor R3
The signals from the first and second level shift circuits are set to have a DC offset. Then, the differential voltage signals VI1 and VI2 are supplied to the bases of the transistors Q4 and Q5. Then, the detection output is taken out from the terminal of the resistor R1 or R2 and supplied to the reduction filter of the next stage.

FIG. 4 shows an output signal example of the circuit of FIG. signal
VB1 and VB2 are signals obtained as a result of the differential voltage signals VI1 and VI2 passing through the level shift circuit, respectively. Also the signal
VO1 is a detection output obtained at the collector of the transistor Q1. When the level of the input signal exceeds a predetermined level, that is, the detection level VDET, a detection waveform can be obtained. Here, the detection level VDET is expressed as VDET = R3 × 13.

[Problems of background technology]

As can be seen from FIG. 4, the peak detection circuit described above can obtain the detection output waveform only once in one cycle of the input signal. Therefore, the detection efficiency is poor, and it is necessary to increase the gain of the amplifier in the subsequent stage in order to obtain the required detection sensitivity. Further, since the detection output waveform once obtained in one cycle cannot be obtained, the amplitude of the waveform smoothed by the low pass filter at the next stage becomes large, which is not desirable.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a peak detection circuit that improves detection efficiency to improve detection sensitivity and also reduces amplitude fluctuation of the output of a low-pass filter in the next stage. And

[Outline of Invention]

According to the present invention, a reference voltage is a voltage different from the common mode voltage of two differential input signals by a constant voltage, and the reference voltage is compared with an input signal having a higher voltage of the differential input signals. This enables full wave detection.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. Signals having different polarities, that is, differential input signals VI1 and VI2 are supplied to the base input terminals of the transistors Q14 and Q15, respectively. Transistor Q14
Has a collector connected to the power supply line and an emitter with a resistor R1
4, grounded via a current source I12 to form a level shift circuit. The transistor Q15 has a collector connected to the power supply line and an emitter grounded via the resistor R15 and the current source I13 to form a level shift circuit.

The outputs of the above level shift circuits, that is, the outputs of the terminals of the resistors R14 and R15 are supplied to the bases of the transistors Q11 and Q12, respectively.

Transistors Q11 and Q12 have their emitter-collector current paths connected in parallel, a common collector connected to the power supply line via a resistor R11, and a common emitter connected to the emitter of transistor Q13 corresponding to transistors Q11 and Q12. To be done. These emitters are also grounded via the current source I11. The collector of the transistor Q13 is the resistor R12.
Is connected to the power supply line via. Further, to the base of the transistor Q13, to supply a voltage obtained by adding a constant voltage to the common mode voltage of the differential input signals input to the bases of the transistors Q11 and Q12 as a reference voltage,
The combined voltage of resistors R16 and R17 connected between the emitters of Q15,
That is, the intermediate voltage is supplied.

Therefore, the signals of each part of this circuit are shown in FIG. 2, and when the amplitudes of the base potentials VB1 and VB2 of the transistors Q11 and Q12 corresponding to the input signal exceed a predetermined level, that is, the base potential VB3 of the transistor Q13. , The detection output waveform is obtained.

In the above circuit, if the differential input signals supplied to the bases of the transistors Q14 and Q15 are VI1 and VI2, and the differential voltage is Vd and the common mode voltage is Vc, VI1 and VI2 are VI1 = Vc + Vd VI2 = Vc -Vd, and the base voltage of the transistors Q11, Q12, Q13 is VB
1, VB2, VB3 and the base-emitter junction voltage is VJ, VB1 = VI1−VJ− (R4) (I12) = {Vc−VJ− (R4) (I12)} + Vd VB2 = VI2−VJ− ( R5) (I13) = {Vc-VJ- (R5) (I13)}-Vd VB3 = {(VI1-VJ) + (VI2-VJ)} x (R7) / (R6 + R7) = (Vc-VJ) x (2R7) / (R6 + R7) R4 to R7 are the values of resistors R14 to R17 where R4 = R5 and R6 = R7, VB1 = {Vc-VJ- (R4) (I12)} + Vd VB2 = {Vc- It can be expressed as VJ- (R4) (I12)}-Vd VB3 = Vc-VJ.

Therefore, VB3 is the common mode voltage of VB1 and VB2 (Vc-VJ- (R4) (I1
2)} plus a constant voltage (R4) (I12) = VDET / 2.

Therefore, as shown in Fig. 2, when the amplitude of the input signal is equal to or lower than the constant voltage VDET, the outputs VO1 and VO2 are constant, and when it is equal to or higher than VDET, the detected output waveform changes every half cycle depending on its magnitude. Is output to and realizes full-wave peak detection.

〔The invention's effect〕

As described above, according to the circuit of the present invention, since the detection output waveform is obtained twice in one cycle of the input, the detection efficiency is high and the high detection sensitivity can be obtained, and the output smoothed by the low pass filter in the subsequent stage. The fluctuation of the waveform amplitude can be reduced. Furthermore, the number of elements can be increased by two resistors and one transistor, and the consumption current does not increase.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part of FIG. 1, FIG. 3 is a conventional peak detection circuit diagram, and FIG. 4 is a signal of each part of FIG. It is a waveform diagram. Q11 to Q15 …… transistors, R11 to R17 …… resistors.

Claims (1)

[Claims] 1. A first and a second transistor, to which respective first differential input signals are supplied to their bases, and a first portion to the output part of said first and second transistors, respectively.
A first and a second current source connected via a second resistor and a second resistor; a connection point between the first resistor and the first current source;
Third and fourth transistors having respective bases supplied with respective signals at the connection point between the second resistance and the second current source, and collector-emitter paths connected in parallel, and the third and fourth transistors. A direct connection of the emitter to the common emitter of the third transistor and a fifth transistor forming a differential amplifier circuit together with the third and fourth transistors, and a series connection between the output parts of the first and second transistors. A peak detection circuit comprising: third and fourth resistors; and means for supplying the voltage at the connection point of the third and fourth resistors as a reference voltage to the base of the fifth transistor.