JPH0783073B2 - Semiconductor chip mounting board - Google Patents
Semiconductor chip mounting boardInfo
- Publication number
- JPH0783073B2 JPH0783073B2 JP61116512A JP11651286A JPH0783073B2 JP H0783073 B2 JPH0783073 B2 JP H0783073B2 JP 61116512 A JP61116512 A JP 61116512A JP 11651286 A JP11651286 A JP 11651286A JP H0783073 B2 JPH0783073 B2 JP H0783073B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wiring
- wiring board
- layer
- epoxy resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、プリント配線基板上に半導体チップを実装し
た半導体チップ実装板に関するものである。Description: TECHNICAL FIELD The present invention relates to a semiconductor chip mounting board in which a semiconductor chip is mounted on a printed wiring board.
従来の技術 近年、ガラス布基板等のプリント配線基板上に裸の半導
体チップを実装した半導体チップ実装板を使用した電子
機器が用いられてきている。この電子機器として、例え
ば、LEDを使った表示板やサーマルプリンタ用のヘッド
等がある。2. Description of the Related Art In recent years, electronic devices using a semiconductor chip mounting plate in which a bare semiconductor chip is mounted on a printed wiring board such as a glass cloth substrate have been used. Examples of this electronic device include a display board using LEDs and a head for a thermal printer.
これらの半導体チップ実装板は、紙基材にフェノール樹
脂を含浸させた基板，紙基材に脂肪族アミン硬化のエポ
キシ樹脂を含浸させた基板あるいはガラス布基材に酸無
水物硬化のエポキシ樹脂を含浸させた基板のいずれかの
基板の同一主面上に、銅箔にニッケル，金あるいは銀の
いずれかをめっきするか、またはニッケルと金を二重に
めっきした第１および第２の配線層が形成され、第１の
配線層の上に半導体チップが取り付けられ、半導体チッ
プのボンディング領域と第２の配線層間がワイヤで電気
的に接続され、半導体チップを密閉する蓋が基板に固着
されている構造である。These semiconductor chip mounting boards have a substrate in which a paper base material is impregnated with a phenol resin, a substrate in which a paper base material is impregnated with an epoxy resin cured with an aliphatic amine, or a glass cloth base material with an epoxy resin cured with an acid anhydride. First and second wiring layers in which copper foil is plated with nickel, gold, or silver, or nickel and gold are double-plated on the same main surface of either of the impregnated boards Is formed, the semiconductor chip is mounted on the first wiring layer, the bonding region of the semiconductor chip and the second wiring layer are electrically connected by a wire, and a lid for sealing the semiconductor chip is fixed to the substrate. Structure.
なお、上記の構造では半導体チップのボンディングパッ
ド領域と基板上の配線層との間に段差が生じるためワイ
ヤボンディングの作業性が非常に悪い。このため両者間
の段差を解消する二層配線構造のものもある。In the above structure, workability of wire bonding is very poor because a step is formed between the bonding pad region of the semiconductor chip and the wiring layer on the substrate. Therefore, there is also a double-layer wiring structure that eliminates the step between the two.
この構造は、二層目の配線基板に穴を設けて一層目の配
線基板の配線層を露出させ、この露出させた配線層の上
に半導体チップを取り付ける構造の採用によって、半導
体チップのボンディングパッド領域と二層目の配線基板
の配線層との間の段差をなくし、さらに、両者間にワイ
ヤが接続され、半導体チップを密閉する蓋が二層目の配
線基板に固着されているものである。This structure employs a structure in which a hole is provided in the wiring board of the second layer to expose the wiring layer of the wiring board of the first layer, and the semiconductor chip is mounted on the exposed wiring layer. A step is eliminated between the area and the wiring layer of the second-layer wiring board, and further, a wire is connected between them and a lid for sealing the semiconductor chip is fixed to the second-layer wiring board. .
発明が解決しようとする問題点 上記の配線基板は、基材にフェノール樹脂，脂肪族アミ
ン硬化のエポキシ樹脂あるいは酸無水物硬化のエポキシ
樹脂を含浸させているためガスを多く放出した。さら
に、これらの硬化剤および樹脂に含まれているNa（ナト
リウム）,K（カリウム）,Cl（塩素）,F（弗素）等の不
純物量が多いためガスの放出量がより多かった、 このため、裸の半導体チップがこの放出されたガスにさ
れされ汚染される不都合があった。Problems to be Solved by the Invention Since the above-mentioned wiring board has a base material impregnated with a phenol resin, an epoxy resin cured with an aliphatic amine, or an epoxy resin cured with an acid anhydride, a large amount of gas is released. In addition, the amount of gas released was larger because the amount of impurities such as Na (sodium), K (potassium), Cl (chlorine), and F (fluorine) contained in these curing agents and resins was large. However, there is a disadvantage that a bare semiconductor chip is contaminated by being exposed to this released gas.
とくに、二層配線構造は、半導体チップを取り付けるた
めに二層配線基板に設けた穴の側壁より、さらにガスが
多く放出する欠点があった。In particular, the double-layer wiring structure has a drawback that a larger amount of gas is discharged from the side wall of the hole provided in the double-layer wiring substrate for mounting the semiconductor chip.
これらの結果、樹脂封止のデュアルインライン（DIL）
パッケージあるいは小形（SO）パッケージ等に実装され
た半導体チップと比較して動作寿命が数分の１から数十
分の１に短縮する不都合があった。As a result of these, resin-encapsulated dual in-line (DIL)
As compared with a semiconductor chip mounted on a package or a small (SO) package, there is a disadvantage that the operating life is shortened from a fraction to a few tens of minutes.
問題点を解決するための手段 本発明の半導体チップ実装板は、配線層を有したエポキ
シ系樹脂よりなる第１の配線基板と、前記第１の配線基
板上に積層され、配線層と開口部を有したエポキシ系樹
脂よりなる第２の配線基板と、前記第２の配線基板の開
口部内であって前記第１の配線基板上の配線層上に搭載
された半導体チップと、前記半導体チップと前記第２の
配線基板上の配線層とを接続したワイヤと、前記第２の
配線基板上に設けられ、前記半導体チップを密閉する蓋
とよりなる半導体チップ実装板において、前記第１の配
線基板および第２の配線基板は、芳香族アミン系の硬化
剤を添加したエポキシ樹脂をアーラミド基材に含浸させ
た基材よりなるものであって、前記芳香族アミン系の硬
化剤中およびエポキシ樹脂中の不純物量は10ppm以下で
あることを特徴とするものである。Means for Solving the Problems A semiconductor chip mounting board according to the present invention is a first wiring board made of an epoxy resin having a wiring layer, laminated on the first wiring board, and has a wiring layer and an opening. A second wiring board made of an epoxy resin having a semiconductor chip, a semiconductor chip mounted on a wiring layer on the first wiring board in an opening of the second wiring board, and the semiconductor chip. A semiconductor chip mounting plate comprising a wire connecting a wiring layer on the second wiring board and a lid provided on the second wiring board for sealing the semiconductor chip, wherein the first wiring board The second wiring board is made of a base material obtained by impregnating an aramide base material with an epoxy resin to which an aromatic amine-based curing agent is added, and the second wiring board is contained in the aromatic amine-based curing agent and the epoxy resin. Impurity amount of 10p It is characterized by being pm or less.
作用 本発明では、芳香族アミン系の硬化剤添加のエポキシ樹
脂を基材に含浸した配線基板に半導体チップを実装する
ため、配線基板からのガスの放出が少なくなり、半導体
チップがほとんど汚染されなくなる。Action In the present invention, since the semiconductor chip is mounted on the wiring board in which the base material is impregnated with the epoxy resin containing the aromatic amine-based curing agent, gas emission from the wiring board is reduced, and the semiconductor chip is hardly contaminated. .
実 施 例 本発明の半導体チップ実装板の二層配線基板による実施
例を図の構造断面図の参照して説明する。Example An example of a semiconductor chip mounting board according to the present invention using a two-layer wiring board will be described with reference to the structural cross-sectional views of the drawings.
本発明の半導体チップ実装板は、紙基材，ガラス布基
材，ガラス不織布基材あるいはアーラミド布基材のいず
れかの基材に、硬化剤および樹脂に含まれているNa,KC
l,F等のそれぞれの不純物量が10ppm以下の芳香族アミン
系の硬化剤添加のエポキシ樹脂を含浸させ、かつ、銅箔
の上にニッケル，金あるいは銀のいずれか１種類以上を
めっきした配線層が所定のパターンに形成された第１の
配線基板１と第２の配線基板２が積層され、第２の配線
基板２を貫通し底部に第１の配線基板１の配線層３が露
出した穴４が形成され、この穴の底部に半導体チップ５
が取り付けられ、半導体チップ５のボンディングパッド
領域６と第２の配線基板２の配線層７とがワイヤ８で接
続され、半導体チップ５を密閉するように、金属，セラ
ミックあるいは樹脂でできた蓋９が第２の配線基板２に
固着された構造のものである。The semiconductor chip mounting board of the present invention comprises a base material such as a paper base material, a glass cloth base material, a glass non-woven cloth base material or an aramide cloth base material, and Na, KC contained in the curing agent and the resin.
Wiring impregnated with an epoxy resin containing an aromatic amine-based curing agent with an impurity content of l, F, etc. of 10 ppm or less, and plated with at least one of nickel, gold, or silver on a copper foil A first wiring board 1 and a second wiring board 2 each having a layer formed in a predetermined pattern are laminated, penetrate the second wiring board 2, and the wiring layer 3 of the first wiring board 1 is exposed at the bottom. A hole 4 is formed, and a semiconductor chip 5 is formed at the bottom of this hole.
Is attached, the bonding pad region 6 of the semiconductor chip 5 and the wiring layer 7 of the second wiring substrate 2 are connected by a wire 8, and a lid 9 made of metal, ceramic, or resin is provided so as to seal the semiconductor chip 5. Is of a structure fixed to the second wiring board 2.
なお、実施例では二層配線基板の構造について説明した
が、単層配線基板に形成された第１の配線層の上に半導
体チップが取り付けられ、半導体チップのボンディング
領域と第２の配線層間にワイヤが接続され、半導体チッ
プを密閉する蓋が基板に固着されている構造であっても
よい。Although the structure of the two-layer wiring board has been described in the embodiment, the semiconductor chip is mounted on the first wiring layer formed on the single-layer wiring board, and the semiconductor chip is mounted between the bonding area of the semiconductor chip and the second wiring layer. The structure may be such that a wire is connected and a lid for sealing the semiconductor chip is fixed to the substrate.
また、硬化剤および樹脂に含まれている不純物量が10pp
mを越えると半導体チップの動作寿命時間は短かくなっ
ていった。In addition, the amount of impurities contained in the curing agent and resin is 10 pp
When it exceeded m, the operating life time of the semiconductor chip became shorter.
次に、従来の樹脂を使った基板と本発明の樹脂を使った
基板とに実装された半導体チップの動作寿命時間を比較
するため、温度が85℃，湿度が85％の中で直流電圧1.5V
印加の高温高湿寿命試験の結果と、圧力が２気圧で温度
が121℃のプレッシャクッカー試験の結果を表に示す。Next, in order to compare the operating life time of the semiconductor chips mounted on the board using the conventional resin and the board using the resin of the present invention, a DC voltage of 1.5 ° C. at a temperature of 85 ° C. and a humidity of 85%. V
The results of the applied high temperature and high humidity life test and the results of the pressure cooker test in which the pressure is 2 atm and the temperature is 121 ° C are shown in the table.
表から明らかなように、本発明の半導体チップ実装板を
使用した方が、従来の実装板より半導体チップの動作寿
命時間は長くなる。 As is apparent from the table, when the semiconductor chip mounting board of the present invention is used, the operating life time of the semiconductor chip is longer than that of the conventional mounting board.
発明の効果 本発明の半導体チップ実装板によれば、芳香族アミン系
の硬化剤添加のエポキシ樹脂を含浸し、さらに硬化剤お
よび樹脂に含まれる不純物量を10ppm以下におさえた配
線基板に半導体チップを実装するため、この配線基板か
らのガスの放出が二層配線構造であっても少なく、半導
体チップがほとんど汚染されなくなる。このため、半導
体チップ表面におけるアルミニウム配線の腐食，配線基
板の配線層の腐食がおこらず半導体チップの動作寿命時
間が長くなる効果が奏される。EFFECTS OF THE INVENTION According to the semiconductor chip mounting board of the present invention, a semiconductor chip is mounted on a wiring board in which an epoxy resin containing an aromatic amine-based curing agent is impregnated, and the amount of impurities contained in the curing agent and the resin is 10 ppm or less. Since the wiring board is mounted, the amount of gas released from the wiring board is small even in the two-layer wiring structure, and the semiconductor chip is hardly polluted. Therefore, the aluminum wiring on the surface of the semiconductor chip and the wiring layer of the wiring board are not corroded, and the operation life time of the semiconductor chip is extended.
図は本発明の半導体チップ実装板の実施例を示す構造断
面図である。 １……第１の配線基板、２……第２の配線基板、3,7…
…配線層、４……穴、５……半導体チップ、６……ボン
ディングパッド領域、８……ワイヤ、９……蓋。FIG. 1 is a structural sectional view showing an embodiment of a semiconductor chip mounting board of the present invention. 1 ... First wiring board, 2 ... Second wiring board, 3,7 ...
... Wiring layer, 4 ... Hole, 5 ... Semiconductor chip, 6 ... Bonding pad area, 8 ... Wire, 9 ... Lid.
Claims (1)
１の配線基板と、前記第１の配線基板上に積層され、配
線層と開口部を有したエポキシ系樹脂よりなる第２の配
線基板と、前記第２の配線基板の開口部内であって前記
第１の配線基板上の配線層上に搭載された半導体チップ
と、前記半導体チップと前記第２の配線基板上の配線層
とを接続したワイヤと、前記第２の配線基板上に設けら
れ、前記半導体チップを密閉する蓋とよりなる半導体チ
ップ実装板において、前記第１の配線基板および第２の
配線基板は、芳香族アミン系の硬化剤を添加したエポキ
シ樹脂をアーラミド基材に含浸させた基材よりなるもの
であって、前記芳香族アミン系の硬化剤中およびエポキ
シ樹脂中の不純物量は10ppm以下であることを特徴とす
る半導体チップ実装板。1. A first wiring board made of an epoxy resin having a wiring layer and a second wiring made of an epoxy resin having a wiring layer and an opening laminated on the first wiring board. A substrate; a semiconductor chip mounted on a wiring layer on the first wiring substrate in the opening of the second wiring substrate; and the semiconductor chip and a wiring layer on the second wiring substrate. In a semiconductor chip mounting plate including a connected wire and a lid provided on the second wiring board and sealing the semiconductor chip, the first wiring board and the second wiring board are aromatic amine-based. Characterized in that it comprises a base material obtained by impregnating an aramide base material with an epoxy resin to which a curing agent is added, wherein the amount of impurities in the aromatic amine-based curing agent and the epoxy resin is 10 ppm or less. Semiconductor chip mounting .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61116512A JPH0783073B2 (en) | 1986-05-21 | 1986-05-21 | Semiconductor chip mounting board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61116512A JPH0783073B2 (en) | 1986-05-21 | 1986-05-21 | Semiconductor chip mounting board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62273759A JPS62273759A (en) | 1987-11-27 |
| JPH0783073B2 true JPH0783073B2 (en) | 1995-09-06 |
Family
ID=14688980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61116512A Expired - Lifetime JPH0783073B2 (en) | 1986-05-21 | 1986-05-21 | Semiconductor chip mounting board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0783073B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5384689A (en) * | 1993-12-20 | 1995-01-24 | Shen; Ming-Tung | Integrated circuit chip including superimposed upper and lower printed circuit boards |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5231672A (en) * | 1975-09-05 | 1977-03-10 | Hitachi Ltd | Ceramic package |
| JPS5254963A (en) * | 1975-10-31 | 1977-05-04 | Nippon Electric Co | Circuit substrate having metalized wiring layer |
| JPS5436031A (en) * | 1977-08-27 | 1979-03-16 | Rikuomi Nakano | Heattretaining mat |
| JPS59167090A (en) * | 1983-03-14 | 1984-09-20 | 松下電器産業株式会社 | Printed circuit board |
-
1986
- 1986-05-21 JP JP61116512A patent/JPH0783073B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62273759A (en) | 1987-11-27 |
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