JPH0778994A - MOS semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] An SOI structure MOS transistor and a CMOS device, which have improved subthreshold characteristics and current driving capability, and can operate with high reliability even under a radiation environment such as X-rays. To provide. [Structure] In the SOI-structure MOS transistor, the buried oxide film below the channel portion is made thinner than the buried oxide film below the source and drain diffusion layers. [Effect] Since the buried oxide film below the channel portion is thin, the amount of charges generated in the buried oxide film due to irradiation with radiation such as X-rays is small, and device operation with higher reliability is realized. Further, the subthreshold characteristic and the operating current are improved as compared with the conventional one, and high-speed operation at a low voltage becomes possible. Furthermore, since the buried oxide film below the source and drain diffusion layers is thick, the capacitance of the source and drain can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device and a method of manufacturing the same, and more particularly to SOI (Silicon on Insul).
and a method for manufacturing the same.

[0002]

2. Description of the Related Art As an example of a conventional MOS type semiconductor device having an SOI structure, SIMOX (Separation by IMpla) is used.
CM of the ultra-thin film SOI structure created by the nted-OXygen) method
The OS device is shown in FIG. Here, 21 is an n-type (10
0) Si substrate, 22 is a buried SiO ₂ layer (buried oxide film) formed by implanting oxygen ions, and 29 is a Si layer, that is, an SOI layer thereon. The nMOS transistor is formed on this SOI layer using the n + layers 23 and 25 as the source and drain and the p layer 24 as the channel portion, and is
The S transistor is formed using the p + layers 26 and 28 as drains and sources and the n layer 27 as a channel portion. 20
Reference numeral 1 is a field oxide film for element isolation, 202 is a gate oxide film, and 203 is a polysilicon gate electrode. The thickness of the SOI layer 29 is as thin as about 70 to 150 nm, and the thickness of the buried oxide film 22 is about 35.
It is formed as thick as about 0 nm to 550 nm. In this SOI structure CMOS device, compared to a CMOS device of a normal structure formed in bulk Si, 1) the short channel effect can be suppressed, 2) the subthreshold coefficient can be reduced, and rapid current rising characteristics can be realized. ) Diffusion layer capacitance and wiring capacitance can be reduced, 4) Latch-up can be prevented, 6) Information inversion of logic circuits due to radiation such as alpha rays and X-rays, that is, soft error can be prevented, 7) Simplification of manufacturing process There are advantages such as being able to.

[0003]

CMOS of SOI structure
Although the device has the above-mentioned advantages, further improvement in performance is required to use it as a basic device of deep submicron ULSI, which requires low voltage operation, and in particular, improvement of subthreshold characteristics and current driving force. is important. The SOI structure is extremely useful as an electronic device or a CMOS for an electronic computer operated in a radiation environment such as outer space due to the soft error prevention effect of the above 6), but has the following problems. That is, in a radiation environment such as outer space, in addition to soft errors, radiation such as X-rays generates positive fixed charges in the oxide film, which causes a large problem that the threshold value fluctuates. Especially SOI
In the structural device, radiation such as X-rays generates fixed charges in both the gate oxide film and the buried oxide film, which cause fluctuations in the threshold value. The generation of fixed charges in the buried oxide film effectively changes the substrate bias,
This causes fluctuations in the threshold value. Conventionally, a buried oxide film having an SOI structure has a thickness of about 350 nm as shown in FIG.
Therefore, there is a serious problem that the thickness is formed as thick as about 550 nm, the amount of positive charges generated therein is large, and the variation of the threshold value due to this is large.

[0004]

The SOI structure MO of the present invention
In the S transistor and the CMOS device, the buried oxide film below the channel portion of the MOS transistor is made thinner than before, while the buried oxide film below the source and drain diffusion layers is kept thick as before. That is, as shown in FIG. 1, the channel portion 10 of the MOS transistor is
The buried oxide film 12 below 5 is thinner than the buried oxide film 13 below the source / drain diffusion layers 103 and 104. Further, the present invention provides a method of implanting oxygen ions into two kinds of buried oxide films having different thicknesses, that is, SIMOX (Separation by IMplanted-OXy).
gen) method. The thin buried oxide film 12 below the channel portion is formed before forming the field oxide film, and the thick buried oxide film 13 below the diffusion layer is formed after forming the gate electrode. The formation of 13 is performed in a self-aligned manner by implanting oxygen ions using the gate electrode and the thick resist film deposited thereon as a mask. Further, the oxide film 13 below the diffusion layer is formed by oxygen ion implantation using the gate electrode having the spacer oxide film on the side wall and the thick resist film deposited thereon as a mask.

[0005]

In the SOI structure of the present invention, since the oxide film thickness under the channel portion is thinned, it is clear that the subthreshold coefficient is smaller than that of the conventional one and the current driving force is also improved. Because the relative permittivity of the oxide film is 3.9, the relative permittivity of Si is as large as 11.9, and the gate voltage component applied to the oxide film and the Si substrate is reduced due to the thinning of the embedded oxide film. On the other hand, the voltage component applied to the SOI layer and the gate oxide film in the channel portion increases, and the depletion layer capacitance on the surface of the SOI layer decreases. Further, since the buried oxide film below the channel portion is thin, the total volume of the buried oxide film in the entire device is significantly reduced, and even when the device is irradiated with radiation such as X-rays, the generated charge amount in the film is reduced. It was possible to reduce much more than before. As a result, the fluctuation of the substrate potential due to the generated charges could be suppressed to a lower value. The charge Q generated in the oxide film by radiation such as X-rays is given by the following equation. Q = qA · Tox · nox (1) Here, q is an electronic charge, A is an occupied area of an oxide film, Tox is an oxide film thickness, and nox is an amount of positive charges generated per unit volume.
The substrate bias variation ΔVsub due to this charge Q is given by the following equation. ΔVsub to Q / Cox = q · Tox ² · nox / εox (2) where Cox is the oxide film capacitance and εox is the dielectric constant of the oxide film.

From the above equation (2), if the oxide film below the channel portion is thinned to reduce the amount of generated charges, the substrate potential fluctuation of the MOS transistor can be suppressed, and therefore the threshold fluctuation can be made much smaller than before. it is obvious. Further, in the present invention, since the oxide film below the diffusion layer is kept thick as before, the effect of reducing the diffusion layer capacitance, which is a great advantage of the SOI structure device, can be maintained, and the short channel effect can be suppressed.
Subthreshold coefficient reduction, latch-up prevention,
The characteristics of the SOI structure, such as prevention of soft errors due to radiation such as alpha rays and X-rays, are maintained. Further, according to the present invention, SIMOX (Separation by IMp.
Since it was formed by the lanted-OXygen) method, the buried oxide film thickness of both could be easily made different. The thin oxide film below the channel is formed before the field oxide film is formed, and the thick oxide film below the diffusion layer is formed after the gate electrode is formed by self-alignment by oxygen ion implantation using the gate electrode as a mask. The oxide film below the diffusion layer can be formed thinner than the oxide film below the diffusion layer, and the accurate positions of both can be set. Further, since the thick oxide film below the diffusion layer is formed by oxygen ion implantation using the gate electrode having the side wall oxide film as a mask, the influence of lateral ion implantation on the gate oxide film can be eliminated. . In the oxygen ion implantation method using the gate electrode portion as a mask, oxygen ions are also implanted into the field oxide film 15 shown in FIG. As a result, the field oxide film spreads laterally,
If the device is designed in consideration of the spread amount in advance, no adverse effect will occur. A downward spread of the field oxide also occurs, but this does not affect the device characteristics.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. The first embodiment is an n-type ultra-thin SOI structure according to the present invention.
This is an example in which a MOS transistor is prototyped by the SIMOX method. In FIG. 1, reference numeral 11 is a p-type Si (100) substrate. 12 is about 70 keV of oxygen ions on the Si substrate 11.
To 90 keV, about 1 × 10 ¹⁸ to 1.5 × 10 ¹⁸ /
Amount of cm ² , implantation, then from about 1200 ℃ to about 14
It is a buried oxide film formed by applying a heat treatment at 00 ° C. This oxide film has a thickness of about 0.25 μm in the depth direction, centered on a position at a depth of about 0.19 μm from the Si surface.
14 is a Si crystal layer on the buried oxide film 12, that is, SO
It is an I layer and has a thickness of about 65 nm. 15 is LOCOS
(Field oxidation film by the local oxidation of silicon) method. Reference numeral 101 is a gate oxide film formed on the SOI layer by a thermal oxidation method and has a thickness of about 5 to 25 n.
m, 102 is a polysilicon gate electrode layer deposited thereon, and 101 and 102 were processed by ultraviolet lithography or electron beam (EB) lithography. Reference numerals 103 and 104 denote n + diffusion layers formed by implanting arsenic ions on the SOI layer 14 using the gate electrode and the resist film thereon as a mask, which are the source and drain portions of the nMOS transistor, respectively. Reference numeral 105 is a channel portion of the transistor. Further, 13 is, after forming the diffusion layer, using the gate electrode and the resist film thereon as a mask,
Oxygen ions are implanted at about 200 keV in an amount of about 1.5 × 10 ¹⁸ to 2.5 × 10 ¹⁸ / cm ² , and then about 12
It is a buried oxide film formed by applying heat treatment from 00 ° C. to about 1400 ° C. The oxide film is formed in a self-aligned manner and is limited to below the diffusion layers 103 and 104.
It has a thickness of about 0.5 μm in the depth direction centered on a position at a depth of about 0.5 μm from the surface. The resist film thickness is about 1
It was set to 2 μm from μm. The nMOS having the ultra-thin film SOI structure of this embodiment is then subjected to a normal MOS VLSI process.
I made a transistor. According to the present embodiment, the buried oxide film thickness under the source and drain diffusion layers of the MOS transistor is 0.5 μm, whereas the buried oxide film under the channel portion has a thickness of 0.25 μm, which is the conventional value (about 0. 5μ
It is formed much thinner than m). For this reason, the subthreshold coefficient has been reduced and the operating current has been increased compared to the conventional one. Further, even when the device is irradiated with radiation such as X-rays, the generation of positive charges in the oxide film below the channel portion can be significantly reduced as compared with the conventional case, and therefore, much more reliable transistor operation can be realized. Further, since the buried oxide film below the diffusion layer is formed thick as usual, the capacitance of the diffusion layer is kept small.

FIGS. 3 and 4 show the device performance of the nMOS transistor of this embodiment in comparison with the conventional device. The gate length of the sample transistor is 1.25 μm, the gate width is 15 μm, and the drain structure is a normal single drain structure. FIG. 3 is an experimental result of the drain current-gate voltage characteristic of the transistor. In the present invention, the gradient of the subthreshold current is larger than that of the conventional one, so that the subthreshold coefficient value is smaller and the operating current is also larger. This is because the buried oxide film is thin and the gate voltage component applied to the SOI layer of the channel portion increases as described above.

FIG. 4 shows the result of an experiment comparing the fluctuation of the threshold voltage when X-rays are irradiated with the conventional device. The irradiation X-ray generation method is a tube type, and tungsten is used for the target electrode. The average energy of irradiated X-rays is 5 to 15 keV, and the maximum X-ray irradiation dose is 2 × 10.
Up to ⁶ rad. The results show that the device of the present invention can suppress the fluctuation of the threshold value to 1/2 or less as compared with the conventional device,
It is clear that the radiation resistance is greatly improved. This is because the buried oxide film 12 below the channel portion has a thickness of about 0.
This is because the thickness is reduced to 5 μm, the amount of charges generated in the oxide film 12 by X-rays is suppressed to a small amount, and the substrate bias effect due to the charges is reduced.

A second embodiment of the present invention will be described with reference to FIG. The second embodiment is an example in which a CMOS device having an ultra-thin film SOI structure according to the present invention is experimentally manufactured by the SIMOX method. In FIG. 4, 41 is an n-type (100) Si substrate, 4
2 shows oxygen ions on the Si substrate 41 from about 70 keV to 90
It is a buried oxide film formed by implanting in an amount of about 1 × 10 ¹⁸ to 1.5 × 10 ¹⁸ / cm ² at keV, and then performing a heat treatment at about 1200 ° C. to about 1400 ° C. This oxide film has a thickness of about 0.25 μm in the depth direction, centered on a position at a depth of about 0.19 μm from the Si surface. Reference numeral 44 is a Si crystal layer, that is, an SOI layer on the buried oxide film 42, and has a thickness of about 65 nm. After forming the SOI layer, the S
Phosphorus ions are implanted into the OI layer to form an n well.
Next, using the thermal oxide film formed on the n-well as a mask, S
Boron ions are implanted into the OI layer to form a p-well in a self-aligned manner with respect to the n-well to form a double well structure.
Then, a field oxide film 45 is formed by a LOCOS (local oxidation of silicon) method. 401 is the S
A gate oxide film is formed on the OI layer by a thermal oxidation method, its thickness is about 5 to 25 nm, 402 is a polysilicon gate electrode layer deposited thereon, 401
And 402 are ultraviolet lithography or electron beam (E
B) Processed by lithography. 403 and 40
Reference numeral 4 denotes an n + diffusion layer formed by implanting arsenic ions into the p-well using this gate electrode and the resist film on it as a mask, which are the source and drain portions of the nMOS transistor, respectively. 405 is a channel portion of the nMOS transistor. Reference numerals 406 and 407 denote p + diffusion layers formed by implanting boron ions into the n-well using the gate electrode and the resist film thereon as a mask, which are the source and drain portions of the pMOS transistor, respectively. Reference numeral 408 is the channel portion of the pMOS transistor. Further, 43 is a gate electrode and a resist film thereon, which is used as a mask, and subsequently, after forming a diffusion layer, oxygen ions are continuously applied at about 200 keV from about 1.5 × 10 ¹⁸ to 2.5 × 10 ¹⁸ /
Amount of cm ² , implantation, then from about 1200 ℃ to about 14
It is a buried oxide film formed by applying a heat treatment at 00 ° C. This oxide film is self-aligned and n + diffusion layers 403, 4
04 and p + diffusion layers 406 and 407 are formed only below the Si surface and have a thickness of about 0.5 μm in the depth direction centered on a position of about 0.5 μm in depth from the Si surface. The CM according to the present embodiment will be described below according to a normal MOS VLSI process.
An OS device was created. According to this embodiment, n, p
The buried oxide film thickness under the source and drain diffusion layers of both MOS transistors is 0.5 μm, whereas the buried oxide film under the channel portion is 0.25 μm, which is much thinner than the conventional one (about 0.5 μm). Has been formed. Therefore, as in the first embodiment, the subthreshold coefficients of both the n and p MOS transistors are smaller than in the conventional case, and the operating current is improved. As a result, low voltage and high speed CMO
S-circuit operation has been realized. Further, even when the device is irradiated with radiation such as X-rays, the generation of positive charges in the oxide film below the channel portion can be significantly reduced as compared with the conventional one, and C having much higher reliability can be obtained.
MOS device was realized. Further, since the buried oxide film below the diffusion layer is formed thick as usual, the capacitance of the diffusion layer is kept small.

A third embodiment of the present invention will be described with reference to FIG. This embodiment is a prototype of an nMOS transistor having an ultra-thin film SOI structure like the first embodiment. The difference from the first embodiment is that the oxide film below the diffusion layer is formed and the gate electrode having a sidewall oxide film is formed. This is performed by implanting oxygen ions with the mask used as a mask. In FIG. 6, 51 is a p-type S
i (100) substrate, 52 is the substrate 5 as in the first embodiment.
Oxygen ion is about 1 to 70 keV to 90 keV
An amount of × 10 ¹⁸ to 1.5 × 10 ¹⁸ / cm ² , implantation,
It is a buried oxide film formed by applying high temperature heat treatment.
This oxide film has a thickness of about 0.25 μm in the depth direction, centered on a position at a depth of about 0.19 μm from the surface. 54 is S
It is an OI layer and has a thickness of about 65 nm. 55 is a field oxide film. 501 is a gate oxide film, and 502
Is the polysilicon gate electrode layer deposited on it,
Reference numeral 507 denotes a shallow diffusion layer having a low impurity concentration formed by implanting phosphorus ions using this gate electrode as a mask. 5
06 is an HLD (High Temperature Low Pressure Deposi) on the side wall of the gate electrode after the formation of the shallow diffusion layer 507.
is a spacer oxide film deposited by the method (1). Reference numerals 503 and 504 denote n + diffusion layers formed by implanting arsenic ions on the SOI layer 54 using the gate electrode having the sidewall oxide film and the resist film thereon as a mask, which are the source and drain portions of the nMOS transistor, respectively. Reference numeral 505 is a channel portion of the transistor. Further, 53 is formed with diffusion layers 503 and 504 using the gate electrode and the resist film thereon as a mask, and then oxygen ions are continuously applied at about 200 keV from about 1.5 × 10 ¹⁸ to 2.5.
It is a buried oxide film formed by implanting a quantity of × 10 ¹⁸ / cm ² and heat treatment at high temperature. This oxide film is self-aligned and is limited to below the diffusion layer and has a depth of about 0.5 from the surface.
It has a thickness of about 0.5 μm in the depth direction with the position of μm as the center. The resist film thickness was about 1 μm to 2 μm. According to this embodiment, the following new effects are obtained in addition to the effects of the first embodiment described above. That is, in the present embodiment, since the thick oxide film below the diffusion layer is formed by oxygen ion implantation using the gate electrode having the sidewall oxide film as a mask, lateral ion implantation into the gate oxide film can be prevented, and oxygen ions can be prevented. It was possible to prevent the deterioration of the gate oxide film due to the implantation of. The manufacturing method of the buried oxide film of this embodiment can be applied to the second embodiment, and the same effects as the above can be obtained.

[0012]

The present invention relates to SOI-structure MOS transistors and CMOS devices.
The buried oxide film thickness below the channel portion of the transistor is made thinner than before and thinner than the buried oxide film thickness below the diffusion layer. As a result, the subthreshold characteristics and the operating current of the MOS transistor are improved as compared with the conventional one, and the MOS transistor and the CM which have a lower voltage and a higher speed are operated.
OS operation has become possible. Further, even when radiation such as X-rays was applied, charge generation in the buried oxide film below the channel portion was reduced, and the variation in threshold voltage due to this was suppressed to a smaller extent. As a result, more reliable device operation has been realized in the radiation environment such as outer space. The thin buried oxide film below the channel is formed by implanting oxygen ions before forming the field oxide film, and the thick buried oxide film below the diffusion layer is formed by self-alignment by implanting oxygen ions using the gate electrode as a mask. Since it is done at the same time, it is possible to set the exact thickness and position of both.

[Brief description of drawings]

FIG. 1 is a diagram showing an nMOS transistor according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a conventional CMOS device having an ultra-thin film SOI structure.

FIG. 3 is a diagram showing operating performance of an nMOS transistor according to the first embodiment of the present invention.

FIG. 4 is a diagram showing the reliability under the X-ray irradiation condition of the first embodiment of the present invention.

FIG. 5 is a view showing an ultra thin film SOI structure CMOS device according to a second embodiment of the present invention.

FIG. 6 is a diagram showing an nMOS transistor according to a third embodiment of the present invention.

[Explanation of symbols]

11 ... Si substrate, 12 ... Buried oxide film below channel part, 13 ... Buried oxide film below diffusion layer, 14 ... SOI
Layer, 15 ... Field oxide film, 101 ... Gate oxide film,
102 ... Polysilicon gate electrode, 103 ... Source diffusion layer, 104 ... Drain diffusion layer, 105 ... Channel part.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 21/265 J

Claims (5)

[Claims] 1. An MO having a MOS transistor in a single crystal semiconductor thin film formed on a semiconductor substrate with an insulating film interposed therebetween.
In the S-type semiconductor device, the buried insulating film below the channel region of the transistor is formed to be thinner than the buried insulating film below the source and drain regions of the transistor. Characteristic MOS type semiconductor device. 2. A second conductivity type MOS is formed in a first conductivity type region of a single crystal semiconductor thin film formed on a semiconductor substrate via an insulating film.
A MOS type semiconductor device having a transistor and a MOS transistor of the first conductivity type in a second conductivity type region of the semiconductor thin film, the channel region of the MOS transistor of the first conductivity type and the second conductivity type. The MOS type semiconductor is characterized in that the buried insulating film on the side is formed thinner than the thickness of the buried insulating film on the lower side of the source and drain regions of the transistors of the first conductivity type and the second conductivity type. apparatus. 3. A method for forming a buried insulating film below a channel region of a MOS transistor, comprising the step of implanting oxygen ions into a semiconductor substrate before forming a field oxide film. The method for forming a buried insulating film includes the step of implanting oxygen ions into the semiconductor substrate after forming the gate electrode using the gate electrode as a mask, wherein the energy for implanting oxygen ions before forming the field oxide film is equal to the oxygen ion after forming the gate electrode. It is smaller than the implantation energy.
Alternatively, the embedded insulating film manufacturing method of the MOS type semiconductor device according to claim 2. 4. The method according to claim 3, wherein in the oxygen ion implantation after forming the gate electrode, oxygen ions are implanted using the gate electrode and a thick resist film deposited thereon as a mask. 5. Oxygen ion implantation after forming the gate electrode is performed by implanting oxygen ions using a gate electrode having a spacer oxide film on a side wall and a thick resist film deposited thereon as a mask. 4. The manufacturing method according to 4.