JPH0778464A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To eliminate useless operation of an internal circuit for the change in an external address signal and to reduce current consumption by using a mode switching circuit and controlling the fetch of a column address signal with an address control circuit. CONSTITUTION:By the address control circuit 1A, row, column address buffers 2, 3 are controlled with a mode switching signal A outputted from the mode switching circuit 9, and an operation mode is switched. That is, by the circuit 1A, when the signal A is an L level, the external address signal is fetched only when an external CAS signal level is changed to H L as a normal mode. Further, when the signal A is an H level, by the circuit 1A, no useless external address signal is transmitted to the inside as a specific mode. Thus, the useless operation reading out and outputting the information in a memory cell 7 by row, column decoders 4, 5 and an output system control circuit 8, etc., is prevented, and a device reducing current consumption is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as DRAM capable of reducing power consumption.

[0002]

2. Description of the Related Art The structure of a conventional semiconductor memory device will be described with reference to FIG. FIG. 12 shows a conventional general dynamic random access memory (hereinafter, “DR
AM ”. 2) is a block diagram showing the configuration of FIG.

In FIG. 12, 1 is an external / (slash / in this case indicates an overline. The same applies hereinafter). A row address latch signal and a column address latch signal are output by the RAS signal and the external / CAS signal. An address control circuit 2 for receiving an external address signal, a row address buffer controlled by the row address latch signal, and a column address buffer 3 for receiving an external address signal and controlled by the column address latch signal.

Reference numeral 4 is a row decoder connected to the row address buffer 2, 5 is a column decoder connected to the column address buffer 3, and 6 is an address change signal in response to a change in the output signal of the column address buffer 3. Address change detection circuit.

Further, 7 is a memory cell connected to the row decoder 4 and the column decoder 5, and 8 is an output system control circuit connected to the address change detection circuit 6 and the memory cell 7 and including a differential amplifier (sense amplifier). Is. The output system control circuit 8 receives the address change signal and outputs a read signal from the memory cell 7 as an output signal.

Next, the operation of the above-described conventional semiconductor memory device will be described with reference to FIGS. 13 and 14. FIG. 13 shows a general D which is a conventional semiconductor memory device.
6 is a timing chart showing a read timing and an operating current of a RAM. Further, FIG. 14 is a timing chart showing a case where the address is changed several times in the non-specific (Don't care) portion of the external address signal in FIG.

In FIG. 13, (a) shows an external / RAS signal, (b) shows an external / CAS signal, (c) shows an external address signal, and (d) shows a current waveform of the output control circuit 8.

In FIG. 14, (a) is an external / RAS signal, (b) is an external / CAS signal, (c) is an external address signal, (d) is a current waveform of the output control circuit 8, and (e) is. A column address latch signal, (f) shows an address change signal, and (g) shows an output signal of the output system control circuit 8.

In the conventional semiconductor memory device, as shown in FIGS. 13A and 13B, when the external / RAS signal changes from the "H" level to the "L" level, the X address is changed to the external / CAS. When the signal changes from the "H" level to the "L" level, the Y address is taken into the chip.

As shown in FIG. 13D, external / RAS
When the signal changes from the "H" level to the "L" level, a current flows due to the operation of the row system, and when the external / CAS signal changes from the "H" level to the "L" level, the operation of the column system Because of this, current flows.

Further, as shown in FIG.
When the RAS signal changes from the “L” level to the “H” level, a current flows for resetting the row system and the external / CA
When the S signal changes from "L" level to "H" level,
Current flows due to column reset.

As shown in FIG. 13 (c), the external address signal is defined only at the time of fetching the X address and the Y address, and is otherwise unspecified (Don't c).
are).

By the way, since a general DRAM is made to have a specification capable of operating in the first page mode, as shown in FIGS. 14 (a) and 14 (e), external / RA
Some time after the S signal changes from the "H" level to the "L" level, the column address latch signal changes to the "L" level, and the external address signal operates as a column address.

In response to the change of the external address signal, as shown in FIGS. 14C and 14F, the address change signal outputs a one-shot pulse every time the external address signal changes, and the output system control circuit. It is transmitted to 8.

The output system control circuit 8 re-reads the internal data each time it receives the pulse of the address change signal from the address change detection circuit 6, and therefore, as shown in FIGS. 14 (b) and 14 (g), When the external / CAS signal changes from "H" to "L", the output signal (Dout) can be obtained after the time of t _CAC (CAS access).

However, as shown in FIGS. 14C, 14D and 14E, when the external address signal changes many times during the column address acceptance period, the output system control circuit 8 operates each time, In addition to the current caused by the row-related and column-related operations described above, a consumed current flows when the external address signal changes.

The differential amplifier (sense amplifier) included in the output system control circuit 8 of the conventional semiconductor memory device described above will be described with reference to FIG. Figure 15
FIG. 4 is a circuit diagram showing a current mirror type differential amplifier that is often used to amplify a minute potential difference in a conventional semiconductor memory device.

In FIG. 15, Q ₁ , Q ₂ , Q ₅ , Q ₆ , Q
₁₀ and Q ₁₁ are P-channel MOS transistors, Q ₃ ,
Q ₄ , Q ₇ , Q ₈ , Q ₉ , Q ₁₂ , Q ₁₃ and Q ₁₄ are N-channel MOS transistors.

When the activation signal φ (corresponding to the address change signal described above) is at "H" level, "" is applied to the output terminal according to the difference in voltage level between the input signals C and / C. It outputs an "H" level or an "L" level. The characteristic of this current mirror type differential amplifier is that when the activation signal φ is at the “H” level,
When the signal level of C changes, it operates so that a voltage corresponding to that value appears at the output terminal. Although this is a static differential amplifier, it has the drawback of a large operating current.

[0020]

In the conventional semiconductor memory device as described above, when the external address signal is operated so as to change more than necessary within the operating specifications, a large number of operations are performed as compared with the normal operation. There was a problem that current flows.

Further, the current mirror type differential amplifier in the conventional semiconductor memory device has a problem that the operating current is large.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor memory device capable of preventing an operation current from flowing more than necessary by switching operation modes.

Another object of the present invention is to obtain a semiconductor memory device which can minimize the access penalty in the page mode by using it together with another mode switching signal.

[0024]

A semiconductor memory device according to claim 1 of the present invention comprises the following means. [1] Mode switching means for generating a mode switching signal. [2] A column address latch signal is output only when the external / CAS signal changes from a high level to a low level based on the mode switching signal and the external / RAS signal, and based on the external / RAS signal and the external / CAS signal. Address control means for outputting a row address latch signal. [3] Address buffer means for fetching an external address signal as a column address based on the column address latch signal. [4] Address change detection means for outputting an address change signal when the column address is fetched. [5] Output system control means for reading information in the memory cells arranged in a matrix based on the address change signal by using the row address and the column address.

A semiconductor memory device according to a second aspect of the present invention comprises the following means. [1] Mode switching means for generating first and second mode switching signals. [2] Column address when the external / CAS signal first changes from a high level to a low level based on the first and second mode switching signals and the external / RAS signal, and then changes from a low level to a high level Latch signal is output, and the external / RAS signal and external / C
Address control means for outputting a row address latch signal based on the AS signal. [3] Address buffer means for fetching an external address signal as a column address based on the column address latch signal. [4] Address change detection means for outputting an address change signal when the column address is fetched. [5] Output system control means for reading information in the memory cells arranged in a matrix based on the address change signal by using the row address and the column address.

A semiconductor memory device according to claim 3 of the present invention comprises the following means. [1] Mode switching means for generating a mode switching signal. [2] A column address latch signal is output when the external / CAS signal changes from a high level to a low level based on the mode switching signal and the external / RAS signal,
Address control means for outputting a row address latch signal based on the external / RAS signal and the external / CAS signal. [3] Address buffer means for fetching an external address signal as a column address based on the column address latch signal. [4] Address change detection means for outputting an address change signal when the column address is fetched. [5] Output system control means including a latch-type differential amplifier for reading information in memory cells arranged in a matrix based on the address change signal by using a row address and the column address.

A semiconductor memory device according to a fourth aspect of the present invention is provided with the following means, and when operating as an X1 device, only a differential amplifier that reads out one bit of data operates. [1] Mode switching means for generating a mode switching signal. [2] A column address latch signal is output when the external / CAS signal changes from a high level to a low level based on the mode switching signal and the external / RAS signal,
Address control means for outputting a row address latch signal based on the external / RAS signal and the external / CAS signal. [3] Address buffer means for fetching an external address signal as a column address based on the column address latch signal. [4] Address change detection means for outputting an address change signal when the column address is fetched. [5] Output system control means including a differential amplifier for reading information in the memory cells arranged in a matrix based on the address change signal by using the row address and the column address.

A semiconductor memory device according to claim 5 of the present invention comprises the following means. [1] Mode switching means for generating a mode switching signal by special timing of WCbR and applying a voltage higher than an external power supply voltage to a specific terminal of an external address. [2] A column address latch signal is output when the external / CAS signal changes from a high level to a low level based on the mode switching signal and the external / RAS signal,
Address control means for outputting a row address latch signal based on the external / RAS signal and the external / CAS signal. [3] Address buffer means for fetching an external address signal as a column address based on the column address latch signal. [4] Address change detection means for outputting an address change signal when the column address is fetched. [5] Output system control means for reading information in the memory cells arranged in a matrix based on the address change signal by using the row address and the column address.

[0029]

In the semiconductor memory device according to the first aspect of the present invention, the mode switching signal is generated by the mode switching means. Also, by the address control means,
The column address latch signal is output only when the external / CAS signal changes from the high level to the low level based on the mode switching signal and the external / RAS signal, and the row address latch based on the external / RAS signal and the external / CAS signal. The signal is output. Further, the address buffer means captures an external address signal as a column address based on the column address latch signal, and the address transition detecting means outputs an address transition signal when the column address is captured.
Then, the output system control means reads the information in the memory cells arranged in a matrix based on the address change signal by using the row address and the column address.

In the semiconductor memory device according to the second aspect of the present invention, the mode switching means generates the first and second mode switching signals. Further, when the external / CAS signal first changes from the high level to the low level based on the first and second mode switching signals and the external / RAS signal, the address control means changes from the low level to the high level thereafter. At this time, the column address latch signal is output, and the row address latch signal is output based on the external / RAS signal and the external / CAS signal. Further, the address buffer means captures an external address signal as a column address based on the column address latch signal, and the address transition detecting means outputs an address transition signal when the column address is captured. Then, the output system control means reads the information in the memory cells arranged in a matrix based on the address change signal by using the row address and the column address.

In the semiconductor memory device according to the third aspect of the present invention, the mode switching signal is generated by the mode switching means. The address control means outputs a column address latch signal when the external / CAS signal changes from a high level to a low level based on the mode switching signal and the external / RAS signal, and the external / RAS signal and the external / CAS signal are output. A row address latch signal is output based on the signal. Further, the address buffer means captures an external address signal as a column address based on the column address latch signal, and the address transition detecting means outputs an address transition signal when the column address is captured. Then, the output system control means including the latch type differential amplifier reads information in the memory cells arranged in a matrix form based on the address change signal by using the row address and the column address.

In the semiconductor memory device according to the fourth aspect of the present invention, the mode switching signal is generated by the mode switching means. The address control means outputs a column address latch signal when the external / CAS signal changes from a high level to a low level based on the mode switching signal and the external / RAS signal, and the external / RAS signal and the external / CAS signal are output. A row address latch signal is output based on the signal. Further, the address buffer means captures an external address signal as a column address based on the column address latch signal, and the address transition detecting means outputs an address transition signal when the column address is captured. Then, the information in the memory cells arranged in a matrix based on the address change signal is read by the output system control means including a differential amplifier by using the row address and the column address, and as an X1 device. When operating, only the differential amplifier that reads 1-bit data operates.

In the semiconductor memory device according to the fifth aspect of the present invention, the mode switching means generates the mode switching signal by the special timing of the WCbR and by applying a voltage higher than the external power supply voltage to the specific terminal of the external address. To be done. Also, by the address control means,
A column address latch signal is output when the external / CAS signal changes from a high level to a low level based on the mode switching signal and the external / RAS signal, and a row address latch based on the external / RAS signal and the external / CAS signal. The signal is output. Further, the address buffer means captures an external address signal as a column address based on the column address latch signal, and the address transition detecting means outputs an address transition signal when the column address is captured. Then, the output system control means reads the information in the memory cells arranged in a matrix based on the address change signal by using the row address and the column address.

[0034]

【Example】

Example 1. The configuration of the first embodiment of the present invention will be described with reference to FIGS. 1, 2 and 3. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, and the row address buffer 2 to the output system control circuit 8 are the same as those of the conventional device described above. Further, FIG. 2 shows a first embodiment of the present invention.
It is a figure which shows the structure of the mode switching circuit of. further,
FIG. 3 is a diagram showing the configuration of the address control circuit according to the first embodiment of the present invention. In each figure, the same reference numerals indicate the same or corresponding parts.

In FIG. 1, 1A is an address control circuit,
A mode switching circuit 9 outputs a mode switching signal A. The mode switching signal A is used to control the column address latch signal.

In FIG. 2, 11 is a pad (PAD),
12 is a capacitance (C), 13 is a transistor, 14 and 15
Is an inverter. ND is a node.

In FIG. 3, 16 is an inverter to which an external / RAS signal is input, 17 is a delay element having an even number of stages and having a delay amount a, 18 is an inverter, 19 is a NAND gate, 20 is an inverter, and 21 is an even stage. A delay element having a delay amount b, 22 is a NOR gate, and 23 is a NAN.
D gates, 24 and 25 are inverters, 26 and 27 are NOR gates, 28 is a NOR gate, and 29 and 30 are inverters. The generation circuit of the row address latch signal is omitted.

By the way, the mode switching means according to claim 1 of the present invention corresponds to the mode switching circuit 9 in the first embodiment, and the address control means according to claim 1 of the present invention addresses the address in the first embodiment. The address buffer means according to claim 1 of the present invention corresponds to the column address buffer 3 in the first embodiment, and the address change detecting means according to claim 1 of the present invention corresponds to the control circuit 1A. 1 corresponds to the address change detection circuit 6, and the output system control means according to claim 1 of the present invention comprises a row address buffer 2, a row decoder 4, a column decoder 5 and an output system control circuit 8 in the first embodiment. Has been done.

Next, the operation of the above-described first embodiment will be described with reference to FIGS. 4 and 5. FIG. 4 is a timing chart showing the operation of the first embodiment of the present invention, showing the timing when the mode switching signal A is fixed at the "H" level. FIG. 5 is a timing chart showing the operation of the address control circuit 1A according to the first embodiment of the present invention.

In FIG. 4, (a) is an external / RAS signal, (b) is an external / CAS signal, (c) is an external address signal, (d) is a current waveform of the output control circuit 8, and (e) is. A column address latch signal, (f) shows an address change signal, and (g) shows an output signal of the output system control circuit 8.

In FIG. 5, (a) is a mode switching signal A, (b) is an external / RAS signal, and (c) is an external / CA.
S signal, (d) signal of node NE, (e) node N
The F signal and (f) represent the column address latch signal, respectively.

First, the operation of the mode switching circuit 9 will be described. When the pad 11 is in a floating state, when the power is turned on, the node ND becomes "H" level due to the capacitor 12, so that the mode switching signal A is at "H" level. On the other hand, when the pad 11 is wired to the ground, the node ND becomes the "L" level, so the mode switching signal A is the "L" level.

In the conventional operation, after the external / RAS signal changes from the "H" level to the "L" level, the column address latch signal changes to the "L" level after a while to accept the column address. However, in the first embodiment, as shown in FIGS.
Immediately after the external / CAS signal changes from the "H" level to the "L" level, the column address latch signal changes to the "L" level and operates to receive the column address.

Therefore, even if the external address signal changes more than necessary, it is possible to obtain the signals shown in FIGS. 4C, 4E, 4F and 4G.
As shown in, the internal column address does not change, and the address change signal outputs a one-shot pulse only when the column address latch signal is at the “L” level, that is, when the Y address is fetched, and the output signal (Dout). Is obtained. Therefore, since the output system control circuit 8 operates in response to the pulse of the address change signal, the output system control circuit 8 operates only once, and an unnecessary operating current does not flow.

That is, the mode switching signal A is "L".
In the case of the level, as shown in the left half of FIG. 5, the signal at the node NE rises after being delayed by the delay amount a after the external / RAS signal changes from the “H” level to the “L” level, The CAS signal changes from "H" level to "L"
It falls when it changes to a level. As a result, the column address acceptance period of the column address latch signal is long.

On the other hand, when the mode switching signal A is at "H" level, as shown in the right half of FIG.
The F signal rises immediately after the external / CAS signal changes from the “H” level to the “L” level while the external / RAS signal is at the “L” level, and falls after a delay of the delay amount b. As a result, the column address acceptance period of the column address latch signal is short.

The first embodiment of the present invention, as described above,
Information in the memory cells 7 arranged in a matrix is
A semiconductor memory device comprising an address control circuit 1A for performing a read operation using a row address signal and a column address signal, and controlling the row address signal and the column address signal based on the external / RAS signal and the external / CAS signal,
The address control circuit 1A is controlled by the mode switching signal A output from the mode switching circuit 9, and the external address signal is supplied only when the external / CAS signal changes from "H" level to "L" level during a normal read operation. The column address is fetched.

In the first embodiment, the operation mode is controlled by the mode switching circuit 9, that is, when the mode switching signal A is at "L" level, it is the normal mode, and when the mode switching signal A is at "H" level. Special mode,
This is to prevent an unnecessary change in the external address signal from being transmitted to the internal circuit, thereby eliminating an unnecessary operating current.

That is, the first embodiment is intended to realize an operation mode (special mode) in which current consumption during operation is reduced. Therefore, by changing the timing of fetching the column address by using the mode switching circuit 9, unnecessary operation of the internal circuit against the change of the external address signal is prevented and the useless operating current due to this is eliminated. A device with low current consumption can be obtained.

Example 2. In the first embodiment described above, it is possible to use one mode switching circuit to greatly reduce the operating current, but the access time from the external / CAS signal is delayed. As shown in FIG. 4, immediately after the external / CAS signal changes from the “H” level to the “L” level, the external address signal starts to be taken in, and the output system control circuit 8 starts to operate in order to read the internal information therefrom. .

Since this causes the output signal to be read, the time (t _CAC ) from the external / CAS signal becomes equal to the access time (t _CAA ) from the change in address (generally, t _{CAC as} shown in FIG. 14). ≈t _CAA / 2). In the second embodiment, high-speed reading is performed in the special mode in order to prevent this access delay.

The configuration of the second embodiment of the present invention will be described with reference to FIGS. 6 and 7. FIG. 6 is a block diagram showing the configuration of the second embodiment of the present invention, and the row address buffer 2 to the output system control circuit 8 are the same as those of the conventional device described above. FIG. 7 is a diagram showing the configuration of the address control circuit according to the second embodiment of the present invention.

In FIG. 6, 1B is an address control circuit,
Reference numeral 9 is a mode switching circuit that outputs a mode switching signal A, and 10 is a mode switching circuit that outputs a mode switching signal B. The mode switching circuits 9 and 10
The configuration is similar to that of the mode switching circuit of the first embodiment described above, and the mode switching signals A and B are used to control the column address latch signal.

In FIG. 7, reference numeral 31 is an inverter, 32 is a NOR gate, 33 is an inverter, 34 is a NAND gate, 35 is a delay element having an even number of stages and a delay amount of c.
6 is an inverter, 37 is a NAND gate, 38 is an inverter, 39 is an inverter, and 40 and 41 are clocked Cs.
It is MOS.

42 is an inverter, 43 and 44 are NOR gates, 45 is a NOR gate, 46 is an inverter, 47 is a delay element having an even number of stages and a delay amount b, 4
8 is a NOR gate, 49 is a NAND gate, 50 is an inverter, and 51 is a NOR gate.

Further, 52 is a delay element having an even number of stages and having a delay amount a, 53 is an inverter, 54 is a NAND gate, 55 is a NOR gate, 56 is a NOR gate, and 57 and 58 are inverters.

By the way, the mode switching means according to claim 2 of the present invention is composed of the mode switching circuits 9 and 10 in this embodiment 2, and the address control means according to claim 2 of the present invention is the same as this embodiment 2. Corresponds to the address control circuit 1B, the address buffer means according to claim 2 of the present invention corresponds to the column address buffer 3 in the second embodiment, and the address change detection means according to claim 2 of the present invention corresponds to In the second embodiment, the address change detection circuit 6
The output system control means according to claim 2 of the present invention comprises a row address buffer 2, a row decoder 4, a column decoder 5 and an output system control circuit 8 in the second embodiment.

Next, the operation of the above-described second embodiment will be described with reference to FIGS. 8, 9 and 10. Figure 8
Is the mode switching signal A in the second embodiment of the present invention.
Is a timing chart showing an operation when is at "H" level and the mode switching signal B is at "L" level. Also,
FIG. 9 is a timing chart showing the operation when the mode switching signals A and B are both at the "H" level in the second embodiment of the present invention. Further, FIG. 10 is a timing chart showing the operation of the address control circuit 1B according to the second embodiment of the present invention.

In FIG. 8, (a) is an external / RAS signal, (b) is an external / CAS signal, (c) is an external address signal, (d) is an output signal of the output system control circuit 8, and (e) is. A column address latch signal and (f) are address change signals, respectively.

In FIG. 9, (a) is an external / RAS signal, (b) is an external / CAS signal, (c) is an external address signal, (d) is an output signal of the output system control circuit 8, and (e) is. A column address latch signal and (f) are address change signals, respectively.

In FIG. 10, (a) is a mode switching signal A, (b) is a mode switching signal B, (c) is an external / RAS signal, (d) is an external / CAS signal, and (e) is a node NG. Signal, (f) is a signal of the node NH, (g) is a signal of the node NJ (= external / CAS signal), (h) is a signal of the node NK, and (i) is a column address latch signal.

First, the case where the mode switching signal A is at "H" level and the mode switching signal B is at "L" level will be described. FIG. 8 shows the operation in the page mode, which is exactly the same as the operation of the first embodiment shown in FIG. That is, as shown in FIG. 8, when the external / CAS signal changes from the "H" level to the "L" level, the column address is taken in, and the output system control circuit 8 starts to operate from there. Output signal (Dout1,
As in the first embodiment, the time until the address access (t _CAA ) is required until 2 and 3) appear. That is, access speed has not yet been increased.

Next, the case where both the mode switching signals A and B are at the "H" level will be described. As shown in FIG. 9, when the external / CAS signal changes from the “H” level to the “L” level for the first time after the external / RAS signal falls from the “H” level to the “L” level, the first embodiment is performed. Similarly, the column address is taken in immediately after the external / CAS signal falls to the “L” level, and the output system control circuit 8 operates,
After the address access time (t _CAA ) has passed, the output signal (Dout1) is obtained.

Subsequently, when the external / CAS signal changes from the "L" level to the "H" level while the external / RAS signal is kept at the "L" level, as shown in FIG. 9 (e). The column address latch signal again changes to the “L” level to fetch the column address, and the output system control circuit 8 starts operating.

When the external / CAS signal changes from the "H" level to the "L" level again, only the data already read internally is output.
CAS access time (t
_The output signal (Dout2) is obtained after _CAC .

Similarly, the column address corresponding to the third output is fetched by the change of the next external / CAS signal from the "L" level to the "H" level, and from the next "H" level of the external / CAS signal. The output signal (Dout3) can be output at the CAS access time (t _CAC ) when changing to the “L” level.

If the next read is not planned,
When the external / CAS signal changes from the “L” level to the “H” level, the output system control circuit 8 operates by fetching an appropriate column address. However, as shown in FIG.
If the external / RAS signal changes from the “L” level to the “H” level before the AS signal changes from the “H” level to the “L” level, the output signal is output because all resets are applied at that time. However, the internal circuit is also reset.

That is, the mode switching signal A is "H".
At the level, when the mode switching signal B is at the "L" level, as shown in the left half of FIG. 10, when the external / CAS signal changes from the "H" level to the "L" level, the column address latch signal (" L "level) is output.

When the mode switching signal A is "H" level and the mode switching signal B is "H" level,
As shown in the right half of FIG. 10, the first column address latch signal (“L” level) is output when the external / CAS signal changes from “H” level to “L” level, and the second column address latch signal (“L” level) is output. Subsequent column address latch signals are external / C
It is output when the AS signal changes from "L" level to "H" level.

Such a page mode is often used as a high speed access mode, and the bit length read at one time tends to be long. When the operation mode as shown in the second embodiment is used, the access of the first bit is slightly delayed, and the reading of subsequent bits is not delayed. Furthermore, the current consumption can be significantly reduced, and low power consumption and high speed operation can be achieved.

The second embodiment of the present invention, as described above,
Information in the memory cells 7 arranged in a matrix is
A semiconductor memory device in which reading is performed using a row address signal and a column address signal, and the control of the row address signal and the column address signal is controlled by an address control circuit 1B controlled by an external / RAS signal and an external / CAS signal. In the above, the address control circuit 1B is controlled by the mode switching signal A output from the mode switching circuit 9 and the mode switching signal B output from the mode switching circuit 10, so that when the page mode read operation is performed, / CAS
When the signal first changes from the "H" level to the "L" level, the external address signal is taken in as the column address to perform the internal operation, and thereafter, the "L" level of the external / CAS signal is changed to the "H" level. It is provided with an operation mode in which the external address signal is taken in as a column address when changing to a level and the internal operation is sequentially performed.

In the second embodiment, by using together with another mode switching circuit 10, the address fetch timing is changed so as to minimize the access penalty during the page mode operation.

Example 3. A third embodiment of the present invention will be described with reference to FIG. FIG. 11 is a circuit diagram showing a differential amplifier (sense amplifier) included in the output system control circuit 8A according to the third embodiment of the present invention. In addition, this Example 3
The configuration of Example 1 is the same as that of the first embodiment except the output system control circuit 8A.
Alternatively, it is similar to the second embodiment.

In FIG. 11, Q ₁₅ , Q ₁₆ , Q ₁₇ and Q
₁₈ is a P channel MOS transistor, Q ₁₉ , Q ₂₀ , Q
₂₁ , Q ₂₂ and Q ₂₃ are N-channel MOS transistors.

The circuit shown in FIG. 11 is a cross-couple type differential amplifier (sense amplifier), and an activation signal φ (corresponding to the address change signal described in the first and second embodiments).
The difference between the voltage levels of the input signals C and / C at the time when the signal goes to the "H" level, the "H" level or "L" level signal is output to the output terminal, and then the input signals C and / C are output.
The value of the output does not change even if the value of is changed unless the activation signal φ returns to the "L" level. That is, it is a differential amplifier that operates dynamically.

The dynamically operating differential amplifier (sense amplifier) means that there is a precharge time and an operation time. That is, when the column address changes continuously, data must be output according to the change, and the precharge period and the operation period cannot be separated. Therefore, the dynamic differential amplifier cannot be used. On the other hand, if the column address does not change continuously, it is possible to precharge immediately after reading once.

In the circuit corresponding to the first page mode as shown in the conventional example, the differential amplifier as shown in FIG. 11 cannot be used because it operates so as to read the internal signal every time the column address changes. It is the input signal C,
Since it is not known when / C changes, it is unavoidable to use a current mirror type differential amplifier that consumes a large amount of current.

Since the column address does not change continuously in the operation of the column address latch signal as shown in the first and second embodiments, the dynamic latch type differential amplifier (sense) shown in FIG. Amplifier) can be used. The differential amplifier as shown in FIG. 11 consumes less current and has the same sensitivity as that of the current mirror type differential amplifier shown in FIG. 15, so that the differential amplifier is the same as the semiconductor memory device shown in the first or second embodiment. If used together, a device that operates with lower current consumption can be obtained.

That is, in the third embodiment of the present invention, as described above, the information in the memory cells 7 arranged in a matrix is read by using the row address signal and the column address signal, and the row address signal is read. In the semiconductor memory device in which the control of the column address signal is controlled by the address control circuits 1A and 1B controlled by the external / RAS signal and the external / CAS signal, the external / CAS signal is changed from "H" level to "L". It is controlled so that the external address signal is taken in as the column address only when the level or the "L" level changes to the "H" level. , A latch type differential amplifier (sense amplifier).

Example 4. In a typical DRAM,
Even for X1 products (devices that output only 1 bit), 4-bit data is read at the same time as an internal operation (4
The differential amplifiers are operated. ) It corresponded to nibble mode, but there are very few users who read using nibble mode, so there is no need to support nibble mode itself. Therefore, in the case of the X1 product, it is possible to further lower the operating current by reading only 1-bit data as an internal operation, that is, by operating only one differential amplifier. The configuration of the fourth embodiment is the same as that of the first, second or third embodiment described above except the above.

That is, in the fourth embodiment of the present invention, the information in the memory cells 7 arranged in a matrix is read by using the row address signal and the column address signal, and the row address signal and the column address signal are controlled. But outside /
In the semiconductor memory device controlled by the address control circuits 1A and 1B controlled by the RAS signal and the external / CAS signal, the output system control circuits 8 and 8A are controlled by the mode switching signal A output from the mode switching circuit 9. 1 when operating as an X1 device
Only the differential amplifier that reads out data for bits operates.

Example 5. In each of the above embodiments, a bonding pad is separately provided as the mode switching circuit 9, and the mode switching signal A is output by wiring the pad to the power supply voltage level or the ground level. However, in the fourth embodiment, WCbR (timing to set external / WE signal and / CAS signal to "L" level before / RAS signal) + mode switching signal A by applying a voltage higher than the power supply voltage level to a specific external address signal To do. The configuration of the fifth embodiment is the same as that of the above-described respective embodiments except the mode switching circuit.

That is, in the fifth embodiment of the present invention, the information in the memory cells 7 arranged in a matrix is read by using the row address signal and the column address signal, and the row address signal and the column address signal are controlled. But outside /
In the semiconductor memory device controlled by the address control circuits 1A and 1B controlled by the RAS signal and the external / CAS signal, the address control circuits 1A and 1B are controlled by the mode switching signals A and B output from the mode switching circuit, External / CAS
When the signal changes, the external address signal operates so as to be fetched as the column address, and the mode switching circuit operates as the W
It is configured by applying a special timing of CbR and applying a voltage higher than the external power supply voltage to the specific terminal of the external address.

[0084]

As described above, in the semiconductor memory device according to the first aspect of the present invention, the mode switching means for generating the mode switching signal and the external / CAS signal are generated based on the mode switching signal and the external / RAS signal. The column address latch signal is output only when the high level is changed to the low level, and the external / RAS signal and the external / RAS signal are output.
Address control means for outputting a row address latch signal based on the CAS signal, address buffer means for taking in an external address signal as a column address based on the column address latch signal, and an address change signal when taking in the column address. Since the address change detection means and the output system control means for reading the information in the memory cells arranged in a matrix form based on the address change signal by using the row address and the column address are provided, the column address signal It is possible to control the capture of the output current and to eliminate the operation of the output system except when necessary, thereby significantly reducing the operating current.

As described above, the semiconductor memory device according to the second aspect of the present invention includes the mode switching means for generating the first and second mode switching signals, the first and second mode switching signals and the external device. A column address latch signal is output when the external / CAS signal first changes from the high level to the low level based on the / RAS signal and then changes from the low level to the high level, and the external / RAS signal and the external / CAS signal are output. Address control means for outputting a row address latch signal based on the signal,
Address buffer means for taking in an external address signal as a column address based on the column address latch signal, address change detecting means for outputting an address change signal when taking in the column address, and arranged in a matrix form based on the address change signal. Since the output system control means for reading the information in the stored memory cell by using the row address and the column address is provided, it is possible to control the capture of the column address signal and eliminate the operation of the output system except when necessary. This has the effect of significantly reducing the operating current. Further, the timing of fetching the column address signal can be changed, and the delay of access to the output can be prevented.

As described above, in the semiconductor memory device according to the third aspect of the present invention, the external / CAS signal is at a high level based on the mode switching means for generating the mode switching signal and the mode switching signal and the external / RAS signal. From the external / RAS signal and the external / CA signal.
Address control means for outputting a row address latch signal based on the S signal, address buffer means for taking in an external address signal as a column address based on the column address latch signal, and an address change signal when taking in the column address. Address change detection means and output system control means including a latch type differential amplifier for reading out information in memory cells arranged in a matrix based on the address change signal using a row address and the column address. Since it is provided, it is possible to control the fetching of the column address signal, and it is possible to significantly reduce the operating current by eliminating the operation of the output system except when necessary. Further, the timing of fetching the column address signal can be changed, and the delay of access to the output can be prevented.

As described above, in the semiconductor memory device according to the fourth aspect of the present invention, the external / CAS signal is at a high level based on the mode switching means for generating the mode switching signal and the mode switching signal and the external / RAS signal. From the external / RAS signal and the external / CA signal.
Address control means for outputting a row address latch signal based on the S signal, address buffer means for taking in an external address signal as a column address based on the column address latch signal, and an address change signal when taking in the column address. An address change detection means and an output system control means including a differential amplifier for reading information in memory cells arranged in a matrix based on the address change signal using a row address and the column address, When operating as an X1 device, only the differential amplifier that reads 1-bit data operates, so the column address signal can be controlled and the operating current can be greatly increased by eliminating the operation of the output system except when necessary. The effect that can be reduced to. Further, the timing of fetching the column address signal can be changed, and the delay of access to the output can be prevented.

As described above, the semiconductor memory device according to the fifth aspect of the present invention generates the mode switching signal by the special timing of WCbR and by applying the voltage higher than the external power supply voltage to the specific terminal of the external address. A column address latch signal is output when the external / CAS signal changes from a high level to a low level based on the mode switching means and the mode switching signal and the external / RAS signal, and the external / RAS signal and the external / CAS signal are output.
Address control means for outputting a row address latch signal based on a signal, address buffer means for capturing an external address signal as a column address based on the column address latch signal, and an address for outputting an address change signal when capturing the column address Since the change detection means and the output system control means for reading out the information in the memory cells arranged in a matrix based on the address change signal by using the row address and the column address are provided, the column address signal It is possible to control the capturing, and it is possible to significantly reduce the operating current by eliminating the operation of the output system except when necessary. Further, the timing of fetching the column address signal can be changed, and the delay of access to the output can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a mode switching circuit according to a first embodiment of the present invention.

FIG. 3 is a diagram showing the configuration of an address control circuit according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the address control circuit according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of an address control circuit according to a second embodiment of the present invention.

FIG. 8 is a timing chart showing the operation of the second embodiment of the present invention.

FIG. 9 is a timing chart showing the operation of the second embodiment of the present invention.

FIG. 10 is a timing chart showing the operation of the address control circuit according to the second embodiment of the present invention.

FIG. 11 is a diagram showing the configuration of a differential amplifier included in the output system control circuit according to the third embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a conventional semiconductor memory device.

FIG. 13 is a timing chart showing an operation of a conventional semiconductor memory device.

FIG. 14 is a timing chart showing an operation of a conventional semiconductor memory device.

FIG. 15 is a diagram showing a configuration of a differential amplifier included in an output system control circuit of a conventional semiconductor memory device.

[Explanation of symbols]

 1A, 1B Address control circuit 2 Row address buffer 3 Column address buffer 4 Row decoder 5 Column decoder 6 Address change detection circuit 7 Memory cell 8 Output system control circuit 9 Mode switching circuit 10 Mode switching circuit

Claims (5)

[Claims] 1. A mode switching means for generating a mode switching signal, said mode switching signal and external / RAS.
An address control unit that outputs a column address latch signal only when the external / CAS signal changes from a high level to a low level based on the signal, and outputs a row address latch signal based on the external / RAS signal and the external / CAS signal. Address buffer means for taking in an external address signal as a column address based on the column address latch signal, address change detecting means for outputting an address change signal when taking in the column address, and arranged in a matrix form based on the address change signal. A semiconductor memory device comprising an output system control means for reading information in a memory cell using a row address and the column address. 2. A mode switching means for generating first and second mode switching signals, and an external / C based on the first and second mode switching signals and an external / RAS signal.
A column address latch signal is output when the AS signal first changes from the high level to the low level and then changes from the low level to the high level.
Address control means for outputting a row address latch signal based on the S signal and the external / CAS signal, address buffer means for fetching an external address signal as a column address based on the column address latch signal, and an address change signal when fetching the column address Is provided, and output system control means for reading information in the memory cells arranged in a matrix based on the address change signal by using the row address and the column address. And semiconductor memory device. 3. A mode switching means for generating a mode switching signal, said mode switching signal and external / RAS.
An address control unit that outputs a column address latch signal when the external / CAS signal changes from a high level to a low level based on the signal, and outputs a row address latch signal based on the external / RAS signal and the external / CAS signal, Address buffer means for taking in an external address signal as a column address based on the column address latch signal, address change detecting means for outputting an address change signal when taking in the column address, and arranged in a matrix form based on the address change signal. A semiconductor memory device comprising: output system control means including a latch type differential amplifier for reading information in a memory cell using a row address and the column address. 4. A mode switching means for generating a mode switching signal, said mode switching signal and external / RAS.
An address control unit that outputs a column address latch signal when the external / CAS signal changes from a high level to a low level based on the signal, and outputs a row address latch signal based on the external / RAS signal and the external / CAS signal, Address buffer means for taking in an external address signal as a column address based on the column address latch signal, address change detecting means for outputting an address change signal when taking in the column address, and arranged in a matrix form based on the address change signal. Only the differential amplifier which reads out the information in the memory cell by using the row address and the column address and has an output system control means including a differential amplifier, and reads out one bit of data when operating as an X1 device Is characterized by The semiconductor memory device. 5. A mode switching means for generating a mode switching signal by special timing of WCbR and applying a voltage higher than an external power supply voltage to a specific terminal of an external address, and an external device based on the mode switching signal and an external / RAS signal. Outputs a column address latch signal when the / CAS signal changes from high level to low level,
Address control means for outputting a row address latch signal based on the external / RAS signal and the external / CAS signal;
Address buffer means for taking in an external address signal as a column address based on the column address latch signal, address change detecting means for outputting an address change signal when taking in the column address, and arranged in a matrix form based on the address change signal. A semiconductor memory device comprising an output system control means for reading information in a memory cell using a row address and the column address.